Bit Logic Instructions
5.5 Instructions for Transitional Contacts: FP, FN
You can use the Edge Positive (FP) and Edge Negative (FN) instructions like transition-sensing contacts in a relay circuit. These instructions detect and react to transitions in the result of logic operation. A transition from 0 to 1 is called a “positive edge.” A transition from 1 to 0 is called a “negative edge”
(see Figure 5-6).
Figure 5-6 Representation of Positive and Negative Edges
Figure 5-7 shows a statement list that enables your program to react to a positive edge transition. An explanation follows the figure.
1
OB1 Scan Cycle No.:
I 1.0
Figure 5-7 Programming a Reaction to a Positive Edge Transition
If the programmable logic controller detects a positive edge at contact I 1.0, it energizes the coil at Q 4.0 for one OB1 scan cycle. The programmable logic controller stores the result of the logic operation performed by the A instruction in edge memory bit M 1.0 and compares it to the RLO from the previous scan cycle. (In the example in Figure 5-7, the RLO of the statement
“A I 1.0” just happens to be the same as the signal state of input I 1.0. This will not be the case for every program.) If the current RLO is 1 and the RLO from the previous scan cycle stored in memory bit M 1.0 is 0, then the FP statement sets the RLO to 1. The FP statement detects a positive edge at the contact (that is, the signal state of the RLO changed from 0 to 1). If there is no change in the RLO (current RLO and previous RLO stored in the edge memory bit are both equal to 0 or 1), then the FP statement resets the RLO to 0.
Description
Reacting to a Positive Edge Bit Logic Instructions
Table 5-9 Checking for Positive Edge Transition at Input I 1.0
Table 5-9 applies specifically to the statement list program shown in
Figure 5-7. In general, you should consider the transitions detected by FP and FN to be transitions reflected in the RLO, not in the signal states of contacts.
For example, a logic string can form an RLO that is not directly related to the signal state of a contact.
Figure 5-8 shows a statement list that enables your program to react to a negative edge transition. An explanation follows the figure.
I 1.0
Figure 5-8 Programming a Reaction to a Negative Edge Transition
If the programmable logic controller detects a negative edge at contact I 1.0, it energizes the coil at Q 4.0 for one OB1 scan cycle.
The programmable logic controller stores the result of the logic operation Reacting to a
Negative Edge
Bit Logic Instructions
The FN statement detects a negative edge at the contact (that is, the signal state of the RLO changed from 1 to 0). If there is no change in the RLO (current RLO and previous RLO stored in the edge memory bit are both equal to 0 or 1), then the FN statement resets the RLO to 0.
Table 5-10 Checking for Negative Edge Transition at Input I 1.0 OB1 Scan
Cycle No.
Signal State at Input in Previous Cycle
Signal State at Input in Current Cycle
Did the signal state change from 1 to 0?
Is the coil at Q 4.0 energized?
1 0
(default value)
0 No No
2 0 1 No No
3 1 0 Yes Yes
4 0 0 No No
5 0 1 No No
6 1 1 No No
7 1 1 No No
8 1 0 Yes Yes
9 0 0 No No
Table 5-10 applies specifically to the statement list program shown in Figure 5-8. In general, you should consider the transitions detected by FP and FN to be transitions reflected in the RLO, not in the signal states of contacts.
For example, a logic string can form an RLO that is not directly related to the signal state of a contact.
The location that the FP or FN instruction addresses is a bit. The instruction accesses the output through one of the following types of addresses:
Address identifier (ID) and location within the memory area that is indicated by the address identifier (see Tables 5-11 and 5-12)
Bit transferred as a parameter (see Table 5-13) Addressed Bit
Bit Logic Instructions
Table 5-11 Addresses of FP and FN: Direct and Indirect Addressing Address Maximum Address Range According to Addressing Type
ID1 Direct Memory Indirect Area-Internal Register Indirect I2
Q3 M DBX
DIX
0.0 to 65,535.7
[DBD]
[DID]
[LD]
[MD]
0 to 65,532
[AR1, P#byte.bit]
[AR2, P#byte.bit]
0.0 to 8,191.7
1 See the Caution that follows this table.
2 Because the operating system overwrites the process-image input table at the beginning of every scan cycle, the RLO stored by an FP or FN instruction that uses an input bit as its address is corrupted. See the Caution that follows this table.
3 Using an output bit as the address of an FP or FN instruction is not recommended. If you want to influence an output, use the S, R, or = instruction.
!
CautionCorruption of stored result of logic operation.Can cause minor property damage.
If you use an FP or FN instruction in your program, the memory bit that is the address of this instruction is used by FP or FN exclusively for its own storage purposes. Therefore you should not use any instruction that would change this bit. Otherwise you will corrupt the stored RLO. This caution applies to all the memory areas indicated in the address identifiers listed in Table 5-11.
Table 5-12 Addresses of FP and FN: Area-Crossing Register Indirect Addressing
Address Identifier1 Address Range
I, Q, M, DBX, or DIX [AR1, P#byte.bit]
[AR2, P#byte.bit] 0.0 to 8,191.7
1 The memory area is encoded in AR1 or AR2, respectively (see Section 3.6).
Table 5-13 Addresses of FP and FN: Bit Transferred as Parameter
Address Address Parameter Format
Bit Logic Instructions