Design and Implementation of Fault Tolerant Hybrid Full Adder Using Inverter
1Pradeep.S, 2Abinaya.R
1,2 Assistant Professor,
Department of Electronics and Communication Engineering, M.Kumarasamy College of Engineering, Karur, Tamilnadu
Abstract
Fault tolerance is a property that enables a system to continue operating properly in the event of one or more faults within of its component. The fault further classified into transient fault and permanent fault. Overall System performance can be effect by the presence of fault. The aim of this paper is to design a fault tolerant hybrid full adder so that the system will satisfy the requirements despite failures. We designed to detect and repair any faults in a circuit using self checking and self repairing full adder. It can also identify the location of faults. The conventional full adder involves many numbers of components. And also area and power will be high. So we introducing hybrid full adder with less number of logic gates. And also we implemented a multiplier using this proposed system. The proposed design is simulated by Xilinx and synthesized by ModelSim. This system can solve the major problem occurring in real-time application.
Keywords: Fault tolerance, Hybrid adder, self checking adder, self repairing adder
1. Introduction
Very Large Scale Integration (VLSI) is the process of designing and manufacturing an integrated circuit by combining much number of devices into a single chip. Before introducing VLSI technology most integrated circuits had a limit ed set of functions they could perform [1]. With technology improvement, now the range of devices is in billion.
VLSI applications are used almost in every real-time applications include microprocessor in a PC, digital camera or camcorder, or a portable co mputing device. Addition is a basic operation used in many VLSI systems. All complex circuits use full adder to execute their operation. Many applications use full adder because it will reduce system complexity. It can be used to construct a ripple carry counter to count n-bits. Thus, it is also used in ALU also. It is used in processor chip like snapdragon, Intel Pentium for CPU part. The fault is the representation of the defect at the function level. The fault is further classified into permanent fault and transient fault. Transient fault is a fault that is temporarily present and automatically recovered if the power is disjoined and then restored. Permanent fault is one that continues to exist until the faulty component is repaired. The fault arises due to variation of power supply. To design a circuit, we generally use logic gates which may result in more area and power [3]. By using this technique, we can reduce power, propagation delay and area of digital circuits while maintaining low complexity of l ogic design. In ripple carry adder the carry out of previous adder is the carry in of previous adder. Xilinx produced a software tool called Xilinx ISE which is used for synthesis and analysis of HDL design [5]. It enables the developer to synthesis the de sign and performs the timing analysis. VHDL is a hardware description language used in electronic device
2. Existing System
There are many approaches available for self checking and self repairing full adder. Self checking adder is used to check the fault while self repairing fault is used to repair the faults by detecting the location. In existing systems we use Carry select adder (CSA) [4]. CSA is usually built in cascade form to perform fast. The use of conventional logic gates may produce more area and power consumption in Carry select adder. Number of logic gates used is also very high.
2.1 Self Checking Full Adder:
It is the existing Self checking Full adder [fig 2.1]. It can detect the fault and also identifies the fault locations. The fastest adder is CSA and also takes minimum hardware cost compared to other Adder [2]. In this CSA based self checking full adder both sum and carry output are checked individually to detect the fault in both sum and carry output. XNOR gates are used here to compare the output. To detect the carry output XNOR gates and functional unit are used. The output expressions are represented as a form of f1,g1,fc. If there is no fault then the output fc will be zero. If there is a fault in carry output, fc indicates 1. Similarly, three XNOR gates are used for detecting the fault in sum output. If there is fault free condition in the sum output, then the output fs will be 0. If there is a fault in sum output, fs indicates 1. Finally fc and fs are used to detect the fault in carry and sum output. If there is a fault, then any one or both of the signals are high. If there is no fault, both the signals will be low. In this way, both single and double fault can be identified at the time.
B1 A1 B0 A0
B1 A1 B0 A0
Cout S1 S2
Z1 Z2
FIG 2.1 Self checking Full Adder
Full adder Full adder
Full adder Full adder
0 1 0 1
1 1
2 pair 2 rail checker 0 1
Cin = 0
Cin = 1 Cin
2.2 Self Repairing Full Adder
This design fig [2.2] is used to repair the faults by Carry select adder. It can repair both permanent and transient faults. In this design we need two self checking full adders and multiplexer (mux) [7]. One adder is used as a normal adder. Another adder is used for recovery at run time. If there is a fault in normal adder, then mux will send the sum and carry to another adder. Two internal mux are used to design this self checking mux. The purpose of mux is to deliver final output. Here e refers for extra adder which is used for fault recovery.
The limitation of this design is it requires redundant full adder to repair single fault. This self repairing full adder design will not repair double fault at a time. To remove the fault in the full adder, we can replace it with fault free adder. if there is double fault, then it indicates that there is no fault. And this method is less reliable. This design failed when multiple faults occurred in individual full adder. In existing system, they use cadence virtuso tool to design their circuit and also to measure area delay and power.
Cout Cout- final
Sum
Cout
Sum
Sum- bit 0 faults
FIG 2.2 Self Repairing Full Adder
3. Proposed System
In proposed system we designed self checking and self repairing full adder using Hybrid adder.
The adder we used here is Ripple Carry Adder. The power consumed in ripple carry adder is less than the power consuming the carry select adder. So we designed using ripple carry adder.
3.1. Proposed Self Checking Full Adder
In this design fig [3.1] we used ripple carry adder instead of conventional logic gates. This method can detect the fault with the exact indication of its location. It can detect both single and
Adder-
1e Adder-0e
Adder-1
Adder-0
XNOR gates are used to compare the outputs. If both the values of G1 and F1 are low or high then there is no fault in carry. If any one of the value is low, then there is a fault in carry.
Similarly G2 and G3 are compared to detect the fault in sum output. Finally fc and fs are the signals which are used to determine the fault in the Full adder [10].
3.2 Proposed self repairing full adder
This self repairing full adder design fig [3.2] is proposed to repair the faults detected by the self checking design of hybrid full adder. We use multiplexer and inverter to repair and generate the output. The purpose of inverter is to invert the output [8]. This design is based on the principle of two control signals Fc and Fs. If there is no fault in the output coming from self checking full adder, then the multiplexer will take the fault free output to generate the final output [9]. If there is a fault detected in self checking full adder, then the inverter is used to repair the fault. The inverter is used to make the faulty output into fault free output. Then the multiplexer is used to generate the final output. In this way it will reduce area and power consumption.
There is no need to replace the faulty adder. And also this self repairing full adder requires less area. It can repair both the permanent and temporary faults and makes the full adder fault free
A B C
sum cell
Sum Cout
2
3 1
G2 G3 G1
Fs Fc
FIG 3.1 Proposed Self Checking Full Adder 1
Function al unit
2
Fc
carry
Carry Mux1
sum mux2
Sum bit 0
Fs
FIG 3.2 Proposed self repairing full adder
4. RESULT
The proposed self checking hybrid full adder and self repairing hybrid full adder were designed.
Simulation is done by Xilinx. And the designs are synthesized by using ModelSim. The advantage of this design is we can extend the bits up to desirable level. Here we reduce the area when compared to existing system. This system can detect and repair double fault at a time. And we also implemented multiplier using this design. From the result, the power consumed in proposed system is less than the existing system [fig 4.1 and fig 4.2]. The power of existing system is 1269 mw and the power of proposed system is 1247 mw.
Proposed self checking
hybrid Full Adder
Proposed self checking
Full Adder
FIG 4.1 Waveform of proposed self checking full adder
FIG 4.2Waveform of proposed self repairing full adder
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