Process Development for an Undergraduate Microchip Fabrication Facility

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Session 2464

Process Development for an

Undergraduate Microchip Fabrication Facility^†

Christopher T. Timmons, David T. Gray, and Robert W. Hendricks Virginia Polytechnic Institute and State University

Abstract

We have built a microchip fabrication facility for teaching the elements of semiconductor processing to a multidisciplinary group of approximately 500 students per year from all areas of engineering, science, and even the humanities. In order to meet our pedagogical objectives of introducing microchip fabrication to introductory students, we have developed a four-mask, nine- step nMOS process using 100 µm rules for use with 4-inch wafers that can be completed by students working in teams of four in six two-hour laboratory periods. Our masksets and the processes used were developed in less than a year, primarily by senior level students in materials, chemical, and electrical engineering.

I. Introduction

Virginia Polytechnic Institute and State University, under the auspices of the Virginia Microelectronics Consortium (VMEC), the Bradley Department of Electrical and Computer Engineering, and the Materials Science and Engineering Department, has developed an 1,800 ft² Class 10,000 cleanroom for teaching the elements of the microchip fabrication process to a multidisciplinary cohort of students from all areas of engineering, science, and even the

humanities. The estimated throughput is approximately 500 students per year (about 170 students per semester). The development of our Class 10,000 cleanroom and the operation of our facility are described elsewhere.¹

The process we have developed follows a manufacturing scheme to fabricate simple devices and simple testable circuits. We design our photolithography masks in AutoCad^TM and print them on standard transparencies using a high-resolution Alps Microdry^TM printer. This simple mask design and generation procedure allows process flexibility at minimum cost—a complete maskset costs less than a dollar. Further, such simplicity will allow advanced students to design, fabricate, and test wafers using their own masksets. For our introductory class, the mask design includes resistors, p-n junctions, nMOS transistors, and simple circuits, as well as regions for device characterization and analysis. During the processing, students visually inspect and electrically test their wafers to insure the quality of processing. Students can test their wafers and devices using software written in LabView, which permits standard and custom tests. Typically, we measure the sheet resistivity after each processing step and we measure I–V curves for each device. The

† A version of this manuscript with gray-scale images suitable for color vision-impaired readers may be found at http://www.mse.vt.edu/faculty/hendricks/publications/publications.html.

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characteristic variables of the processes such as diffusion and oxide growth rates correspond well with literature, thus allowing the students to compare and model their results.

Students taking this laboratory class learn the basics of a complete transistor manufacturing process and develop an appreciation for the processing equipment. This gives them a significant head start towards a career in semiconductor manufacturing or semiconductor related research.

The organization and procedures of our process and laboratory have received very favorable comment from industrial representatives who have visited our facilities.

The process developed for this lab is tailored for a specific type of wafer. We use 4-inch (100 mm) diameter, 500 to 550 µm thick, p-type wafers with bulk resistivities between 14 and 22 Ω- cm that were donated to us by Motorola. All tools and times are specific for wafers with these characteristics. It is the purpose of this paper to present the details of our process by which our completed wafers are created.

II. Mask Design and Creation

Based on Jaeger,² we decided to fabricate enhancement mode nMOS devices based on a four level mask step. The four level mask set also allowed the fabrication of resistors, diodes and

capacitors. We used standard laser printer transparencies and a high resolution Alps 2000 lpi MicroDry^TM printer capable of 1400 x 1400 dots per inch. For our purposes, the MicroDry technology is superior to both ink jet and laser jet printing. The smallest line width that is possible to print reliably was 100 microns. The masks were designed and printed using AutoCAD 2000.

We employed a positive resist and imaging process meaning the areas of the mask exposed to light were removed after the develop process. Ideally, an image reversal process should be employed to guard against pinholes, however, time constraints limited the development of this process.

A number of devices and process control structures including nMOS transistors, PN junctions, resistors, and capacitors were included in the original maskset. For each structure, several devices were created with varied dimensions thus allowing the student to observe the effect of size on device performance. Transistor channel widths ranged from 50 to 250 microns. Other dimensions of the devices were also varied including source/drain size, n-well size, resistor width and length, and capacitor area. The mask design also included sheet resistance measurement sites at each level. Four process control structures are created at the edge of each layer. These

structures include variable sized lines and spaces, variable sized squares and holes, and a vernier to measure X and Y offset between each mask level relative to the first. This structures allows visual evaluation and keeps a record of each photolithography, develop, and etch step. The structures can be easily inspected using an optical microscope. Other devices included a contact resistance measurement and several simple circuits including a ring oscillator and an inverter.

Time constraints, however, limited the testing of these circuits.

The mask set comprises a source/drain diffusion mask, a channel etch mask, a contact etch mask and an aluminum metallization mask. As the names imply, the diffusion mask is used to define the

source and drains of the transistors. Similarly, the resistors, n-wells for diodes and sheet Page 6.810.2

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resistance measurement sites are also opened. The channel etch mask opens the transistor channels. The “un-doped” sheet resistance sites are also defined. Next, the contact holes are opened in the gate oxide using the contact mask. Finally, the evaporated aluminum film is defined using the last mask. Figure 1 shows the various mask steps with typical dimensions for the

transistors while the complete maskset is shown in figure 2.

Each mask must be precisely aligned with the previous mask. We define marks in the first mask level that are used as a reference for later levels. It is important to design the mask so your marks are protected. Alignment was accomplished using alternating solid and outlined crosses. The cross in the center is used for X and Y alignment. The outer crosses are used for rotational alignment. The outer crosses were located as far from the center as the alignment tool allows.

While sacrificing resolution, the ease, low cost and speed with which mask sets can be modified or designed from scratch is an incredible advantage. This advantage allowed rapid development of working devices. The possibility of an advanced course where the students design and test their own mask sets can also be realized.

(a) (b)

Figure 1: Planar view of the various steps for creating an nMOSFET.

(a) create the source and drain wells; (b) grow the gate oxide; and (c) add the contact metallization.

(c)

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(a) (b)

(c) (d)

Figure 2: Four-layer maskset for process described.

III. Wafer Processing

Our device fabrication process is only nine steps, suitable for a semester-long laboratory class. All processing is carried out using the Modu-Lab series of tools which includes an oxidation furnace, two diffusion furnaces, a wet bench, a photolithography station, an aluminum evaporator, and two device characterization stations. These tools are described in detail elsewhere.^{1, 3} Explicit experimental details are given in our laboratory manual.⁴ The eight processing steps that involve changes to the surface of the wafer are shown in Figure 3.

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(a) (b)

(c) (d)

(e) (f)

(g) (h)

Figure 3: Cutaway illustrating each step of the process. (See text for details.)

First, the wafer is cleaned with acetone and HF to remove both organic contaminants and the native silicon dioxide from the surface. The wafer is rinsed with deionized (DI) water and spun dry. The sheet resistance of the wafer is measured to provide comparative data for calculations.

The field oxide layer is grown on the wafer under wet conditions (Figure 3a) in the oxidation furnace module. Water vapor is mixed with the oxygen entering the furnace using a boiler maintained at 95⁰C. The wet oxide grows substantially faster than the dry oxide but is of a lower quality than dry oxide. The lower quality oxide is acceptable because for this step it acts only as a barrier against the phosphorus diffusion. In order to effectively block the phosphorus from diffusing through the oxide, the layer must be at least 530 nm thick. Following oxide growth, the thickness is measured using a Filmetrics F20 thin film measuring device.

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After the field oxide layer is grown, the first mask (Figure 2a) is transferred to the wafer using the photolithography module. Photoresist is spun on the wafer using the spinner and a modified pipette. A gravity drain of the resist from the pipette minimizes splatter and eliminates streaks in the film. The wafer is exposed using the first mask with the exposure module. Because the masks are practically disposable, we used contact printing which means the wafer came in contact with the mask. This method resulted in the better resolution than proximity printing even though the tool is capable of both. After exposure, the wafer is baked at 95^oC and then placed in a bath of commercially available developer. It is removed after reaching a visual endpoint. Using an optical microscope, the devices and the process control structures are inspected for under- or over- develop. If over-developed, the photoresist can be stripped with acetone and the process can be repeated. If under-developed, it can be returned to the developer solution for completion. We note that our photoresist does not require a soft or pre-exposure bake.

The wafer is etched in commercially available buffered oxide etchant (BOE) which is dilute hydrofluoric acid. After a visual endpoint, the wafers are removed from the bath and rinsed with DI water and dried. The process control structures are inspected for etch completeness. If satisfactory, the photoresist is stripped using acetone. The etched holes in the oxide will become the source and drain of the FETs, resistors and the n-well of the diodes (Figure 3b).

Using the diffusion furnace module, the wafer is doped by heating a PhosPlus solid-state source held at 810^oC in close proximity to the wafer. This source is a ceramic material designed to provide a constant effusion of P2O5 with time.⁵ Using a specially designed quartz carrier, wafers are mounted in pairs with the active surfaces facing the source. This predepositon step deposits a highly concentrated dose of phosphorous onto the wafer. After a specified time, the doping source is removed, and the shallow dose of phosphorus is diffused deeper into the wafer at 1000^oC. Figure 3c shows the wafer with the n-wells diffused into the substrate. Our typical junction depths are 1.5 to 2.0 µm. The sheet resistivity is measured in a designed test area of the wafer to verify proper diffusion and to allow junction depth calculations.

Another photolithography step, using the second mask (Figure 2(b)) is performed to remove the oxide covering the channels of the transistors. Mask alignment is required in this step. The wafer is etched in BOE and the channel is removed. Any residual phosphorous film is also removed from the doped surfaces. A 40 nm thick high quality gate oxide is grown using the oxidation furnace and pure (dry) oxygen (Figure 3e). The gate oxide layer acts as the capacitive gate for the FETs. Next, another photolithographic step (Figure 2(c)) is used to pattern the gate oxide layer creating contact holes through which the aluminum probe pads contact the silicon.

Once the contacts are opened and inspected, a 200 nm aluminum film is evaporated onto the entire surface of the wafer using the aluminum PVD module. A final photolithographic step (Figure 2(d)) is used to pattern the probe pads and connections. This completes wafer processing.

In the case of a broken or mis-processed wafer during the laboratory class, the instructor’s

demonstration wafer is given to the team. Thus, no team is required to start over and each team is able to complete the entire lab with a working wafer.

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IV. Wafer Testing

The wafer testing system, or device characterization module (DCM), comprises a Signatone Model H-150 hybrid microprobe station, a Signatone Model S-301 4-point probe sheet resistivity station, a Keithley Model 2400 digital source meter, and a National Instruments general purpose digital/analog I/O card. The test stations are interfaced to a Pentium II-based PC via a GPIB interface, and are controlled remotely via software written in LabView. Our configuration and software has been modified significantly from that provided by EMS.⁶ Calculations of laboratory throughput showed that wafer testing would be the rate-limiting step in our procedure. Thus, we have developed two identical DCMs.

There are two groups of tests that are performed on each wafer—those to verify processing and those to determine device functionality. The sheet resistivity of the wafers is measured

periodically throughout the process in order to verify proper processing and to allow for a greater understanding of those processes. To determine the sheet resistivity, the 2400 source meter is used to force a current through the outer two pins of the Signatone S-301 probe head, while measuring the resulting voltage on the inner two pins (see Figure 4(a)). After the application of a correction factor to allow for layer geometry, a measurement in ohms/ is attained. The sheet resistivity is measured 3 times during the process; before field oxidation, after field oxide etch, and after diffusion drive-in. Each measurement is made in a dedicated region of the wafer. These measurements show the initial sheet resistivity of the wafer, the effect of oxide growth on doped silicon, and the proper execution of phosphorus diffusion, respectively. A typical representation of a sheet resistance measurement is shown in Figure 5.

The second set of tests is done at the end of the process flow and verifies proper functioning of the devices. These tests include a resistor test, a diode test, transistor characterization curves, and transistor threshold voltage tests. All characterization tests are performed on our simplified semiconductor parameter analyzer (SPA).⁶ In each case, the device under test (DUT) is selected, the probes (either two or three, as required) on the Signatone H-150 microprobe station are aligned under a microscope, and good electrical contact is made by raising the wafer stage (see Figure 4(b)).

The resistor and diode tests are nearly identical. The student defines variables in the LabView interface and views the results graphically. For both the resistor and the diode, the student specifies the start value, the stop value, and the number of points for a voltage sweep. The Keithley 2400 then sweeps a voltage across the resistor or diode and measures the current. The results appear in a graph and may be saved in a coma delimited text file, which may be imported into Excel or other graphical Windows-based programs. The data are also exported to our LIMS SQL-2000 database. During the measurement of the characteristic curves of a MOSFET

transistor, the National Instruments card is employed as well as the Keithley 2400. Students input sweep parameters for the drain-source voltage for the measurement, as well as six gate voltages.

When the test is performed, the gate voltage of the device is held constant and the drain to source voltage (VDS) is swept by the Keithley 2400 following the input parameters. The gate voltage is updated to the next value and the drain-to-source sweep is performed again. This cycle occurs

for each of the six gate voltages and the results are graphically displayed. Page 6.810.7

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The threshold voltage test uses the same probe configuration as the MOSFET characterization curve tracer. This test holds the drain-to-source voltage constant at 25 volts, and sweeps the gate voltage while measuring the resulting drain to source current. The graphical result of this test shows the student the threshold or “on” voltage of the MOSFET under examination. Figure 6 shows typical results of both the threshold voltage test and the characterization curves.

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Figure 4: (a) Four-point sheet resistivity probe head on wafer under test. (b) Three micro-probes aligned for MOSFET

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Figure 5: Typical sheet resistivity data.

Figure 6: Typical transistor characteristic curves.

One notes immediately from Figure 6 that there is a small leakage current in this particular device.

This is common among many of our devices. We believe that this is a result of some penetration of phosphorous through the field oxide over the channel during n-well creation.

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Analysis of the data acquired during testing allows students to discover the effects of both process and design variables on the final product. For example, varying dimensions of devices give

varying performance parameters and the graphical representation of these differences provides data that are both easy to understand and easy to manipulate for reporting.

V. Conclusions

By using large design rules (100 µm), and through the use of the Modu-Lab Trainer series of semiconductor processing modules, we have been able to greatly simplify a complex process.

Our current facilities are simple enough to allow a group of multidisciplinary students with little or no previous knowledge of semiconductors to benefit from a laboratory class, while allowing for future modifications to both the toolset and/or the process flow. In this manner, we have retained the pedagogical aspects of semiconductor manufacturing but significantly reduced the cost. At the same time, by installing our processing tools in a modest cleanroom, we have been able to retain the essential features of a “real” semiconductor fab, thus giving our students a greater appreciation for the delicacy, precision, and complexity of the process. Student and industry feedback has been overwhelmingly positive.

VI. Acknowledgements

We are indebted to Professors Peter Athanas, Louis Guido, Alex Huang, and Carlos Suchicital for their continuing support in a myriad of ways, and to Mr. David Berry for his consistently excellent work in helping us install and maintain the our processing tools. We thank Ashland Chemical for donating the aluminum etch, Clariant for donating the photoresist, Motorola for donating the wafers, Techneglas for donating phosphorous and boron sources, and Texwipe for donating a wide range of cleanroom supplies. Without their financial and technical support, the development of the process described here would not have been possible.

This work was supported in part by the Combined Research and Curriculum Development program of the NSF under grant EEC 99-80282.

Bibliography

1. R. W. Hendricks, An Undergraduate Microchip Fabrication Facility, (this symposium).

2. R. C. Jaeger, Introduction to Microelectronic Fabrication, Volume V in Modular Series on Solid State Devices, R. F. Pierret and G. W. Neudeck, eds, Englewood Cliffs: Prentice-Hall (1988).

3. Electromechanical Services, Inc., Albuquerque, NM (http://www.emsi-usa.com).

4. R. W. Hendricks, Semiconductor Fabrication Laboratory Manual,

(http://www.mse.vt.edu/faculty/hendricks/courses/mse2224/manual/index.html) 5. PhosPlus source from Techneglas, Inc. (http://www.techneglas.com)

6. D. T. Gray and R. W. Hendricks, A Simplified Semiconductor Parameter Analysis System for an Undergraduate Microchip Fabrication Facility, (2001, to be published).

7. P. D. Eckerman and R. W. Hendricks, A Laboratory Information Management System (LIMS) for an Undergraduate Microchip Fabrication Facility, (this symposium).

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CHRISTOPHER T. TIMMONS

Chris Timmons is currently a graduate student in Chemical Engineering at Georgia Institute of Technology. He received his B.S. in Chemical Engineering from Virginia Tech in 2000. While at Virginia Tech he led the team of students that developed the mask set and process used in the Semiconductor Fabrication Laboratory.

DAVID T. GRAY

David Gray is currently a graduate student in Materials Science and Engineering at Virginia Tech where he is a GTA in the undergraduate Semiconductor Fabrication Laboratory with responsibilities for both process

development and undergraduate teaching. He received his B.S. in Electrical Engineering from Virginia Tech in 2000.

ROBERT W. HENDRICKS

Robert Hendricks holds a joint appointment as Professor of Electrical and Computer Engineering and Professor of Materials Science and Engineering at Virginia Polytechnic Institute and State University in Blacksburg, Virginia.

He is also the Director of the Center for Microelectronics, Optoelectronics, and Nanotechnology (MicrON). Dr.

Hendricks received his B.Met.E (1959) and his Ph.D. (1964) from Cornell University and his M.B.A. (1985) from the University of Tennessee. He joined the faculty at Virginia Tech in 1986 following seventeen years at Oak Ridge National Laboratory and six years with Technology for Energy Corporation. Dr. Hendricks is a Fellow of the AAAS and the APS. He may be reached at [email protected].

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