Chapter 5, The Instruction Set Architecture Level

Chapter 5, The Instruction Set Architecture Level

5.1 Overview Of The ISA Level

5.2 Data Types

5.3 Instruction Formats

5.4 Addressing

5.5 Instruction Types

5.6 Flow Of Control

5.7 A Detailed Example: The Towers Of Hanoi

5.8 The Intel IA-64

5.9 Summary

Instruction Set Architecture

The Instruction Set is an interface between the Hardware and Software.

It is a mnemonic description of the machine language being executed by the micro-architecture.

Issues in new ISA Design and Application

 “Is it compatible with it’s own predecessor?”

 “Can I run my old OS on it?”

 “Will it run existing applications unmodified?”

Backward Compatibility

 Source code compatible

 Machine code compatible

A new ISA will have new features, but what about other aspects of the language!

 What remains and what changes?

 A revolutionary change may make all higher level software change!

A good ISA will:

1. “..define a set of instructions that can be efficiently implemented in current and future technologies, resulting in cost-effective designs over several generations.”

 Requiring gates to interpret legacy instructions is reasonable

 Expansion at the machine level should be possible

 Speed considerations are dealt with

Note: new processors may be developed every 9-18 months … can the basic elements be maintained for multiple generations?

2. Provide a clean target for compiled code

 Compiler friendly

 Regularity and completeness of a range of choices (what to do when “obvious” alternatives are not included)

Note: A “good” ISA can make a significant difference in the performance of a processor.” AST reports (p. 333) that a difference of up to 25 % is possible.

An Overview of the ISA Level

It used to be a one-to-one relation to the machine language It used to be the machine assembly language

It is now considered what a compiler/linker outputs to execute on a processor.

Note: some of the microarchitecture complexity may be hidden (e.g. micro-program)

A minor disagreement with AST (possibly an ECE vs. CS perspective):

AST states, “no (sane) person does much programming in machine language any more …”

Yes, but … there will always be work at the machine language/firmware level!

Real-Time Signal Processing often demands machine level optimization!

Overlapping and non-overlapping activities and involvement

HARDWARE FIRMWARE SOFTWARE

A possible extension

SOFTWARE APPLICATION USER

Overlapping can make individuals and products more valuable and useful in the long run!

What do you get and what do you need-to-know at the ISA level?

 Memory Model

 Registers Available

 Instructions

 Data Types

Where do you get this information? The Programmer’s Model of a Computer

An ISA Level Specification can be written that allows multiple implementations.

If so, all machines (from different vendors) can execute the same software! Examples:

 SPARC V9

 JVM

Normative Section: Provide requirements Information Section: Provide help and hints

Note: the INTEL ISA is not shown above. Why? The ISA is not a released, public specification.

If you are not licensed by INTEL, you are using reversed engineered materials that are for a

generally “compatible” ISA.

Other things the compiler/linker need to know:

Multiple Machine Modes:

 USER mode

 PROTECTED mode

 SUPERVISOR mode

 KERNEL mode

OS level operations for multiple users protect sensitive information

support system level traps and interrupts time sharing/context switching

virtual memory assignment

Important Documentation:

The Programmer’s Guide software and firmware, includes all ISA issues

The User’s Guide hardware and firmware, usually not the ISA

Registers

Memory

Instructions

Programmer’s Reference Guides/Manuals

SPARC v9: The SPARC Architecture Manual

http://www.sparc.org/standards/SPARCV9.pdf

 SPARC stands for a Scalable Processor ARChitecture. SPARC has been implemented in processors used in a range of computers from laptops to supercomputers.

 SPARC-V9 is a robust RISC architecture that will remain competitive well into the next century.

 SPARC-V9 directly supports 64-bit virtual addresses and integer data sizes up to 64 bits.

 Overview: “This specification defines a 64-bit architecture called SPARC-V9, which is upward-compatible with the existing 32-bit SPARC-V8 microprocessor architecture. This specification includes, but is not limited to, the definition of the instruction set, register model, data types, instruction opcodes, trap model, and memory model.”, p. 22.

Intel® 64 and IA-32 Architectures Software Developer Manuals

http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

“The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number 253665) is part of a set that describes the architecture and

programming environment of Intel® 64 and IA-32 architecture processors. Other volumes in this set are:

 The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B &

2C: Instruction Set Reference (order numbers 253666, 253667 and 326018).

 The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B &

3C: System Programming Guide (order numbers 253668, 253669 and 326019).Page 22:

Overview of manual”

Vol. 1, page 1-1.

MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL

http://www.industrologic.com/MCS51FamilyUsersGuide.pdf

From Wikipedia: (http://en.wikipedia.org/wiki/MCS_51)

The Intel MCS-51 (commonly referred to as 8051) is a Harvard architecture, single chip microcontroller (µC) series which was developed by Intel in 1980 for use in embedded systems.[1][2] Intel's original versions were popular in the 1980s and early 1990s. While Intel no longer manufactures the MCS-51, binary compatible derivatives remain popular today. In addition to these physical devices, several companies also offer MCS-51

derivatives as IP cores for use in FPGAs or ASICs designs.

Programmer’s Guide Sections

1. Overview/Architecture Introduction

2. Basic Environment – Registers and Memory Mapping/Models 3. Interrupts/Calls/Exceptions/Traps

4. Data Types 5. Instructions

Memory Models and Addressing

8-bit Bytes

Historic CISC processors use byte addressing on word-wide storage elements.

Therefore, Byte alignment issues can and do arise …

Also: Little Endian and Big Endian issues

In what order is data vs. text (e.g. ASCII) stored?

Within a processor, this isn’t an issue; between processors it can be an issue.

When peripheral devices are memory mapped, Byte ordering on busses must be done correctly!

Memory Maps

Are their separate memories for Data, Instructions and Peripherals?

If there is a single “address” space, how is it partitioned?

 Reserved addresses/memory (User/Kernel/Supervisor)

 Boot Memory locations or blocks

 Memory mapped Input/Output (I/O)

 Speed/Control/Device Boundaries (ROM/EEPROM/DRAM access time and wait states)

 Virtual Memory Registerss

IJVM

Explicit: MAR, MDR, PC, MBR, SP, LV, CPP, TOS, OPC, H Implicit: MPC, MIR, Condition Code

General Purposes Registers

 Address/Index Registers

 Program Status Words or Condition Code Registers

 Flag Registers

Program Status Word (PSW) or Flag Register or Condition Code (CC) Register

Available to describe operating conditions that exist within the processor Arithmetic status information

N – negative result Z – zero result

V – overflow of the addition/subtraction C – carry out of the ALU

Interrupt status information Interrupt Pending

Priority or type of interrupt

INTEL P6 Basic Registers

Page 85: Vol. 1, 3-15 Software Developer’s Manual

Alternate Naming (backward Compatible)

Page 86: Vol. , 3-16 Software Developer’s Manual

EFLAGS Register

Page 91: Vol. 1, 3-21 Software Developer’s Manual

Basic Status Flags

CF (bit 0) Carry flag. Set if an arithmetic operation generates a carry or a borrow out of the most- significant bit of the result; cleared otherwise. This flag indicates an overflow condition for unsigned-integer arith-metic. It is also used in multiple-precision arithmetic.

PF (bit 2) Parity flag. Set if the least-significant byte of the result contains an even number of 1 bits;

cleared otherwise.

AF (bit 4) Adjust flag. Set if an arithmetic operation generates a carry or a borrow out of bit 3 of the result;

cleared otherwise. This flag is used in binary-coded decimal (BCD) arithmetic.

ZF (bit 6) Zero flag. Set if the result is zero; cleared otherwise.

SF (bit 7) Sign flag. Set equal to the most-significant bit of the result, which is the sign bit of a signed integer. (0 indicates a positive value and 1 indicates a negative value.)

OF (bit 11) Overflow flag. Set if the integer result is too large a positive number or too small a negative number (excluding the sign-bit) to fit in the destination operand; cleared otherwise. This flag indicates an over-flow condition for signed-integer (two’s complement) arithmetic.

UltraSPARC II Basic Registers

Working registers include:



Integer working registers (r registers)



Floating-point working registers (f registers)

Registers are assigned to specific tasks and data types Control/status registers include:



Program Counter register (PC)



Next Program Counter register (nPC)



Processor State register (PSTATE)



Trap Base Address register (TBA)



Y register (Y)



Processor Interrupt Level register (PIL)



Current Window Pointer register (CWP)



Trap Type register (TT)



Condition Codes Register (CCR)



Address Space Identifier register (ASI)



Trap Level register (TL)



Trap Program Counter register (TPC)



Trap Next Program Counter register (TNPC)



Trap State register (TSTATE)



Hardware clock-tick counter register (TICK)



Savable windows register (CANSAVE)



Restorable windows register (CANRESTORE)



Other windows register (OTHERWIN)



Clean windows register (CLEANWIN)



Window State register (WSTATE)



Version register (VER)



Implementation-dependent Ancillary State Registers (ASRs) (impl. dep. #8)



Implementation-dependent IU Deferred-Trap Queue (impl. dep. #16)



Floating-Point State Register (FSR)



Floating-Point Registers State register (FPRS)



Implementation-dependent Floating-Point Deferred-Trap Queue (FQ) (impl. dep.#24)

Register windows

Register Windows from SPARC v9 Manual

8051 or MCS 51

Memory:

Logical Separation of Program and Data Memory

All MCS-51 devices have separate address spaces for Program and Data Memory, as shown in Figure 2. The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an 8-bit CPU.

Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register.

From the textbook

Registers shown:

Program Ststus Word (PSW) Interrupt Enable (IE)

Interrupt Priority (IP) Timer control (TCON) Timer Mode (TMOD)

Implicit but not shown …. the Accumulator!

Special Function Registers

4 banks of 8 registers R0-R7 Bit addressable space

Port addresses, accumulator address, and PSW

Program Status Word

Data Types

Numerical Data

 Unsigned Integer

 Signed Integer

 Binary vs. Decimal

 Floating Point

 Single and Double Precision

Problems:

Y2K: 2 decimal digits used to store year (8-bits instead of 16 bits) Clocks: nominal 1 usec (1 MHz) accuracy, ~ 2^20

32-bit register allows 2^12 seconds

Time “rolls-over” every 4096 seconds or every 1.1 hours!?

GPS: GPS week defined as a 10-bit quantity Therefore, 1024 weeks starting in 1980.

Roll-over every 19.7 years (1999 roll-over) Relative Memory Addressing:

16-bits provide 65536 forward offset, or

16-bits provide 32768 forward and backward offset, Memory addressing in general

32-bits provides 4 GB addressing

How big are modern hard-drives and how are the being addressed?

Non-Numerical Data

ASCII 7-bit representation (p.109-110)

UNICODE 16-bit representations (p. 111-112) Boolean

Bit Map

Example Data Types

Pentium P6 Architecture – (a 32-bit machine)

UltraSPARC II – (a 64-bit machine)

8051 – (an 8 bit machine)

Java Virtual Machine (JVM) – (a 32 bit machine)

JAVA Note: no unsigned integers!