Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Lecture 13

Biasing and Loading Single Stage FET Amplifiers

The Building Blocks of Analog Circuits - III

In this lecture you will learn:

• Current and voltage biasing of circuits

• Current sources and sinks in CS, CG, and CD amplifiers

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

DD

V

R

S

R

+ -+ -BIAS

V

s

v

The Common Source Amplifier



r

R



g

v

R

i

v

v

A

m o in d in out v











||

Open circuit voltage gain:

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The Common Source Amplifier: Problems



r

R



g

v

v

A

_{m o} in out v







||

Open circuit voltage gain:

To achieve large gain one needs:

1) A large DC current bias

I

Din order to get a large

g

m 2) A large value of the resistor

R

In saturation:



n DS



D n GS D m

k

I

V

V

I

g













2

1

Both the above requirements cannot be met easily simultaneously:  Not easy to realize large resistors in micro-chips

 A large resistor

R

will limit the maximum value of the DC current bias

I

D(because the potential drop

I

D

R

can become large enough to put the FET in the linear region where

g

mand the gain will be small)

The Digital Logic Inverter: Problems

To achieve fast switching one needs:

1) A small resistor (because then the RCLcharging time will be smaller when the output switches from “0” to “1”)

0

0

OUT

V

IN

V

TN

V

DD

V

V

IN



V

TN Cut-off Saturation Linear But

 A small resistor will require a very large current (to achieve a large potential drop across it) when the input is “1”, and the NFET is turned on, and the output need to be low or “0” – and this means more power dissipation

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The Common Source Amplifier with a Current Source

DD

V

BIAS

I

S

R

+ -s

v

+

-out OUT

v

V



D

I

What is needed is an ideal current source in the drain that can supply a large DC current and at the same time has a large small signal resistance

The incremental (or differential or small signal) resistance looking into an ideal current source is infinite + -BIAS

V

o m in out v

g

r

v

v

A







An ideal current source, of course, does not exist

But one can certainly do much better than using a resistor in the drain

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The Common Source Amplifier with a Current Source: DC Biasing

BIAS

I



GS TN

 

n DS



ox n BIAS D

C

V

V

V

L

W

I

I









1





2

2

The above equation determines

V

DS

=

V

OUT for a given value of

V

GS

=

V

BIAS

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The CS Amplifier with a Current Source: Small Signal Analysis

Gate Drain gs m

v

g

+

gs

v

-g

i

Source o

r

out

v

+

-in

v

+

-d

i

bs mb

v

g

+

bs

v

-Base 0 o m in out v

_v

g

r

v

A







Open circuit voltage gain:

o out

r

R



Output resistance:

Large Signal Model of a Current Source

The output resistance of the current source BIAS

I

Large signal circuit model

oc

r

 A large signal model of a current source

 r

ocis large for a good current source and infinitefor an ideal current source

A current source BIAS

I

Ideal current source IOUT VOUT IBIAS oc OUT OUT r dV dI _ 1 Slope oc

r

I

_BIAS OUT

V

OUT

I

+

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Small Signal Model of a Current Source

BIAS

I

Small signal circuit model oc

r

A current source IOUT VOUT IBIAS oc OUT OUT r dV dI _ 1 Slope oc

r

I

_BIAS

_V

_OUT OUT

I

+ -The output resistance of the current source oc

r

I

_BIAS Ideal current source Large signal circuit model

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Large Signal Model of a Current Sink

The output resistance of the current sink BIAS

I

Large signal circuit model

oc

r

 A large signal model of a current source

 r

ocis large for a good current source and infinitefor an ideal current source

A current sink BIAS

I

Ideal current source IOUT VOUT IBIAS oc OUT OUT r dV dI 1  Slope oc

r

I

_BIAS OUT

V

OUT

I

+

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Small Signal Model of a Current Sink

BIAS

I

Small signal circuit model oc

r

A current sink IOUT VOUT IBIAS oc OUT OUT r dV dI _ 1 Slope oc

r

I

_BIAS

_V

_OUT OUT

I

+ -The output resistance of the current source oc

r

I

_BIAS Ideal current source Large signal circuit model

PFET Loaded NFET Common Source Amplifier

DD

V

BIAS

I

S

R

+ -s

v

+

-out OUT

v

V



D

I

+ -BIAS

V

An ideal current source, of course, does not exist

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Current Sink:

I I roc

IOUT

VOUT

One can have any voltage at the at the output terminals of a good current sink and the current sinked will remain mostly constant

Current Sinks and NFET Transistors

OUT

V

OUT

I

D

I

OUT

I

OUT

V

o o OUT OUT

r

g

dV

dI

_

_

1

Slope

Characteristics in saturation resemble that of a non-ideal current source!

IOUT VOUT IBIAS oc OUT OUT r dV dI _ 1 Slope + -+

-ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Current Sources:

I I roc

IOUT

VOUT

One can have any voltage at the at the output terminals of a good current source and the current delivered will remain mostly constant

Current Sources and PFET Transistors

OUT

V

OUT

I

D

I

Characteristics in saturation resemble that of a non-ideal current source!

-ECE 315 – Spring 2007 – Farhan Rana – Cornell University

PFET Loaded NFET: Large Signal Analysis

0

0

DD

V

D

I

OUT

V

M2 M1 DD OUT DS OUT DS

V

V

V

V

V







2 1 2 1 D D D

I

I

I







BIAS

V

B

V

DC value of the output voltage (Both FETs in saturation)

Instead of the resistive load line, we now have the full

I

Dvs

V

DScurves of the PFET

The biasing voltages need to be selected carefully, otherwise one of the transistors can go into the linear region!!

PFET NFET

0

0

DD

V

D

I

OUT

V

BIAS

V

B

V

Instead of the resistive load line, we now have the full

I

Dvs

V

DScurves of the PMOS

The biasing voltages need to be selected carefully, otherwise one of the transistors can go into the linear region!!

PFET NFET

DC value of the output voltage (PFET in the linear region)

PFET Loaded NFET: Large Signal Analysis

ECE 315 – Spring 2007 – Farhan Rana – Cornell University



GS TN

 

n DS



n



BIAS TN

 

n OUT



n D

V

V

V

k

V

V

V

k

I













1





2

1

2

2 1 2 1 1









p



_{B DD TP}





_p



_{OUT DD}





DS p TP GS p D

V

V

V

V

V

k

V

V

V

k

I



















1







2

1

2

2 2 2 2 2 NFET PFET

Assuming the biasing is correct, both the FETs are in saturation

Equate the drain current magnitudes of the two FETs Then the only unknown will be

V

_OUT; solve for it

Verify that the obtained value of

V

_OUTdoes indeed result in both the transistors being in saturation

Equating:



 



p



_{B DD TP}





_p



_{DD OUT}





OUT n TN BIAS n D D D

V

V

V

V

V

k

V

V

V

k

I

I

I



























1

2

1

2

2 2 2 1

PFET Loaded NFET: Large Signal Analysis

M2

M1

1

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

PFET Loaded NFET: Transfer Curve

M2 M1

0

0

OUT V IN V TN V DD V VINVTN I II IV

I: V

_IN

< V

_TN M1 cut-off

II: V

_IN

> V

_TN

& V

_OUT

> V

_IN

- V

_TN

& V

_OUT

> V

_B

- V

_TP

M1 saturation, M2 Linear

III: V

_IN

> V

_TN

& V

_OUT

> V

_IN

- V

_TN

& V

_OUT

< V

_B

- V

_TP

M1 saturation, M2 saturation

IV: V

_IN

> V

_TN

& V

_OUT

< V

_IN

- V

_TN

& V

_OUT

< V

_B

- V

_TP

ECE 315 – Spring 2007 – Farhan Rana – Cornell University Gate1 Drain1 1 1 gs m

v

g

+

1 gs

v

-1 g

i

Source1 1 o

r

out

v

+

-in

v

+

-1 d

i

Gate2 Drain2 2 2 gs m

v

g

+

2 gs

v

-2 g

i

Source2 2 o

r

2 d

i

PFET NFET

Looking into the drain end of the PFET, what does one see?

PFET Loaded NFET: Small Signal Analysis

S

R

+ -s

v

M2 M1 1 Gate1 Drain1 1 1 gs m

v

g

+

1 gs

v

-1 g

i

Source1 1 o

r

out

v

+

-in

v

+

-1 d

i

Drain2 2 o

r

2 d

i

NFET

Looking into the drain end of the PFET, what does one see?

PMOS Loaded NMOS: Small Signal Analysis

ECE 315 – Spring 2007 – Farhan Rana – Cornell University 1 1 gs m

v

g

+

1 gs

v

-1 g

i

1 o

r

out

v

+

-in

v

+

-1 d

i

2 o

r



1 2



1 o

||

o m in out v

g

r

r

v

v

A







Open circuit voltage gain:

2 1

||

o o out

r

r

R



Output resistance:

PFET Loaded NFET: Small Signal Analysis

M2

M1

1

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

DD

V

S

R

+ -s

v

+

-out OUT

v

V



1 D

I

+ -BIAS

V

PFET load 2 B

V

3 B

V

M2 M1 M3

This load has a larger resistance looking into it

PFET Loaded NFET: The Cascode PFET Load

DD

V

S

R

+ -s

v

+

-out OUT

v

V



1 D

I

+ -BIAS

V

PFET load 2 B

V

M2 M1 D

R

Better

ECE 315 – Spring 2007 – Farhan Rana – Cornell University Gate2 Drain2 2 2 gs m

v

g

+

2 gs

v

-2 g

i

Source2 2 o

r

2 d

i

PFET Gate3 Drain3 3 3 gs m

v

g

+

3 gs

v

-The image part with relationship ID rId19 was not found in the file.

Source3 3 o

r

3 d

i

PFET

Cascode PEFT Load: Small Signal Analysis

PFET load 1 Gate2 Drain2 2 2 gs m

v

g

+

2 gs

v

-2 g

i

Source2 2 o

r

2 d

i

PFET Drain3 3 o

r

3 d

i

Cascode PFET Load: Small Signal Analysis

PFET load

ECE 315 – Spring 2007 – Farhan Rana – Cornell University Gate2 Drain2 2 2 gs m

v

g

+

2 gs

v

-2 g

i

Source2 2 o

r

2 d

i

3 o

r

Resistance looking into the current source is:



2 2



2 2 3 3 2 3 2 2 3 2 o m o o o o

1

m o m o o o

r

g

r

r

r

r

g

r

g

r

r

r













Cascode PFET Load: Small Signal Analysis

PFET load

1

Typically a good approximation

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

1 1 gs m

v

g

+

1 gs

v

-1 g

i

1 o

r

out

v

+

-in

v

+

-1 d

i

3 2 2o o m

r

r

g







1 2 2 3



1 1 1 o

||

m o o m o m in out v

g

r

g

r

r

g

r

v

v

A











Open circuit voltage gain:



2 2 3



1 1

||

m o o o o out

r

g

r

r

r

R





Output resistance: NFET

Cascode PFET Load: Small Signal Analysis

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The Common Source Amplifier: General Topology



V

BIAS

I

OUT

V

IN

V

BIAS

I

OUT

V

IN

V



V



V



V

NFET PFET

V

+_{is the most positive voltage in the circuit}

V

-_{is the most negative voltage in the circuit}

Large input resistance Large output resistance Large voltage gain Large current gain

 Good transconductance

amplifier

The Common Gate Amplifier: General Topology



V

BIAS

I

OUT

V

IN

V

I

_BIAS OUT

V



V



V



V

IN

V

Small input resistance Large output resistance Large voltage gain Small (unity) current gain

 Good current buffer

 Good transimpedance amplifier G

V

G

V

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The Common Drain Amplifier: General Topology



V

BIAS

I

OUT

V

IN

V

BIAS

I

OUT

V

IN

V



V



V



V

Large input resistance

Small output resistance

Small (less than unity) voltage gain Large current gain

 Good voltage buffer

NFET PFET

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Chip-Based Current Sources and Voltage Sources

We have realized a decent load but ……

How does one generate voltage levels on a chip for biasing??

Current and voltage biasing of circuits require transistor based current and voltage sources on a chip!