4 th Workshop on Innovative Memory Technologies

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Resistive RAM (

Resistive RAM (ReRAM

ReRAM) Technology

) Technology

for High Density Memory Applications

Sunjung Kim

sj [email protected]@samsung.com

S

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t

R&D C

t

S

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R&D C

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Semiconductor R&D Center

SAMSUNG Electronics

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 Introduction

• NAND Scaling Technologies & Barriers

 Samsung Vertical ReRAM (VRRAM)

• VRRAM vs. 3D cross-point • ALD/CVD ReRAM Properties

• VRRAM Integration & Challenges

 Selector-less Cell for VRRAM

• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies

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Scaling Technology of NAND Flash

 Lith Sh i k A F i  D bl PT  Q d l PT  Litho. Shrink : ArF-imm.  Double-PT  Quadruple-PT  # of cells increase : 64  128 ?  Vertical 3-D Stack

 Multi-Bit : 2  3  4 bit ? (data processing + ECC )

QPT /DPT 0.1 ] CG Planar FG Multi‐bit /DPT 64cell NAND 1 10 Rule [nm ] FG Air Physical DR 100 Design STI Air Gap 3D NVM era 2D NAND era 1000 1994 2004 2014 2024 Y 2xnm NAND _Year

Source : 2010 IEDM, page 98 & page 103

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Scaling Barriers of NAND Flash

 Scaling Barriers seem difficult to be overcome from 10 nodes.  WL-WL leakage : High PGM_V, Tun_Oxide  (Etun.OX. ~ EWL)

 # of electron decrease : Cstorage  (High-K)  Bigger cell coupling : Thin storage, ECC 

3D NVM [Parasitic capacitance coupling of FG] J.‐D. Lee, IEEE EDL, pp. 264‐266, 2002 3D NVM

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Scaling Breakthrough with 3D Structures

 Planar > VNAND for sub 20nm > VRRAM for sub 10nm scaling

TCAT (VNAND)

 Planar > VNAND for sub-20nm > VRRAM for sub-10nm scaling

VRRAM (Vertical ReRAM)

ReRAM Cell

J H Jang Samsung 2009 VLSI Tech p 192 I G Baek Samsung 2011 IEDM p 737 J.H. Jang, Samsung, 2009 VLSI Tech., p. 192. I.G. Baek, Samsung, 2011 IEDM, p. 737.

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 Introduction

• NAND Scaling Challenges

 Samsung Vertical ReRAM (VRRAM)

• VRRAM vs. 3D cross-point

• ALD/CVD ReRAM Properties

 Selector-less Cell for VRRAM

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3D ReRAM Technology

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 C t # f C iti l k

Fabrication Cost of 3D X-point ReRAM

 Cost ~ # of Critical masks

 The # of stacks is limited by the

affordable # of masks

 Cost effective # of stacks

< 8 stacks (4 stacks with DPT)

 Cost ~ Lithography tools

 EUV must be used to reach

> 512Gb even with 2bit MLC

 Only 2 more generations may be

covered with 3D X-point ReRAM

Chip area x Cell efficiency 100mm2

 3D X-point is only

a temporary solution

Chip area x Cell efficiency = 100mm2_, 2bit MLC, 4F2_{unit cell assumed}

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Scalability of VRRAM

 Compared to 3D X-point,

the # of critical masks relatively independent of the # of stacks.

 Compared to VNAND,

~ smaller cell area and ~ shorter stack height

V-RRAM V-NAND

Poly _{Switching material}

~ shorter stack height.

WL WL e e e e e e • Short ch. effect Vertical coupling Poly channel CTF stack Electrode Switching material (direct tunneling limited > 5 nm) •WL leakage WL WL • Vertical coupling • Charge spreading g J.D. Choi, Samsung, 2011 VLSI, p. 178.

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Process Requirements of VRRAM



Cell material deposition with high step coverage



High A/R dry etching



High A/R dry etching



Selective wet etching, treatment



Good diffusion barrier etch stopper materials



Good diffusion barrier, etch stopper materials



Low heat budget



3D inspection methodology



3D inspection methodology



…

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 Introduction

 Samsung Vertical ReRAM (VRRAM)

• VRRAM vs. 3D cross-point

• ALD/CVD ReRAM Properties

 Selector-less Cell for VRRAM

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 TMO : PVD Ta / ALD Ta₂O₅ ( ~ Ta₂O_{5 x} )

Reference Planar ReRAM

 TMO : PVD Ta / ALD Ta₂O₅( Ta₂O_5-x)

 Electrodes : PVD TiN (TE), CVD TiN (BEC)

 I_sw < 100uA, V_sw < 2.5V (pulse)

10 10-5 R ead @ 0.2 V 10-3 SET V_G: 2 V  t_sw ~ 10ns  Endurance > 1E6 10-7 10-6 10-5 e nt ( A ) @ 10-6 10-5 10-4 e nt ( A ) SET V_G: 2 V R ESET V_G:3 V 10-9 10-8 10 Cu rr e SET: 10n s/2.5V R ESET: 10n s/-2.5V 10-9 10-8 10-7 Cur re Set Reset 100 101 102 103 104 105 106 107 10 Cycles (N) -2 -1 0 1 2 10 Drain Voltage (V)

1 order of S/W window with >1E6 endurance

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PVD-free Planar ReRAM

 TMO : ALD Ta₂O₅

 Electrodes : CVD TiN (TE, BEC)

 No memory switching : leaky

Cl f CVD TiN TE h TiN/T O i i i

TOF-SIMS depth profiles of

 Cl from CVD TiN TE enhances TiN/Ta₂O₅ intermixing

 TaN, TaO generation at the interface

10-5 10-4 10-3 (A ) p p PVD TiN/ALD Ta₂O₅, CVD TiN/ALD Ta₂O₅ 10-8 10-7 10-6 Cur rent C V D TiN / A LD Ta₂O ₅ -3 -2 -1 0 1 2 3 10-9 Voltage (V)

No S/W window poor CVD TiN interface quality No S/W window, poor CVD TiN interface quality

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 ALD based diffusion barrier with optimum thickness

S/W Properties with a Diffusion Barrier

10-4

10-3

 ALD based diffusion barrier with optimum thickness

10-7 10-6 10-5

rrent (A

)

10-9 10-8 10

Cu

r

C V D TiN B arrier + C V D TiN TaO x B arrier layer C V D TiN -2 -1 0 1 2 10-10

Voltage (V)

C V D TiN TaO x

 Reference S/W properties are reproduced with

only CVD and ALD processes

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10-5

Reliabilities with a Diffusion Barrier

103 105 a il (hr) 85o_C 10 years 180o_C 10-6 10 (A ) R ead @ 0.2 V 101 10 T ime to f a P V D (R ef.) B arrier + C V D TiN 250o_C 200o_C 10-7 Cur rent SET: 10n s/2.5V R ESET 10 / 2 5V B arrier + C V D TiN 2.0 2.2 2.4 2.6 2.8 3.0 10-1 1000/T (1000/K) T _{C V D TiN} 100 101 102 103 104 105 106 107 10-8 Cycles (N) R ESET: 10n s/-2.5V C V D TiN

Endurance : > 1E6 Retention : ~ 10yrs @85C

 No critical reliability degradation was observed

with CVD TiN + ALD barrier

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 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

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V ti l NAND

i l

d

Process Integration of VRRAM (1/2)



Vertical NAND processes

are mainly used

except for the cell stack, vertical electrode and selection Tr.

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Process Integration of VRRAM (2/2)

VNAND (TCAT/BiCS) VRRAM

Storage layer ONO TMO/Barrier

Vertical Channel Poly-Si TiN (VE)

Horizontal Line W / poly Si (W/L) W (HE)

Selection Tr High V, Low I Low V, High I

Process Temp High (>700C) Low (<400C)

Process Temp. High (>700C) Low (<400C)

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 TMO : ALD Barrier / ALD Ta O

S/W Properties of VRRAM

 TMO : ALD Barrier / ALD Ta₂O₅

 Electrodes : CVD TiN (VE), CVD W/TiN (HE)

 I_sw < 80uA, V_sw < 4V

10-3

 t_sw < 1us (due to high parasitic RC)

 Endurance > 1e2 10-6 10-5 n t (A ) R ead @ 0.2 V 6 10-5 10-4 10-3 n t (A )

I_reset: 80 μA C .C : 50μA

8 10-7 10 Cur re n SET: 1μsec/4V R ESET: 1μsec/-5V 10-8 10-7 10-6 Curr e n V R R A M 100 101 102 10-8 Cycles (N) -4 -3 -2 -1 0 1 2 3 4 10-9 Voltage (V)

First reported results using PVD-free process in a vertical structurep g p

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Challenges for VRRAM

Demonstrated VRRAM using cost effective 3D process.

But the major challenges for VRRAM include;

Demonstrated VRRAM using cost effective 3D process.



Self-Rectifying Cell (SRC)

 SRC reduces leakage currents and cell-to-cell disturbance

 bl l i

 enables larger array size

- Highly non-linear, asymmetric I-V characteristics are necessary

Hi h

ll ffi i



High cell efficiency

 Larger memory block with smaller overhead chip area

- Low operation current needed p

- Layout optimization of driving circuits and vertical interconnection are necessary

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 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

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Selector

½ V d h

½ V read scheme and sneak current

 Need selector (function)

to avoid sneak current

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Why Selector-less (Self-Rectifying) Cell

VRRAM Density  H.S. Yoon, Samsung, VLSI Tech., 2009 Cross-point Process complexity  Operation voltage  Operation voltage  X.A. Tran, IEDM 2011

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SRC Examples

ISSCC 2010, LETI Memory W/S 2011 – Unity

• Current ratio 1000:1

i i l ( )

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IEDM 2010 – Gwangju Inst. Sci. Tech. (GIST)

SRC Examples

• Back-to-back connection of HfO/ZrO stackBack to back connection of HfO/ZrO stack

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IEDM 2011 – Nanyang Tech. Univ. (NTU)

SRC Examples

• Simple n+Si/HfOx/Ni stackSimple n+Si/HfOx/Ni stack

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VLSI 2012 – Macronix

SRC Examples

• 0T1R CBRAM array0T1R CBRAM array

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In Short ...

Targeting to what Unity presented in this W/S last year.

But using fab-friendly materials (transition metal oxides)

LETI Memory W/S 2011 – Unity LETI Memory W/S 2011 – Unity

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 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

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Conclusions

1. Vertical ReRAM (VRRAM) has been successfully

demonstrated as a cost effective post-NAND solution.

2. Compared to the 3D X-point ReRAM, VRRAM has advantages

when stacking >8 stacks with relaxed patterning technology. g g g

We expect VRRAM technology can be extensible beyond 1Tb

era with ArF-i tools.

3. Self-rectifying cell technology would be main challenges for VRRAM production.

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Acknowledgement

In Gyu Baek & Jungdal Choi

In-Gyu Baek & Jungdal Choi

Advanced Process Development Team

S i d t R&D C t

Semiconductor R&D Center Samsung Electronics

4 th Workshop on Innovative Memory Technologies

Resistive RAM (

Resistive RAM (ReRAM

ReRAM) Technology

) Technology

for High Density Memory Applications

for High Density Memory Applications

for High Density Memory Applications

for High Density Memory Applications

Sunjung Kim

Sunjung Kim

S

i

d

t

R&D C

t

S

i

d

t

R&D C

t

Semiconductor R&D Center

Semiconductor R&D Center

SAMSUNG Electronics

SAMSUNG Electronics

Contents

 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

Scaling Technology of NAND Flash

Scaling Barriers of NAND Flash

Scaling Breakthrough with 3D Structures

Contents

 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

3D ReRAM Technology

Fabrication Cost of 3D X-point ReRAM

 3D X-point is only

a temporary solution

Scalability of VRRAM

Process Requirements of VRRAM

Cell material deposition with high step coverage

High A/R dry etching

High A/R dry etching

Selective wet etching, treatment

Good diffusion barrier etch stopper materials

Good diffusion barrier, etch stopper materials

Low heat budget

3D inspection methodology

3D inspection methodology

…

Contents

 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

Reference Planar ReRAM

PVD-free Planar ReRAM

S/W Properties with a Diffusion Barrier

rrent (A

)

Cu

r

Voltage (V)

 Reference S/W properties are reproduced with

only CVD and ALD processes

Reliabilities with a Diffusion Barrier

 No critical reliability degradation was observed

with CVD TiN + ALD barrier

Contents

 Introduction

 Samsung Vertical ReRAM (VRRAM)

 Selector-less Cell for VRRAM

V ti l NAND

i l

d

Process Integration of VRRAM (1/2)

Vertical NAND processes