Lecture 3 Addressing Modes, Instruction Samples, Machine Code, Instruction Execution Cycle

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Lecture 3 – Addressing Modes, Instruction Samples, Machine Code, Instruction Execution Cycle

Contents

3.1.  Register Transfer Notation ... 2 

3.2.  HCS12 Addressing Modes ... 2 

1.  Inherent Mode (INH) ... 2 

2.  Immediate Mode (IMM) ... 3 

3.  Direct mode (DIR) ... 3 

4.  Extended mode (EXT) ... 3 

5.  Relative mode (REL) ... 3 

6.  Indexed Mode (INDEX) ... 4 

a.  Indexed addressing Modes with Constants Offsets ... 4 

b.  Indexed Addressing Modes with Offset in an Accumulator ... 4 

c.  Auto Pre/Post increment/Decrement Indexed Addressing Modes ... 5 

d.  16-Bit Offset Indexed Indirect Mode ... 5 

e.  Accumulator D Indirect Indexed Addressing ... 5 

3.3.  A Sample of HCS12 Instructions ... 6 

1.  The LOAD instructions ... 6 

2.  Load Effective Address Instruction ... 6 

3.  The STORE instruction ... 7 

4.  Register to Register Transfer Instructions ... 7 

5.  Exchange Instructions ... 7 

6.  Sign Extension Instructions ... 8 

7.  Memory to Memory Move Instructions ... 8 

8.  The ADD instruction ... 8

9.  The SUB instruction ... 8 

10.  Shift instructions ... 9 

11.  Programming Examples ... 10 

3.4.  HCS12 Instructions ... 11 

3.5.  The HCS12 Machine Code ... 14 

3.6.  Decoding Machine Language Instructions ... 14 

3.7.  Instruction Execution Cycle ... 16 

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3.1. Register Transfer Notation ()

 A B X IX M + v –

^

The content of the address specified inside the parenthesis.

Transferred to Accumulator A Accumulator B

Accumulator A or accumulator B Index register X

Memory location Add

OR Subtract And Here are examples:

A  15 A  $15 A  ($2015) A  A + ($2F)

The decimal value of 15 is loaded into A.

The hexadecimal value of 1516 (2110) is loaded into A.

The contents of memory location $2015 is loaded into A.

The contents of memory location $2F is added to the contents of A 3.2. HCS12 Addressing Modes

An HCS12 instruction consists of 1 or 2 bytes of opcode and 0 to 5 bytes of operand addressing information:

 The opcode specifies the operation to be performed and the addressing mode used to access the operand.

 The operand contains the information needed for the operation

The addressing mode determines how the CPU accesses registers or memory locations for an instruction to be executed. The HCS12 supports several addressing mode: inherent, immediate, direct, extended, relative, indexed addressing with constants offsets, indexed addressing with Offset in an accumulator, auto pre/post increment/decrement indexed

addressing, 16-bit offset indexed indirect mod, and accumulator D indirect indexed addressing.

Address and data values are represented in binary format. A large binary number is not practical for human beings to deal with, and therefore, decimal and hexadecimal formats are often used.

1. Inherent Mode (INH)

Instructions do not have operands.

CLRA Clear the content of the accumulator A

ABA Add the content of the accumulator A to the accumulator A and leave the result in the accumulator A

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INCA Increment the content of the accumulator A by 1 DECB Decrement the content of the accumulator A by 1 2. Immediate Mode (IMM)

The value of the operand is included in the instruction. The immediate value (8-bit or 16- bit) is preceded by #

LDAA #22 Load the decimal value of 22 into the accumulator A.

ADDA #@32 Add the octal value of 32 to the accumulator A.

LDD #$1000 Load the hexadecimal value of 1000 into the accumulator D.

Note: # is a prefix that indicates that the operand is actually the data (not address) 3. Direct mode (DIR)

This addressing mode is sometimes called zero-page addressing because it is used to access the operands in the address range of $0000 to $00FF. Since the address begin with $0000, only the low byte of the address of the operand need to be included in the instruction.

Address of operand  operand (low byte) + $0000 (base address of data section) ADDA $10 Add the value stored at the memory location $0010 to

the accumulator A.

SUBA $20 Subtract from the accumulator A the value stored at the memory location $0020.

LDD $30 Load the contents of the memory locations at $0030 and $0031 into double accumulator D.

4. Extended mode (EXT)

In the addressing mode, the full 16-bit address (2-byte address) of memory location is included in the instruction

Address of operand  operand (2-byte)

ADDA $1003 Add the value stored at the memory location with the effective address of $1103 to the accumulator A.

LDX $1000

Load the 16-bit value stored at the memory location with the effective address of $1000 into the index register X. The byte at $1000 will be loaded into the upper byte of X and the byte at $1001 will be loaded into the lower byte of X.

ADDD $1030

Add the 16-bit value stored at the memory location with the effective addresses of $1030 and $1031 to double accumulator D.

5. Relative mode (REL)

The relative addressing mode is used only for branch instructions that can change the direction of the program flow. The distance of the branch (or jump) is referred as branch offset. There are short and long conditional branch instructions.

Short branch instructions consists of an 8-bit opcode and a signed 8-bit offset – ranged from $80 (–128) to $7F (+127).

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Long branch instructions consists of an 8-bit prebyte, an 8-bit opcode, and a signed 16-bit offset contained in 2 bytes following the opcode. The range for long branch instructions is from $8000 (–32768) to $7FFF (+32676).

In the following example, BEQ is a short branch instruction that branches to the label

“There” the condition is met.

...

BEQ There

ADDA #10

...

There: DECB

6. Indexed Mode (INDEX)

In the indexed mode, the effective address of an operand is calculated by adding the base address, which is stored in a base register such as IX, IY, SP, or PC, to the offset.

a. Indexed Addressing Modes with Constants Offsets The syntax of the operand of this indexed mode is:

n, r where

n is a 5-bit, 9-bit, or 16-bit constant r is the base register (IX, IY, SP, or PC)

Address of operand  constant + [IX, IY, SP, or PC]

ADDA 10, X Add the value stored at the memory location pointed by the sum of 10 and the contents of the index register X to accumulator A.

A  [10 + IX] + A

LDAA 3, Y

Load the contents of the memory location pointed by the sum of 3 and the contents of the index register Y into the accumulator A.

A  [3 + IY]

SUBA 0, X

Subtract the value stored at the memory location pointed by the sum of 0 and the contents of the index register X from the accumulator A.

A  A – [0 + IX]

b. Indexed Addressing Modes with Offset in an Accumulator The syntax of the operand of this indexed mode is:

acc, r where

acc can be A, B, or D

r is the base register (IX, IY, SP, or PC)

Address of operand  [A, B, or D] + [IX, IY, SP, or PC]

STAA B, X Store the value in the accumulator A into the memory location pointed by the sum of the accumulator B and the contents of the index register X.

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[B + IX]  A

LDAB A, Y

Load the contents of the memory location pointed by the sum of A and the contents of the index register Y into the accumulator A.

A  [B + IY]

LDX D, SP

Load two bytes from the memory locations into IX

 The high byte (MB) from the location [D + SP]

 The low byte (LB) from the location [1+ D + SP]

IX (high byte)  [D + SP]

IX (low byte)  [1 +D + SP]

c. Auto Pre/Post increment/Decrement Indexed Addressing Modes The syntax of the operand of this indexed mode is:

Syntax Effective

Address

New Value of Base Register r

Pre-decrement n, –r r – n r r – n

Pre-increment n, +r r + n r r + n

Post-decrement n, r – r r r – n

Post-increment n, r+ r r r + n

Here are examples.

STAA 2, –X IX  IX – 2 [IX]  A ADDA 3, +Y IY  IY + 3

A  A + [IY]

LDAB 4, X– B  [IX]

IX  IX – 4 STAB 8, Y+ [IY]  B

IY  IY + 8 d. 16-Bit Offset Indexed Indirect Mode

The syntax of the operand of this indexed mode is: [n, r]

where

n is 16-bit offset

r is the base register (IX, IY, SP, or PC) Here are examples.

STAA [2, X] [ [2 + IX] ]  A ADDA [3, Y] A  A + [ [IY + 3] ]

e. Accumulator D Indirect Indexed Addressing

The syntax of the operand of this indexed mode is: [D, r]

where

r is the base register (IX, IY, SP, or PC)

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Here are examples.

JMP [D, X] Jump to the address [ [D + IX] ]

This addressing mode is often used for interrupt vector table.

3.3. A Sample of HCS12 Instructions

HCS12 instructions are case-insensitive. Upper case letters or lower case letters are acceptable to the compiler. As a rule of thumb, there is a preferable style which is commonly used:

HCS12 Instructions Use upper case letter

Operands or variables Use upper case for the first letter, and lower case for the rest of the letters.

Constant Use upper case letter

1. The LOAD instructions

A group of instructions that place a value or copy the contents of a memory location (or locations) into a register (A, B, D, IX, IY, SP)

<opr> can be immediate, direct, extended, or index mode Examples: LDAA $10

LDX #$1000

2. Load Effective Address Instruction

Load the effective address (n + r), not the content of memory location, into registers (IX, IY, SP)

Examples: LEAX B, Y ; IX  B + IY LEAY A, Y ; IY  A + IY LEAS 4, X ; SP  4 + IX

Mnemonic Function

Load A Load B Load D Load SP

Load index register X Load index register Y

Operation A  [opr]

B  [opr]

A:B  [opr]:[opr+1]

SP  [opr]:[opr+1]

X  [opr]:[opr+1]

Y  [opr]:[opr+1]

LDAA <opr>

LDAB <opr>

LDD <opr>

LDS <opr>

LDX <opr>

LDY <opr>

Mnemonic Function

Load effective address into SP Load effective address into X Load efective address into Y

Operation

SP  effective address X  effective address Y  effective address LEAS <opr>

LEAX <opr>

LEAY <opr>

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3. The STORE instruction

A group of instructions that store the contents of a register (A, B, D, IX, IY, and SP) into a memory location or memory locations

<addr> can be direct, extended, or index mode Examples: STAA $20

STAA 10, X

STD $10

STD $1000

STD 0, X

4. Register to Register Transfer Instructions

TAB Transfer the content of A to B B  A TAP Transfer the content of A to CCR CCR  A TBA Transfer the content of B to A A  B TFR reg1, reg2 Transfer the content of reg1 to reg2 reg2  reg1 TPA Transfer the content of CCR to A A  CCR TSX Transfer the content of SP to IX IX  SP TSY Transfer the content of SP to IY IY  SP TXS Transfer the content of IX to SP SP  IX TYS Transfer the content of IY to SP SP  IY Examples:

TFR A, X ; A is signed-extended to 16 bits and assigned to IX TFR Y, B ; B  IY[7:0], B receives lower byte of IY (bits 7:0) 5. Exchange Instructions

EXG reg1, reg2 reg1 ↔ reg2, exchange the contents of reg1 and reg2 XGDX D ↔ IX, exchange the contents of D and IX

XGDY D ↔ IY, exchange the contents of D and IX Examples:

EXG D, X ; D ↔ IX

EXG X, A ; IX  $0000 + A, A  X[7:0]

Mnemonic Function Operation

Store A in a memory location Store B in a memory location Store D in a memory location Store SP in a memory location Store X in a memory location Store Y in a memory location

m[opr]  [A]

m[opr]  [B]

m[opr]:m[opr+1]  [A]:[B]

m[opr]:m[opr+1]  [SP]

m[opr]:m[opr+1]  [X]

m[opr]:m[opr+1]  [Y]

STAA <opr>

STAB <opr>

STD <opr>

STS <opr>

STX <opr>

STY <opr>

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6. Sign Extension Instructions

SEX reg1, reg2 reg1 is signed-extended to 16 bits and assigned to reg2 Examples:

SEX A, X ; A is signed-extended to 16 bits and assigned to IX SEX CCR, Y ; CCR is signed-extended to 16 bits and assigned to IY 7. Memory to Memory Move Instructions

MOVB <src>, <dest> Move a byte (8-bit) from [src] to dest; dest  [src]

MOVW <src>, <dest> Move a word (16-bit) from [src] to dest; dest  [src]

Examples:

MOVB #$30, $1800 ; [$1800]  $30 MOVW Var1, Var2 ; Var2  Var1 MOVW 1, X, 1, Y ; [1 +IY]  [1 + IX]

8. The ADD instruction

A group of instructions perform addition operation

<opr> can be immediate, direct, extended, or index mode Examples: ADDA #10 ; A  A + 10

ADDA $20 ; A  A + [$0000 + $20]

ADDD $FB46 ; D  D + [$FB46]

9. The SUB instruction

A group of instructions perform subtract operation

ABA ABX ABY ADCA <opr>

ADCB <opr>

ADDA <opr>

ADDB <opr>

ADDD <opr>

Mnemonic

Add B to A Add B to X Add B to Y

Add with carry to A Add with carry to B Add without carry to A Add without carry to B Add without carry to D

A  [A] + [B]

X  [X] + [B]

Y  [Y] + [B]

A  [A] + [opr] + C B  [B] + [opr] + C A  [A] + [opr]

B  [B] + [opr]

D  [D] + [opr]

Function Operation

Mnemonic Function Operation

SBA SBCA <opr>

SBCB <opr>

SUBA <opr>

SUBB <opr>

SUBD <opr>

Subtract B from A

Subtract with borrow from A Subtract with borrow from B Subtract memory from A Subtract memory from B Subtract memory from D

A  [A] - [B]

A  [A] - [opr] - C B  [B] - [opr] - C A  [A] - [opr]

B  [B] - [opr]

D  [D] - [opr]

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<opr> can be immediate, direct, extended, or index mode Examples: SUBA #10

SUBA $10

SUBA 0, X

SUBD 10, X

10. Shift Instructions

Shift instructions are useful for bit field manipulation. They can be used to speed up the integer multiply and divide operations if one of the operands is a power of 2. The HCS12 has shift instructions that can operate on accumulators A, B, and D or a memory location. A memory operand must be specified using the extended or indexed (direct or indirect) addressing modes.

Logical Shift Left

LSL <opr>

LSLA LSLB

memory location <opr> is shifted left one place accumulator A is shifted left one place

accumulator B is shifted left one place The operation is

LSLD accumulator D is shifted left one place The operation is

Logical Shift Right

LSR <opr>

LSRA LSRB

memory location <opr> is shifted right one place accumulator A is shifted right one place

accumulator B is shifted right one place The operation is

LSRD accumulator D is shifted right one place The operation is

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11. Programming Examples

Example 3.11.1 – Compute Y = 7 * X Write an assembly code to compute Y = 7 * X Solution:

Register Transfer

Notation Arithmetic Assembly Code

A  X A = X LDAA X

B  A B = X TAB

A  2 * A A = 2 * X LSLA

A  2 * A A = 4 * X LSLA

A  2 * A A = 8 * X LSLA

A  A – B A = 8 * X – X SBA

Y  A Y = 7 * X STAA Y

Alternative solution:

Register Transfer

Notation Arithmetic Assembly Code

A  X A = X LDAA X

B  A B = X TAB

B  2 * B B = 2 * X LSLB

A  A + B A = X + 2 * X = 3 * X ABA

B  2 * B B = 4 * X LSLB

A  A + B A = 3 * X + 4 * X ABA

Y  A Y = A STAA Y

Example 3.11.2 – Arithmetic Program

Design a program that will perform the following computation voltage = 9 * current – 25.

Solution:

ORG $0 ; location of variables

current DS.B 1 ; the value of current

voltage DS.B 1 ; the value of voltage

;

ORG $C000 ; the starting address of the program LDAA current ; A = current

TAB ; B = A = current LSLA ; A = 2 * current LSLA ; A = 4 * current LSLA ; A = 8 * current

ABA ; A = A + B = 8 * current + current = 9 * current SUBA #25 ; A = 9 * current – 25

STAA voltage ; voltage = A = 9 * current – 25 SWI

END

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Example 3.11.3 – Determine range of Variables

In the previous example, given that the voltage and current shall be defined as 1 byte unsigned variables, determine the range of current for which a solution can be computed.

(From Dr. Tavora’s notes)

 Constraints:

0current voltage, 255  0all computations255

 Valid range

9* 255 255 28.3 28

9

9* 25 0 25 2.77 3

9 ,

3 28

current current current

voltage current current current

Therefore current

     

       

 

Example 3.11.4 – Determine range of Variables

In the previous example, given that the voltage and current shall be defined as 1 byte signed variables, determine the range of current for which a solution can be computed. (From Dr.

Tavora’s notes)

 Constraints:

128 current voltage, 127 128 all computations 127

      

 Valid range

128 9* 127 14.22 14.22 14 14

128 9* 25 127 11.44 16.88

11 16

,

11 14

current current current

voltage current current

current Therefore

current

          

        

  

  

3.4 HCS12 Instructions

Appendix A (pp.758 – 775) – Instruction listing by alphabetical order

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Note:

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3.5 The HCS12 Machine Code

Each HCS12 instruction consists of 1 to 2 bytes of opcode and 0 to 5 bytes of operand information. These bytes are presented in hexadecimal numbers:

Instruction = opcode + operand

 Opcode specifies the operation to be performed.

 Operand specifies a value or the address where the value can be found to be used in the operation.

Assembly instruction Machine instructions (in hex format)

LDAA #29 86 1D

STAA $00 5A 00

ADDA $02 9B 02

STAA $01 5A 01

MOVB $1000, $2000 18 0C 1000 2000

INY 02 3.6 Decoding Machine Language Instructions

1. Procedure

 Compare the first one or two bytes with the opcode table to identify the corresponding assembly mnemonic and format.

 Identify the operand bytes after the opcode field.

 Write down the corresponding assembly instruction.

 Repeat step 1 to 3 until the machine code file is exhausted.

Example 3.6.1 – Decoding Machine Code

Decode the following machine code to its corresponding assembly instructions:

96 30 8B 07 5A 30 96 31 Solution:

The decoding process starts from the leftmost byte. We next look up the machine code table to see which instruction it corresponds to.

Instruction 1:

 The first byte 96 corresponds to the instruction: LDAA DIR.

 The second byte, 30, is the direct address.

 Therefore, the first instruction is LDAA $30.

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Instruction 2:

 The third byte (8B) corresponds to the instruction: ADDA IMM.

 The immediate value is 07.

 Therefore, the second instruction is ADDA #$07.

Instruction 3:

 The fifth byte (5A) corresponds to the instruction STAA DIR.

 The DIR address is the next byte 30.

 Therefore, the third instruction is STAA $30.

Instruction 4:

 The seventh byte (96) corresponds to the instruction LDAA DIR.

 The DIR value is the next byte 31.

 Therefore, the four instruction is LDAA $31.

Therefore, the equivalent assembly code for the machine code 96 30 8B 07 5A 30 96 31 is

LDAA $30

ADDA #$07

STAA $30

LDAA $31

Example 3.6.2 – Decoding Machine Code

Decode the following machine code to its corresponding assembly instructions:

96 10 5B 15 C6 12 7C C8 AF Solution:

96  LDAA DIR  96 10  LDAA $10 5B  STAB DIR  D7 15  STAB $15 C6  LDAB IMM  C6 12  LDAB #$12 7C  STD EXT  FD C8 AF  STD $C8AF Example 3.6.3 – Decoding Machine Code

Decode the following machine code to its corresponding assembly instructions:

86 12 D6 10 54 18 06 5A 12 42 86 12 D6 10 54 1B 97 12 4C

Solution:

86  LDAA IMM 86 12 LDAA #$12

D6  LDAB DIR D6 10 LDAB $10

54  LSRB 18 06  ABA

5A  STAB DIR 97 12  STA $12

42  INCA

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Example 3.6.4 – Decoding Machine Code

Decode the following machine code to its corresponding assembly instructions:

B6 20 00 D6 15 18 06 7C 10 00 42 48 7C 13 45 Solution:

B6  LDAA EXT B6 20 00  LDAA $2000

D6  LDAB DIR D6 15  LDAB $15

18 06  ABA

7C  STD EXT  FD 10 00  STD $1000

42  INCA INH  INCA

48  LSLA INH  LSLA

7C  STD EXT  FD 13 45  STD $1345 3.7 Instruction Execution Cycle

In order to execute a program, the microprocessor or microcontroller must access memory to fetch instructions or operands. The process of accessing a memory location is called a read cycle. The process of storing a value into a memory location is called a write cycle. The process of executing an instruction is called an instruction execution cycle.

When executing an instruction, the HCS12 performs a combination of the following operations:

 One of multiple read cycles to fetch instruction opcode byte(s) and addressing information.

 One or two read cycles to required to fetch the memory operand(s)

 The operation specified by the opcode

 One or two write cycles to write back the result to either a register or a memory location

1. Example 3.7.1 – Executing Instruction Cycle (assume 8-bit data bus) Consider the following instruction sequence:

ORG $C000 LDAA $2000 ADDA $3000 STAA $2000

Assembly Instruction Memory location Opcode

LDAA $2000 $C000 B6 20 00

ADDA $3000 $C003 BB 30 00

STAA $2000 $C006 7A 20 00

Instruction: LDAA $2000

Step 1. Place the value in PC on the address bus with a request to read the contents of that location.

Step 2. The opcode byte $B6 at $C000 is returned to the CPU and PC is incremented by 1.

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Step 3. CPU performs two read cycles to obtain the extended address $2000 from locations $C001 and $C002. At the end the value of PC is incremented to

$C003.

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Step 4. The CPU performs another read to get the contents of the memory location at

$2000, which is $19. The value $19 will be loaded into accumulator A.

Figure

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References

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