Abstract_ECL technology has propagation delay which is fast and able to work under high frequency that is around 125-200MHz. This research aims at analyzing and designing 2 to 4 Decoder IC using ECL Technology (Emitter Couple Logic). Decoder ECL uses shared voltage -5,2V with external capacitor which is 15pF, Rc= 2kΏ and RE= 10kΏ.
Specification of characteristic simulation design of voltage transfer characteristic (VTC) is VIL = -1,06V; VOL = -1,23V; VIH = -0,94V; VOH= -0,81V; Noise Margin NMH = 0,13V and NML = 0,222v. Simulation of propagation delay on CL 15pF is tPLH = 10,25ns and tPD= 5,655ns. Power dissipation produced is 3,68mV. The result of simulation design shows that specification of IC 2 to 4 Decoder ECL has better speed and power dissipation than decoder TTL (74139) and decoder CMOS (4555).
I. INTRODUCTION
The development of electronic technology was started with the use of vacuum tube as active component in electronic series before semiconductor transistor replaces it. The development of microelectronic technology especially for those of monolitical is able to produce interfaced circuit by combining all active and passive components in one chip.
Based on the number of transistor component used, integrated circuit is classified into five groups that is SSI (small scale integration), MSI (Medium Scale integration), LSI (large scale integration) and UVLSI (ultra very large scale integration). Based on its use, IC is classified into two groups that is analog IC and digital IC. Digital IC can be produced using MOS technology (Metal Oxide Semiconductor) and bipolar technology. IC using bipolar technology are RTL (Resistor Transistor Logic), DTL (Diode Transistor Logic), TTL (Transistor), ECL (Emitter Coupled Logic) and HTL (High Transistor Logic). Bipolar technology IC is known to have high dissipation power. However, in terms of propagation delay, IC using bipolar technology has faster than IC of MOS technology. With the increase demand for high performance servers in the mid-range computer family, Emiter Coupled Logic (ECL) technology has gained new attention [1]. Several new ECL configuration have been developed since then with the aim of reducing the ECL power and increasing the speed [2][3].
II. DESIGN DECODER ECL CIRCUIT
In the circuit design of 2-to-4 Decoder ECL Gate, in order to know the value of propagation delay the output of circuit is connected to external capacitor CL. CL functioning as external loading connected from circuit output to VEE. Circuit configuration 2-to-4 Decoder ECL using external capacitor is shown in Fig. 1.
Fig.1. Configuration 2-to-4 Decoder Circuit
Additionally, there is also other loading component which is external output resistance. However, this resistance does not influence time function so that it is used to know the impact of loading to propagation delay
The first step in designing IC circuit 2-to-4 Decoder ECL is changing NAND gate into OR gate. Then, it changes logic gate in circuit 2-to-4 Decoder into ECL gate using NPN bipolar transistor component, resistor, and current source. The design that will be conducted is by designing resistor value and current source in order to obtain ideal design. Transistor design in Decoder is conducted in every gate compiling IC (Fig.1), where each gate is made from NPN bipolar transistor, resistor and current source. As shown in Fig.1, IC 2-to-4 Decoder is compiled from two inverter gates and four OR gate of three output. Then, each node in circuit is given certain number. In the design of ECL circuit, VCC is connected to ground and VEE is connected to negative current source.
The configuration of ECL decoder circuit in each logic gate is shown in Fig 2.
ANALYZING AND DESIGNING 2 TO 4 DECODER
EMITER COUPLE LOGIC (ECL)
Agung Darmawansyah1), Asih Setyarini2)
1,2)
Electrical Engineering Department University of Brawijaya Malang, Indonesia
Fig. 2. 2-to-4 ECL Decoder complete circuits
III. CALCULATION PARAMETERS DECODER ECL
ECL gate is a technology using NPN bipolar transistor to form ECL integrated circuit; thus we need to know NPN BJT parameters used in designing IC 2-to-4 Decoder ECL. In designing ECL, these simulation need three parameters of BJT NPN transistor, which are
βB, IS, and VT. βF is reinforcer of transistor current, Is is saturation current and VT is thermal transistor voltage of 0,025 V.
Calculation VTC and noise margin on ECL inverter gate.
Analysis of inverter circuit for VOH and VOL is obtained under two conditions. When Vi > VR, we obtain VOL and when Vi < V R, Q1 transistor is active and Q2 transistor is not active. Thus, IC1 current flowing is almost the same as IEE current and from that condition we can obtain VOL;
VOL = - IC1RC1 - VBE3 (1)
By inserting ICI value and RCI value and also VBES in 1 Equ. then the calculation of VOL is as follows
3
1 C BE
C
OL i R v
v =− −
7 . 0 10 2 10 3 .
0 × 3× × 3−
−
= −
OL v
volt vOL =−1.3
VOH = - VBE3 (2)
Value of VBE in transistor has value of 0,7 V for germanium-based transistor, then VOH = -0,7 V.
Reference voltage is voltage using as comparison. It functions to determine which transistor is active or not. Reference voltage is average value from high and low output voltage. Function of reference voltage is shown in Equ. (3). by inserting VOH and VOL calculated in Equ. (3), obtained reference voltage with the value;
2
OL OH REF
V V
V = − (3)
1
2 3 . 1 7 . 0
− = − − = REF V
To obtain Equ. of VIL and VIH in ECL gate circuit as shown in Equ. (4) and Equ. (5), by inserting value of VREF = -1V, VT = 0.025V, Rc = 2k Ώ and IEE – 0.3 mA into the Equ. of (5), then the calculation of VIL and VIH is
− −
= ln 1
T EE C T REF IL
V I R V V
V (4)
− × × × −
−
= 1
025 . 0
10 3 . 0 10 2 ln 025 . 0 1
3 3
=−1.078volt
− +
= ln 1
T EE C T REF IH
V I R V V
V (5)
− × × × +
−
= 1
025 . 0
10 3 . 0 10 2 ln 025 . 0 1
3 3
=−0.922volt
Noise margin shows relative resistance of logic family on noise. To obtain noise margin, we need to know the value of VIL, VIH, VOL, and VOH. By knowing the value of VIL = -1,078V, VIH = -0.922V, VOH = -0,7V, VOL = -1.3V, then the lower logic limit can be determined from the Equ. (6) and (7).
NMH = VOH −VIH (6)
= 0,222V
NML = VIL−VOL (7) = 0,222V
Calculation VTC and Noise Margin on OR Gate of Three Input of ECL.
Calculation of VIL, VIH, VOL, and VOH and noise margin of OR 3-input ECL is similar as analysis on the inverter gate, but in this analysis there are 8 input combinations to produce output value. However, in general it still uses two condition that is when V1 < VR obtain VOL due to the output on circuit OR 3 input arranged pararelly so that one input has more value than Vref, then we obtain the value of VOH and vice versa.
Fig.3. Noise Margin calculation result
Calculation of IIL and IIH on Inverter ECL Gate Input current of circuit IC 2-to-4 Decoder ECL is input current on inverter circuit, where input current is transistor basis current becoming the first input on circuit. In Fig. 2, it is shown that input current is transistor basis current Q1, Q4, Q9, Q14, Q19 and Q24. in this design analysis, we will only analyze basis current on inverter ECL circuit. When Vi > Vr can obtained IIH given by
(
+1)
= F EE IH I I
β (8)
By inserting the value of VIH = -0,7V, VBE = 0.7, IEE = 0.3 mA and βF = 20, and value of IIH, that is 14,28µA When Vi < VR, transistor Q1 is not active than IIL= 0. However, there is a formula IB when transistor in preliminary condition is given by
− =
= exp 1
T BE F S IL B V V I I I
β (9)
By inserting the value of βF = 20, VBE = 0.7V, VT=0.025 and IS= 2X1017, obtain value of IIL =1,44 µA.
Calculation IOL AND IOH on OR-3 Input ECL Gate
3 3 E EE OL OL E R V V I
I = = − (10)
By inserting value VOL=-1,3volt, VEE=-5,2V RE3=42kΩ, obtained IOL:
3 3 E EE OL OL E R V V I
I = = −
mA 092 . 0 10 42 2 . 5 3 . 1 3 = × + − =
Equ. (11) show the high output curent IOH;
4 4 E EE OH OH E R V V I
I = = −
(11) mA 107 . 0 10 42 2 . 5 7 . 0 3 = × + − =
Output current IC 2-to-4 Decoder ECL Gate is output transistor emitter current on gate circuit of OR 3-input ECL. Output current is emitter current in Q11, Q16, and Q26. in this design analysis, we will just analysis emitter current in transistor Q11.
Calculation IIL, IIH, IOH and Fan Out with Variation of RC and Re.
Current analysis and fan-out using variation of Rc and Re on circuit is conducted to know the influence of Rc and Re on the magnitude of fan out but the characteristic transfer of current has fixed value. Thus, this analysis will be influential for the analysis of the next IC parameter, that is propagation delay and power dissipation. Table 1 shows variation of Rc and Re that will be analyzed.
Table 1 Variation Value RC and RE
By considering the value of VIL VIH and VOH, then based on the calculation analysis of IIL, IIH, IOH, IOL, we can obtain the result of calculation of IIL, IIH, IOH, IOL and fan out as shown in Table 2.
Table 2
Fanout with variation RC and RE
Propagation Delay Analysis.
In the design of IC 2-to-4 Decoder ECL Gate, the value of propagation delay is 4ns. It is smaller then tPD from characteristic of IC TTL SN74ALS253 and IC CMOS HEF4555B, thus the value of Cl used can be counted using the Equ. (12).
2 ) ( ln ln − − + − −
= o OH
OH OL L O EE OL EE OH L E PD V t v V V C R V V V V C R
t (12)
By inserting value of Re = 42k Ώ , Rc = 2 k Ώ , VOL = 1,3 vol, VOH – 0.7 vol, VEE = -5.2 v, V0 (t) = -0.75 volt, βF = 20 and
F C O R R β
= ., then can obtained the value of CL
as follows. RC (Ω) RE (Ω) IEE (mA) IIL (µA)
IIH (µA)
IOH (mA) IOL (mA) Fan out 2k 42k 0,3 1,44 14,8 0,10 0,09 7
10k 0,3 1,44 14,8 0,45 0,39 31 500 42k 1,2 1,44 57,1 0,11 0,09 1
10k 1,2 1,44 57,1 0,45 0,45 7 RC
(Ω) RE (Ω) 2 k 42 k
2
7 , 0 75 , 0
7 , 0 3 , 1 ln 20
10 2 2 , 5 3 , 1
2 , 5 7 , 0 ln . 10 42 10 4
3 3
9
+ −
+ − × +
+ −
+ − × =
× − L L
C C
pF F CL
27 , 1
10 . 27 , 1
25 , 3129 10 . 4
12 9
= = =
− −
Because 2-to-4 Decoder ECL Gate consists of inverter gate and OR-3-input gate then conduct propagation delay analysis using two level of delay; that is total propagation delay which is the result of addition of propagation delay of inverter gate and OR 3-input gate. There is difference on level delay on output circuit so that conduct two propagation delay analysis on two outputs, that is output analysis Yo where propagation delay is influenced by converter gate and OR. Propagation delay analysis is conducted using value variation of RC and RE as shown in Table 3.
Table 3
Propagation Delay with Variation RC and RE
RC (Ω)
RE (Ω)
CL (F)
tPD (ns)
PD (mW)
PDP (pJ)
2k 42k
0,1p 0,314 2,0774 0,65 2p 6,25 2,0774 12,97 15p 46,94 2,0774 97,37 20p 62,49 2,0774 129,63
10k
0,1p 0,084 3,744 0,314 2p 1,68 3,744 6,29 15p 12,59 3,744 47,14 20p 16,79 3,744 62,86
500 42k
0,1p 0,3031 6,7574 2,048 2p 6,062 6,7574 40,96 15p 45,54 6,7574 307,73 20p 60,62 6,7574 409,63
10k
0,1p 0,075 8,424 0,632 2p 1,492 8,424 12,57 15p 11,19 8,424 94,26 20p 14,92 8,424 125,67
Power Dissipation and Power Delay Product Analysis
ECL power dissipation is obtained from Equ. (13), mean while power delay product (PDP) is obtained from Equ. (14).
EE TOT
D I V
P = (13) PDP = tPD.PD (14)
Power dissipation analysis refers to the calculation data fan out as shown in Table 3. Since analysis power dissipation needs current variable of Itot which is the summation of current IEE and emitter current on output transistor and it needs also VEE variable with the constants value of -5.2 V with the value variation of Rc as shown in Table 4.
Table 4
Calculation Data Result Power Dissipation RC
(Ω) RE (Ω)
IEE (mA)
IOH (mA)
IOL (mA)
PD (mW) 2k 42k 0,3 0,107 0,092 2,0774 10k 0,3 0,45 0,39 3,744 500 42k 1,2 0,107 0,092 6,7574
10k 1,2 0,45 0,45 8,424
IV. SIMULATION
This simulation is used as prove for the result of calculation. The simulation process conducted is;
• Voltage shift simulation (VTC) to know the value of VIl, VIH, VOL, VOH and noise margin. It is conducted using DC analysis.
• Current shift analysis to know the value of IIL, IIH, IOL, IOH and fan out. It is conducted using DC analysis.
• Power dissipation analysis is conducted to know the value of power dissipation using circuit. It is conducted using DC analysis. • Propagation delay analysis is final simulation
process in order to know the value of tPHL and tplh with output signal variation and external capacitance load.
Voltage Transfer Characteristic (VTC)
Voltage Transfer Characteristic simulation is conducted by giving DC voltage on VEE OF -5.v and VCC of 0V and output voltage of -1.3V. It is conducted just once because the system is designed to have fixed voltage shift although there is variation in design. This simulation will show VTC graph based on the expected condition. Listing program VTC is shown in VTC attachment. Fig. 4 shows the graph of VTC IC 2-to-4 Decoder ECL; based on the graph, we can obtain the value of VIL, VIH, VOL and VOH.
Fig. 4. Voltage Transfer Characteristic Decoder ECL
Simulation of Current Characteristics
input current. To obtain the value of IIH, IIL, IOH, and IOL¸ it is not enough to use only one graph but two that Is input current graph (IIH and IIL) and output current (IOH and IOL). The result of simulation is shown in Fig 5.
Fig. 5. Current Input and Current Output RC = 2 kΩ and RE = 10 kΩ
Power Dissipation
Power dissipation simulation is obtained by inserting Equ. (13), that is inserting the Equation; Pd = (IEE+IE)*VEE)on add plot during simulation. Graph resulted is function of power dissipation graph on input voltage. This simulation is conducted when the value of Rc = 2 k and Re = 10k. Fig. 6 shows graph of power dissipation in circuit using Rc= 2k and Re= 10k.
Fig. 6. Power Dissipation in Circuit using RC = 2kΩ and RE = 10kΩ
Unit Step Simulation
Unit step simulation is conducted to obtain propagation delay value. Input given in the form of pulse wave. Propagation delay value is obtained from output signal in the form of tPLH and tPHL value. Propagation delay observed is propagation delay on node 21. Unit step simulation is conducted when the value of Rc = 2k and RE = 10k because the result of manual calculation gives ideal value for all IC parameter. In simulation, capacitor variation is given that is 0,1pF, 2pF, 15pF, and 20pF. Besides that, different frequency variation that is 5 MHz, 10MHZ, 50MHz and 250 MHz is used. This simulation here is conducted only when CL is 15pF because when the value of CL can be compared with datasheet decoder
TTL 74139 and decoder CMOS 4555B. Unit step simulation CL = 15pF frequency 5MHz is shown in Fig.7.
Fig. 7. Unit step simulation CL=15pF frequency 5MHz
Data Simulation And DataSheet Comparation. Based on the result of simulation IC 2-to-4 Decoder ECL Gate to obtain design simulation data that can be compared with data of using pre determined datasheet (CMOS and TTL). Table 5 shows data of comparison between simulation design and datasheet.
Table 5
Simulation design and datasheet 4555 dan 74139
IV. CONCLUSION
Based on the result of analysis and circuit simulation of ECL, can take the following conclusion.
IC 2-to-4 Decoder ECL Gate consists of 4 gate OR 3 input, 2-to-4 Decoder ECL Gate inverter gate compiled
Parameter IC 4555B VCC = 5V
IC74LS1 39, VCC = 5V
ECL Design VEE=- 5,2V
VIH (V) 3,5 2 -0,94
VIL (V) 1,5 0,8 -1,06
VOH (V) 5 3,4 -0,81
VOL(V) 0 0,35 -1,28
NMH (V) 1,5 1,4 0,13
NML (V) 1,5 0,45 0,222
IIH (µA) 0,1 20 13
IIL (µA) 10-5
-360 1,28
IOH (µA) 3200 -400 431
IOL (µA) 1000 4000 385,3
Fa-nout 32x103 11 33
tPD (ns) 108,5 21 5,655
PD (mW) 12 34 3,68
from 26 NPN bipolar transistor and 18 resistor and 6 current source.
Design of 2-to-4 Decoder ECL using manual calculation has characteristics of symmetrical voltage shift (VTC) with high logic noise margin (NMH) and low logic noise margin (NML) in which each is 0.222V with VIL = 1.078V, VIH= 0,922V, VOL= -1,3V and VOH - -0,7 and the result of simulation of 2-to-4 Decoder ECL gives the value of VTC as follows: VIL = -1,06V, VIH = 0,94V, VOL = -1,28V, and VOH= -0,81V thus the value of NMH = 0,13V and NML = 0.222V.
Circuit of 2-to-4 Decoder ECL is designed with propagation delay value of 12,59ns on CL = 15pF using power dissipation of 3,744mW.
Simulation of 2-to-4 Decoder ECL using PSPICE on value of CL = 15pF gives better propagation delay value from calculation result of 5,655ns with power dissipation of 3,68mW.
Simulation of 2-to-4 Decoder ECL by comparing similar capacitance value (CL=15pF) gives better propagation delay and power dissipation from IC TTL 74139 and IC CMOS 4555B.
V. REFERENCES
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