Memory unit. 2 k words. n bits per word

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-1

k address lines Read

Memory unit 2 ^k words n bits per word

n data input lines

n data output lines

Write

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

Memory address Binary

0000000000 0000000001 0000000010

1111111101 1111111110 1111111111

Memory contents 10110101 01011100 10101011 10001001 00001101 01000110

10011101 00010101 00001101 00011110 11011110 00100100

. . . . . Decimal

0 1 2

1021

1022

1023

. .

. .

.

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

T 9-1

TABLE 9-1

Control Inputs to a Memory Chip

Chip select

CS Read/

Memory operation 0

1 1

0 1

None

Write to selected word Read from selected word

Write

R/W

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M. Morris Mano & Charles R. Kime

(a) Write cycle Clock

Address Memory enable Read/

Write Datainput

20 ns

T1 T2 T3 T4 T1

Address valid

Data valid 75 ns

(b) Read cycle Clock

Address Memory enable Read/

Write

Data output

20 ns

T1 T2 T3 T4 T1

Address valid

65 ns

Data valid

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-4

Select

B

RAM cell

C

C B

S

R

Q

Q

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime (a) Logic diagram Select

S R

Q Q B

RAM cell C

C B

Select

S R

Q

Q

RAM cell X Wordselect

0

Wordselect 2ⁿ 2 1

Data in

Write logic Read/

Write

Bitselect

S R

Q Q X

X

X Word

select 0

Wordselect 1

Wordselect 2ⁿ 2 1

Read/Write logic Data in

Data out Read/

Write Bit select (b) Symbol

RAM cell

RAM cell

RAM cell

Data out Read logic

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-6

Read/Write logic

Data in Data out Read/

Write Bit select

(b) Block diagram RAM cell

RAM cell

RAM cell

Data input

Chip select Read/Write

Dataoutput A3

A₂ A1

A0

2³ 2² 2¹ 2⁰

4-to-16 Decoder 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3

A₂ A1

A0

inputData Data

output

(a) Symbol Read/

Write Memory enable

16 3 1 RAM

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

Data input Read/Write

X X X

A₁ A₀ RAM cell

0

RAM cell 4

RAM cell 8

RAM cell 12

Read/Write logic

Data in Data out Read/

Write Bit select

RAM cell 1

RAM cell 5

RAM cell 9

RAM cell 13

Read/Write logic

Data in Data out Read/

Write Bit select

RAM cell 2

RAM cell 6

RAM cell 10

RAM cell 14

Read/Write logic

Data in Data out Read/

Write Bit select

RAM cell 3

RAM cell 7

RAM cell 11

RAM cell 15

Read/Write logic

Data in Data out Read/

Write Bit select

Column

decoder 2-to-4 Decoder with enable

2¹ 2⁰

0 1

Column select 2

Enable 3

Chip select

outputData Rowselect

Row decoder

A₂ A₃

X 2-to-4

Decoder

2⁰ 2¹

1

2

3 0

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-8

A₀ Chip select Data input 0

X

X

X

Column

decoder 1-to-2 Decoder with enable

2⁰ 0

Column select Data

output 0 X

Enable Data

output 1 Data input 1

Read/Write

1 RAM cell

0

RAM cell 4

RAM cell 8

RAM cell 12 Read/Write logic

Data in Data out Read/

Write Bit select

RAM cell 1

RAM cell 5

RAM cell 9

RAM cell 13 Read/Write logic

Data in Data out Read/

Write Bit select

RAM cell 2

RAM cell 6

RAM cell 10

RAM cell 14 Read/Write logic

Data in Data out Read/

Write Bit select

RAM cell 3

RAM cell 7

RAM cell 11

RAM cell 15 Read/Write logic

Data in Data out Read/

Write Bit select Rowselect

Row decoder

A₁ A2

2-to-4 Decoder

2⁰ 2¹

1

2

3 0

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

Input data Address Chip select

Output data 8

16

DATA ADRS CS

8 64K 3 8 RAM

Read/Write R/W

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-10

Input data

DATA Address

ADRS CS

Output data 8 8

64K 3 8 RAM

Read/

Write R/W

Memory enable

DATA ADRS CS

64K 3 8 RAM

DATA ADRS CS

64K 3 8 RAM

DATA ADRS CS

64K 3 8 RAM Lines Lines 0–15

17 16

2-to-4 decoder EN

0 1 2 3

16

0–65,535

65,536–131,071

131,072–196,607

196,608–262,143 R/W

R/W

R/W

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

8

8 8

16

16 DATA ADRS CS

64K 3 8 RAM

DATA ADRS CS

64K 3 8 RAM 8

16 input data lines 8

Address

Chip select

16 output data lines 16

R/W R/W

Read/Write

8

8

8

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-12

(a) (c)

Select

D C B Q

DRAM cell model

C

(f) (g)

(h) Select

B T

C DRAM cell

To Pump

(b)

(d) (e)

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

(b) Symbol

(a) Logic diagram Select

B

Select Wordselect

0

Wordselect 2^{n 2 1}

Data in

Write logic

Bitselect

Data out Read logic

D C

Q

DRAM cell model

D C

Q

DRAM cell model

C

Sense amplifier

Read/Write logic

Data in

Data out Bitselect DRAM cell

DRAM cell

DRAM cell Wordselect

0

Wordselect 1

Wordselect 2^{n 2 1}

Read/

Write

Read/

Write

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-14

DRAM bit slice

DRAM bit slice

DRAM bit slice

Input/Output Logic

Column decoder

R ow d ec od er

Column address register Column timing

Logic Row address

register Refresh counter Refresh controller

Row timing logic

•

Data in/

Data out RAS

CAS R/W OE address Row

Column address

. .

. . . .

. . .

. . .

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

(a) Write cycle

T1 T2 T3 T4 T1

Data valid 75 ns Read/

Write inputData Clock

AddressRow Column Address

RAS

CAS Address

Output enable

(b) Read cycle 20 ns

T1 T2 T3 T4 T1

Data valid 65 ns

Hi-Z Read/

Write

outputData Clock

AddressRow Column Address

RAS

CAS Address

Output enable

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

T 9-2

DRAM Types

Type Abbreviation Description

Fast Page Mode DRAM

FPM DRAM Takes advantage of the fact that, when a row is accessed, all of the row values are available to be read out. By changing the column address, data from different addresses can be read out without reapplying the row address and waiting for the delay associated with reading out the row cells to pass if the row portion of the addresses match.

Extended Data Out- put DRAM

EDO DRAM Extends the length of time that the DRAM holds the data values on its output, permitting the CPU to perform other tasks during the access since it knows the data will still be available.

Synchronous DRAM SDRAM Operates with a clock rather than being asyn- chronous. This permits a tighter interaction between memory and CPU, since the CPU knows exactly when the data will be available.

SDRAM also takes advantage of the row value availability and divides memory into distinct banks, permitting overlapped accesses.

Double Data Rate Synchronous DRAM

DDR SDRAM The same as SDRAM except that data output is provided on both the negative and the positive clock edges.

Rambus DRAM RDRAM A proprietary technology that provides very high memory access rates using a relatively narrow bus.

Error-Correcting

Code ECC May be applied to most of the DRAM types

above to correct single bit data errors and often detect double errors.

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

Memory cell array Control

logic

I/O logic

A dd re ss r eg is te r R ef re sh c ou nt er R ow a dd re ss m ux R ow a dd re ss la tc he s R ow d ec od er D at a in pu t r eg is te r D at a ou tp ut r eg is te r

Column decoder

Col address counter CLK

CS WE RAS CAS

A(11:0)

D(7:0)

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M. Morris Mano & Charles R. Kime

LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e

9-17

CLK

CS

WE

RAS

CAS

ADDRESS

DATA

ROW COL

B1 B2 B3 B0

t

t

© 2004 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime

CLK

CS

WE

DATA

ROW ROW

COL

DATA t

t

t