DESIGN AND CONSTRUCTION OF A SWITCH-MODE DC/DC CONVERTER

DESIGN AND CONSTRUCTION OF A SWITCH-MODE DC/DC CONVERTER

*E.O. Ijoga¹ and Dr. B.J. Kwaha²

1Nigerian Institute of Medical Research, 6 Edmund, Crescent Yaba, Lagos-Nigeria

2Department of Physics, University of Jos, Jos, Plateau State, Nigeria E-mail: [email protected] (^*Corresponding Author)

Abstract: This article presents the design and construction of a transformer-typed Switch- Mode Power Supply (SMPS) with multiple DC outputs. The developed circuit utilized the SG3524 control circuitry at a fixed frequency to generate pulse width train. It was desired to incorporate a transformer into the circuit so as to provide DC isolation and the desired multiple-output voltages. The circuit was built with preferred values of components with a DC input voltage of 12.00V. The voltages designed for the output terminals, Vo1, Vo2, Vo3, Vo4 and Vo5 were 15.00V, 26.00V, 30.00V, 50.00V and 80.00V respectively. The overall output power of the converter was found to be 169.7W while the total power loss in the circuit was determined to be 20.3W with an efficiency of 89.3%. Also, the DC voltage transfer function at the terminals: Vo1, Vo2, Vo3, Vo4 and Vo5 were found to be 1.08, 2.00, 2.33, 3.75 and 6.50 respectively. The developed circuit results in significant cost and space savings for multiple output power supplies. This device is useful in digital systems and electronic appliances such as TV, DVD, Cameras and Laptops which operate internally on DC voltages.

Keywords: DC-to-DC, PWM, control circuitry, driver amplifier, power switch, rectifier.

Introduction

The term “switched mode converter” is used to describe a circuit which takes DC input (unregulated) and provides single or multiple DC outputs, again of same or opposite polarity and of a lower or higher voltage (Bakshi et al, 2010). The equipment for DC conversion can be divided into four technologies (Fang and Hong, 2004):

i) AC/AC – Transformers ii) AC/DC – Rectifiers iii) DC/AC – Inverters iv) DC/DC – Converters DC/DC Converters

DC/DC Converters can be used to increase, decrease and/or reverse the voltage polarity at the output. The basic equations of an ideal DC/DC converter are given as (Erickson, 1998):

Received June 4, 2013 * Published August 2, 2013 * www.ijset.net

Pin=Pout (1) P=VI (2) V=M(D)Vg (3) Ig=M(D)I (4) where Pin and Pout - input and output powers respectively, Vg - input voltage, V - output voltage, Ig -input current, I- output current, M - conversion ratio and D is the duty cycle.

Fig. 1 DC/DC power Converter (Erickson, 1998).

Methodology

The design of a switched mode DC/DC converter with multiple outputs is a complex procedure due to the large number of parameters involved and the interdependence of these circuit parameters. However, when broken down into stages, it becomes much easier to manage. The design specifications are shown in Table 1. The choice for these specifications was primarily driving by low power consumption of digital and electronic appliances such as:

Laptops, Televisions, e.t.c. that operate internally with low DC voltages. Also, most of the commercially available appliances are designed with DC input voltages of 12V and 24V. The circuit chosen is categorised into four main stages:

i) Control circuitry

ii) Driver amplifier and power switch

iii) Power transformer design (with multiple secondary windings) iv) Rectifier and filtering capacitor

Control Circuitry

The SG3524 is a monolithic integrated circuit which incorporates all the function required for the construction of regulating SMPS (datasheetcatalog, 2010). The rationales behind this choice are:

i) It is a low cost device

ii) Has complete Pulse Width Modulation (PWM) control circuitry iii) Line and load regulation of 0.2% (datasheetcatalog, 2010) iv) Frequency of operation up to 300 kHz (datasheetcatalog, 2010)

The oscillating frequency of the PWM circuit can be determined with the equation (datasheetcatalog, 2010):

1.18

s

T T

f = R C (5) where RT and CT are Timing Resistor and Capacitor respectively, the range of practical values specified in the manufacturer’s data sheet; RT is between 1.8 and 100kΩ, while CT falls between 1nF and 0.1 F. By choosing RT to be 24 kΩ and CT to be 0.1 F,

6

1.18 492

24, 000 (0.1 10 )

fs= ₋ = Hz

× ×

The period of oscillation, T of the PWM can be obtained from (datasheetcatalog, 2010):

T = RTCT (6)

Therefore,

T = 24000 x (0.1x10^-6) = 2.4ms Driver amplifier and power switch

Digital ICs are low power devices because they can supply only small load current (Malvino and Bates, 2007). Therefore, there was need to amplify the pulse width train generated by the SG3524 IC. The C1815 NPN Epitaxial Silicon Transistor is the selected transistor for the driver amplifier stage due to its high dc current gain (hFE) linearity, high frequency oscillation, and because, its a general purpose transistor. The Common-Emitter configuration is the chosen connection for operating the circuit. This is because it has got high Current gain, βdc (50-300), very high Voltage gain (up to 1500) and Power gain (up to 10,000 or 40 dB) (Akande et al, 2007).

In addition, the Voltage Divider Bias (VDB) technique is preferred for operating the transistor. This is because it requires only a dc power supply, provides good bias stability and operating point is almost independent of βdc variation (Akande et al, 2007). The supply voltage, VCC chosen for the design is 12V dc with ±10 % tolerance. This was determined by picking an approximate dc voltage based on the analysis of circuit limitation and availability of 12V dc battery. The C1815 electrical characteristic table shown in Appendix B specified collector-emitter voltage, VCE =6.0V, minimum hFE or ßdc =130 and collector current, IC = 2.0mA. Let the load resistance be RL = 3KΩ. The dc load line for the driver stage amplifier is obtained using the equation (Akande et al, 2007):

VCE= VCC – ICRC (7)

Table 1: Specifications of the switch mode power supply (SMPS) to be designed

Parameters Values

Input voltage, Vcc

Output voltage, VO1

Output voltage, VO2

Output voltage, VO3

Output voltage, VO4

Output voltage, VO5

Output power, Po1

Output power, P_o2 Output power, Po3

Output power, Po4

Output power, Po5

Total output power, Pts

Estimated transformer efficiency, η Regulation, a

Switching frequency, fs

Diode forward drop, VF (full wave) Diode forward drop, VF (full bridge) Duty cycle, D of the integrated circuit Core Material

Core operating flux density, Bac

12.00V dc 15.00V dc 26.00V dc 30.00V dc 50.00V dc 80.00V dc 23 W 27 W 28 W 50 W 62 W 190 W 95%

6%

492Hz 1.0V 2.0V 0.45 SiFe 1.5Tesla

At short circuit, VCE = 0, then equation (7) becomes _{( )} 12

3 4

C sat

I V mA

= K =

Ω

At open circuit, IC = 0, then equation (7) becomes VCC = VCE =12V

Hence, at midpoint, 1 _{( )} 2 2

CQ C sat

I ≅ I = mA and VCEQ= 6V

where VCEQ is the collector–emitter voltage, and ICQ collector current at Q-point The dc current gain is expressed as (Akande et al, 2007):

c B

I

β = I (8)

2 15

B 130

I = mA= µA

The emitter voltage, VE can be obtained as (Malvino and Bates, 2007):

VE = 0.1 VCC (9)

VE= 0.1 x 12V = 1.2V

The emitter resistor, RE can be found using the expression (Akande et al, 2007):

E E

E

R V

= I (10)

IC IE

1.2 600

E 2 R V

= mA = Ω (1kΩ preferred).

The base voltage, VBB can be obtained from the relation given by (Malvino and Bates, 2007):

VE = VBB – Vbe (11)

VBB = 1.2V + 0.7V = 1.9V

where, the base-emitter voltage for Silicon transistor is , Vbe = 0.7V

A well deserved VDB circuit satisfies the stiff voltage source condition given by (Malvino and Bates, 2007):

R2≤ 0.01βdc RE (12)

Therefore,

R2≤ 0.01 x (130) x (1000Ω ) = 1.3kΩ (1.3kΩ preferred) The output of a VDB circuit is expressed as (Malvino and Bates, 2007):

2 1

( _{cc BB})

BB

R V V

R V

= − (13)

₁ 1.3 (12 1.9 ) 1.9

K V V

R V

Ω −

= = 6910Ω (6.8kΩ preferred)

The choice of the semiconductor technology utilized for this power switch function was influenced by factors such as low cost, peak voltage and current, frequency of operation and heat sinking. Hence, the IRF1010E power FET was chosen for this design due to its ultra low on-resistance (RDS(ON)) of about 12m . Other benefits includes: fast switching and ruggedized device, low thermal resistance, provides high power capability, and good switching capability (SMPSRM, 2007). The selected switching topology for the design is

called "push-pull" Converter, because the transformer has a double primary (centre-tapped).

The centre tap is connected to the 12V DC battery. The two ends of the primary are connected to a pair of paralleled IRF1010 E MOSFETs. Each ties the MOSFET to ground in each conduction cycle.

Power transformer stage

The design specifications are shown in Table 1.The overall output power, Pts for the DC converter given as 190W. The voltage across the primary winding of a centre tap transformer is twice the input dc voltage (bcae1, 2011). Thus, Vp = 24V ac and efficiency, η = 0.95. The current through the primary winding, IP is given by (McLyman, 2004):

CS p

p

I P ηV

= (14)

A 190

0.95 24 8.3

p

I = W = A

×

And the transformer input power; P_in is calculated as (McLyman, 2004):

Pin=IPVP (15)

Pin = 8.3A x 24 =199.2 W

The apparent power, Pt is calculated as (McLyman, 2004):

Pt = Pin + Pts (16)

Pt= 199.2 W + 190 W = 389. 2 W

The transformer operating frequency, fT is determined from the switching frequency, fS by (datasheetcatalog, 2010):

1

T 2

f = fs (17)

fT =1

2 x 492 =246 Hz

The value of fT and the design parameters in Table 1 can be used to compute the windings.

The number of turns, Np at the primary winding can be computed by (Gottlieb, 1998):

108 p 4

S

N E

= fB A (18)

where E is the voltage, f is the transformer frequency, Bs is the flux density and A is the core area.

24 108

4 246 15000 3.448 47.2

p

N x

x x x

= = (48 turns preferred value)

The current density, j is given by (McLyman, 2004):

108 C

S u T C C

j P

KB K f A W

= (19)

where winding fill factor, Ku = 0.25 (for multiple output transformer (Erickson, 1998)), Bs = 15000 Gauss shown in Appendix F. Using the EI-750 core parameters in appendix D for core area, AC and window area, WC,

389.2 108

4 0.25 15000 246 3.448 2.723 j x

x x x x x

= = 1123 Acm^-2 (1.123 x10⁷Am^-2)

The primary wire area Awp is given by (McLyman, 2004):

w

A I

= j (20)

where I is current. All windings operate at the same current density, j. Therefore, 8.3 ₇

1.123 10 Awp

= x = 7.39 x 10^-7m^-2 (0.00739cm²)

Appendix G: 0.00739cm² has the approximate gauge AWG #18 with resistance per unit length,

cm µΩ

of the wire specified as 209 Ω (2.09 x 10^-4Ω)

The Primary resistance, R_p of a solid copper is given as (McLyman, 2004):

Rp= MLT (NP) of AWG cm

µΩ

(21) Appendix D: The, Mean Length per turn, MLT for EI-750 core is specified as 11.2cm.

Rp =11.2 x 48 x (2.09 x 10^-4) = 0.11 Ω The primary copper loss, Pp is defined as (McLyman, 2004):

Pp=Ip

2Rp (22)

where Ip is the primary current

Pp = 8.3² x 0.11 = 7.6W

The secondary turn, Ns for multiple windings is expressed as (McLyman, 2004):

1 100

p si si

p

N V a

N = V + (23)

where: Vsi=Voi + VF (24)

Nsi is secondary turns, Vsi the secondary voltage, Voi the output voltage (i= 1, 2,...N), Np the primary turn, Vp the primary voltage, a- the voltage regulation, and VF is the diode forward voltage drop.

The 1st secondary winding: Vs1=15 + 1.0= 16V

1

48 16 6

24 1 100

s

N = x + = 33.9 (34 turns preferred)

The 2nd secondary winding: Vs2=26 + 1.0= 27V

₂ 48 27 6

24 1 100

s

N = x + = 57.2 (58 turns preferred)

The 3rd secondary winding: Vs3=30 + 1.0= 31V

₃ 48 31 6

24 1 100

s

N = x + = 65.7 (66 turns preferred)

The 4th secondary winding: Vs4=50 + 2.0= 52V ₄ 48 52 6

24 1 100

s

N = x + = 110.2 (112 turns preferred)

The 5th secondary winding: Vs5=80+ 2.0=82V

5

48 82 6

24 1 100

s

N = x + =173.8 (172 turns preferred)

The secondary power, Ps(i) is given by (McLyman, 2004):

Ps(i) = Io(i) (Vo(i) + Vd) (25)

( ) si s i

si d

I P

V V

= +

where, Io(i) is output current (i=1,2,3,..) Vd is the diode forward voltage drop.

( )

23

15 1

s i

I W

V V

= + = 1.40A

Using equation (20) with parameters in Table 1, the wire gauge for 1st secondary winding:

7

1.40 1.123 10 Awsl =

× = 1.25 x 10^-7m² (0.00125cm²)

Appendix G: 0.00125cm² has the approximate gauge AWG #26 with resistance per unit length,

cm µΩ

of the wire specified as 1339 Ω (1.339 x 10^-3Ω )

The secondary resistance, Rs of a solid copper is given as (McLyman, 2004):

Rs= MLT (Ns) ofAWG cm

µΩ

(26)

For the 1st secondary winding: Rs(1)= 11.2 x 34 x (1.339 x 10^-3) = 0.51Ω (Appendix D: MLT for EI-750 core is specified as 11.2cm).

The secondary copper loss, PS (oi) is defined as (McLyman, 1993):

Ps (oi) = I(oi) 2

Rsi (27) where I(0i) and Rsi are the secondary currents and resistances of the wire. (i=1, 2, 3...N)

1st secondary copper loss: Ps1 = (1.40)² x0.51 = 1.04W Using equation (20), the secondary current for the 2nd winding:

(2)

27

16 1

s

I W

V V

= + = 1.0A

Bare wire area: 2nd secondary winding: ₂ 1.0 ₇ 1.123 10

ws

A A

= x

= 8.9 0x 10^-8m² (0.000890 cm²) Appendix G: 0.000890 cm² has the approximate gauge AWG #28 and

cm µΩ

is 2129 Ω (2.129 x 10^-3Ω )

The resistance for the 2nd secondary winding: Rs2= 11.2 x 58 x (2.129 x 10^-3) = 1.38Ω The Copper loss for the 2nd secondary winding: Ps2 = (1.0)² x 1.38 = 1.38W

The secondary current for the 3rd winding: ₍₃₎ 28

30 1

s

I W

V V

= + = 0.90A

Bare wire area: 3rd secondary winding: ₃ 0.90 ₇ 1.123 10 Aws

= x = 8.01 x 10⁸m² (0.000801cm²) 0.000801cm² AWG #28 and the

cm

Ω of AWG #28 = 2129 Ω (2.129 x 10^-3Ω )

Resistance for the 3rd secondary winding: Rs3= 11.2 x 66 x (2.129 x 10^-3) = 1.57Ω Copper loss for 3rd secondary winding: Ps3 = (0.90)² x1.57 = 1.27W.

The current for the 4th secondary winding: ₍₄₎ 50

50 2

s

I W

V V

= + = 0.96A

Bare wire area: 4th secondary winding, ₄ 0.96 ₇ 1.123 10 Aws

= x = 8.56 x 10⁸m² (0.00086 cm²) Appendix G: 0.00086 cm² AWG #28 and the

cm

Ω of AWG #28

= 2129 Ω (2.129 x 10^-3Ω ) Resistance: 4th secondary winding, Rs4= 11.2 x 112 x (2.129 x 10^-3) = 2.67Ω Copper loss: 4th winding, Ps4 = (0.96)² x 2.67 = 2.46 W

The current for the 5th secondary winding: ₍₅₎ 62

80 2

s

I W

V V

= + = 0.76 A

Bare wire area: 5th secondary winding, ₅ 0.76 ₇ 1.123 10 Aws

= x = 6.73 x 10⁸m²(0.000673cm²)

Appendix G: 0.000673cm AWG #29. And cm

Ω of 2685 Ω (2.685 x 10^-3Ω )

Resistance: 5th secondary winding, Rs5 = 11.2 x 188 x (2.685 x 10^-3) = 5.65Ω The copper loss for the 5th winding: Ps5 = (0.76)² x5.17 = 3.0W

The total secondary copper loss (McLyman, 2004):

PSL = Ps01 + Ps02 +Ps03 + Ps04 + Ps05 (28) PsL= 1.04W + 1.38W +1.27W + 2.46W + 3.0 = 9.15W

The total copper loss is given by (McLyman, 1993):

Pcu= Pp + PsL (29)

Pcu = 7.6 + 9.2 = 16.8W

Appendix E: Core loss equation factors for EI lamination of 14.00 mils thickness with values of the constants: k, m and n.

Manufacturers present core loss in the form of an equation such as (McLyman, 2004):

W/Kg = K f^m Bⁿ (30)

Pfe = (W/Kg) (Wtfe) (31)

where K, m, n are core constants, f is transformer frequency, B is core magnetic flux density, Pfe is core lose, W/Kg is the Watt/Kilogram and Wtfe is the core weight.

W/Kg = 0.0005570 x (246 Hz) ^1.68 x (1.5 T) ^1.86 = 12.3 W/Kg (Appendix D: The weight of the core is 108.8g (0.109Kg)).

Pfe = 12.3 x 0.109 = 1.3W

The total power loss, P can be expressed as (McLyman, 2004):

P = Pcu + Pfe (32)

0 0

P P P

Σ= η − (33) where Pcu the copper loss, Pfe the core or iron lose, Po the output power and η the efficiency

P = 16.8 + 1.3 = 18.1W

Therefore, the total loss in the designed circuit is calculated as 18.1W Rectifier circuit and filtering capacitor

There are four choices of rectifier technology: the standard recovery diodes, fast recovery diodes, the Ultra-fast recovery diode and Schottky rectifier (SMPSRM, 2007). The two rectifier technologies utilized in this design are the full wave rectification using MUR120 ultra fast rectifier. This was chosen due to its fast turn off and high reverse voltage capability of up to 1000V (SMPSRM, 2007). The other rectifier technology utilized is the GBPC1508W

bridge rectifier; this was chosen due to its suitability for high voltage application. The cut off Frequency, fc of a filter is given by (Malvino and Bates, 2007):

1

c 2

f ⁼ πRC (34)

where C is capacitance and R resistance.

1

2 3.143 492 4400

R⁼ x x x µF ^{= 0.07}Ω (80 Ω preferred for convenience) Implementation of the switch-mode dc/dc converter:

The proposed switch-mode DC/DC boost converter has been developed and tested. The electrical circuitry of the system is depicted in Fig. 2.The circuit was powered by a 190W DC source. Output currents as well as voltages were measured using digital multi-meter and different values of dc lamp (4.1Ω , 5.5 Ω , 8.2 Ω , 9.6 Ω , 12.3 Ω , 13.7 Ω and 16.4 Ω ) as load resistors.

The power can be expressed by (Akande et al, 2007):

V2

P= R (35)

where V is the output voltage and R is the resistance (of the dc bulb)

Using equation (35) with the measurements obtained in Table 4, the output powers from the terminals of the developed circuit in Table 5 were computed. To determine the overall output power of the DC converter, maximum output powers obtained from each terminal were collated and summed using the expression (McLyman, 2004):

Po (Total) = Po1(max) + Po2(max) + Po3(max) + Po4(max) + Po5(max) (36) Po (Total) = 19.0 + 25.0 + 20.0 + 46.8 + 58.1 = 169.7W

The efficiency of a DC converter can be expressed by (Malvino and Bates, 2007):

ε = x 100% (37)

where ε is efficiency of the dc converter, Po the output power and Pin the input . With an input power of 190W and total output power of 169.7W, the efficiency of the DC converter can be calculated:

ε = x 100% = 89. 3%

Replacing with in equation (33), the Total loss in the developed circuit:

0 0 L

P P P

= ε − (38) where –the efficiency of the DC converter

PL = – 169.7 = 20.3W

DC voltage transfer function MV(DC) is given by (Rashid, 2007):

MV(DC) = (39)

whereVo is the output dc voltage and Vin is the input dc voltage The 1st output terminal: MV1(DC) = = 1.08

The 2nd output terminal: MV2(DC) = = 2.00 The 3rd output terminal: MV3(DC) = = 2.33 The 4th output terminal: MV4(DC) = = 3.75 The 5th output terminal: MV5(DC) = = 6.50

(-) IN

(+) IN

(+) SENSE Osc. Out

(-) SENSE

RT

CT

GNDCOMP SHTDOWN EA CA CB EB VIN VREF

50V/4400 Fµ 28.0V DC D1

D2

45.0V DC 50V/4400 Fµ

78.0V DC 50V/4400µF Bridge Rectifier

Bridge Rectifier

SG3524

116

15

14

13

12

11

10

9 234567

8 0.1Fµ 24K 10K

100K

15K 350K

0.33Fµ

4.7K 2K

4.0V

C1815

1K 1K

20K

C1815 4.0V

3K 3K

2.0mA 2.0mA

G IRF1010E

IRF1010E G

+12V

IRF1010E IRF1010E

G S G

D

+12V DC FUSE

35A

-12V DC

13.0V DC D1

D2

16V/2200 Fµ

24.0V DC D1

D2

16V/2200 Fµ

6.8K

1.3K 1.3K 6.8K

Fig. 2 Switch-mode DC/DC boost converter (transformer-type)

Results

The developed circuit was powered by a 12V DC supply (190W source). Table 2 shows experimental measurements of output currents, Io as well as load voltages, Vload taken at the various terminals using three different load resistances (4.1 , 5.5 and 8.2 ). Figs.3, 4 and 5 are graphical interpretation of Table 2. The readings in Table 3 compares the voltages measured across the various output terminals of the developed circuit when there were no loads connected and that of the designed values (Vexp). Also, Table 3 shows the voltage transfer function (AV) and percentage errors (P.E) computed from the measurements. Table 4 is the summary of the load voltages measured at the various output terminals of the DC/DC converter when the load resistances were varied; the dc load resistances connected ranged from 4.1Ω to 16.4Ω. Table 5 is the summary of output powers at the various terminals of the power converter with different load resistances. These values were computed using the measurements obtained from the various output terminals of the dc converter. Fig 6 shows the graph of load Voltage, (Vload) ploted against Load resistance (R). The load voltages were obained from the various output terminals of the power converter. Fig 7 shows the graph of the output power (Po) obtained from the various terminals plotted against the Loads resistances (R).

Table 2: Measurements at various output terminals using different load Resistance dc output terminal 4.1Ω (dc lamp) 5.5Ω (dc lamp) 8.2 Ω (dc Lamp)

Vload (V) Io(A) Vload (V) Io(A) Vload (V) Io(A) Initial reading

#o.1

#o.2

#o.3

#o.4

#o.5

0.00 7.30 7.46 8.68 11.11 13.00

0.00 1.79 1.82 2.12 2.71 3.16

0.00 8.86 9.30 10.22 13.37 16.50

0.00 1.61 1.69 1.86 2.43 3.00

0.00 11.48 12.16 12.30 19.60 20.50

0.00 1.40 1.48 1.50 2.39 2.50

Fig. 3: Graph of Vload versus Io for a load resistance of 4.1Ω (dc lamp)

Fig. 4: Graph of V_load versus Io for a load resistance of 5.5Ω (dc lamp)

Fig. 5: Graph of Vload versus Io for a load resistance of 8.2Ω (dc lamp)

Table 3: Comparison of measured and designed values at various output terminals

dc Output terminal Vexp (V) V(no-load) (V) AV = P.E= x 100%

#o.1 #o.2 #o.3 #o.4 #o.5

15.00 26.00 30.00 50.00 80.00

13.00 24.00 28.00 45.00 78.00

1.08 2.00 2.33 3.75 6.50

15. 3 % 8.3 % 7.1 % 11.1 % 2.6 %

Table 4: Summary of load voltages at various output terminals with load resistance R ( ) Vload1(V)

(0utput,#o.1)

Vload2 (V) (0utput,#o.2)

Vload3(V) (0utput,#o.3)

Vload4(V) (0utput,#o.4)

Vload5(V) (0utput,#o.5) 4.1

5.5 8.2 9.6 12.3 13.7 16.4

8.68 10.22 12.16 13.43 15.12 16.07 17.57

7.30 9.30 11.48 13.15 15.13 18.50 19.68

7.46 8.89 12.30 14.11 14.64 15.62 16.89

11.11 13.37 19.60 18.24 20.42 22.33 26.24

13.00 16.50 20.50 22.85 26.32 28.22 30.83

Fig 6: Load voltage (Vload) , versus load resistance (R)

Table 5: Summary of output power at various terminals with load resistances R (Ω)

(dc Lamps)

Po1(W) (output #o.1)

Po2 (W) (0utput,#o.2)

Po3 (W) (output,#o.3)

Po4 (W) (output,#o.4)

Po5 (W) (output#o.5) 4.1

5.5 8.2 9.6 12.3 13.7 16.4

18.4 19.0 18.0 18.8 18.6 18.6 18.8

13.0 15.7 16.1 18.0 18.6 25.0 23.6

13.6 14.3 18.5 20.8 17.4 17.8 17.4

30.1 32.5 46.8 34.7 33.9 36.4 42.0

40.9 49.5 51.3 54.4 56.3 58.1 58.0

Fig. 7: Output power (Po) versus Load resistance (R)

Discussion

Figs 3 through 5 are characteristic linear plots for Ohmic conductor. They show voltage- current proportionality; voltages increase with increase in currents. The gradients are positive. In the absence of an applied potential difference, there is no current flow. Thus, the plots pass through the origin. The slopes obtained from each of the graphs corresponded to the values of the load resistances used for the experiment. These show that the developed circuit obeys ohm’s principle. Hence, validates the circuit. Table 3 shows a strong correlation between theory and experiment. It compares the no-load voltages measured across the various output terminals of the developed circuit and that of the designed values (Vexp). The voltages from the developed circuit have slight deviations from the designed values. These were determined using the percentage error (P.E) method as shown in Table 3. The deviations ranged from 15.3% to 2.6%. Though, it was envisaged that there may be slight deviations. These were due to the non-ideal properties of the component utilized and losses.

The losses in the designed circuit were found to be 18.1W while the Loss from the developed circuit was 20.3W. Electromagnetic Interference was a major issue. However, passive filters were employed to attenuate interferences radiated from the power devices. Table 5 shows that, as the load resistances are being increased, the output power also increase in direct

proportion. Maximum output power was computed from the terminals. These powers were summed so as to obtain the overall output power of the Converter. This was found to be 169.7W. The measurements shown in Table 4 revealed that, for each output terminal of the dc Converter, the load resistances increase in direct proportion with the load voltage. Fig 6 shows that output terminal five has the maximum load voltage of 30.83V at 16.4Ω while output terminal three has the least voltage of 7.46V at 4.1Ω. In addition, the resistance of the dc circuit increase as voltage increase. From Fig. 5, it can also be seen that the plot for terminal four has a shape increase and a drastic drop. This was caused by the effect of stray and parasitic capacitances; these were unavoidable as they were the unwanted capacitance that exists between the parts of the circuit due to component proximity to each other. Also, all actual circuit elements such as: inductors, diodes and transistors have internal capacitance, which can cause their behaviour to depart from that of “ideal” circuit elements. Closely spaced conductors, such as wires or Printed Circuit Board (PCB) traces were also a factor.

leakages to chassis from circuit as well as temperature effect on voltage transformation were also responsible for the sharp increase nd drop. Fig 6 shows that output terminal five has the maximum power of 58.1W while output terminal two has the least output power of 13.0W.

In the design of this circuit, it was assumed that the circuit will be most utilized at its maximum power output. Thus, the need for several readings at the various output terminals.

The maximum output powers obtained at the various terminals were summed so as to compute the overall output power of the circuit. This was found to be 169.7W. Having determined the total output power of the developed circuit, the efficiency of the DC/DC converter was found to be 89.3% with a power loss of 20.3W. The power loss and efficiency calculation of the converter system were utilized for the overall performance evaluation of the converter. It can be observed that the practical results obtained from the experiments are reasonable compared to theoretical results obtained from the design if the losses in the system are taken into account. For safe use of DC voltage without specific insulating precautions, the voltage must not exceed 50 V as reported by Peter (2005). Therefore, the DC voltages obtained from terminal one through terminal four as presented in Table 3 are within the acceptable limit, and can be tolerated in real life. However, adequate precaution should be taken in handling the DC voltage from terminal five for safety reason. The stabilized voltages obtained from the developed circuit can be used where high voltage fluctuations are present.

Conclusion

An analysis, methodical design process and practical implementation of a transformer-type isolated DC/DC converter were pursued in this study. The design was supported by experimental verification yielding a satisfactory result. The developed circuit takes an input voltage of 12.00V DC and delivers five different values of DC voltages across the various output terminals. There are two significant achievements in the developed circuit. Firstly, the magnitudes of the output voltages have been boosted. These amplification ranged from 1.05 to 6.50 as designed. Secondly, multiple output DC voltages have been achieved using multiple secondary transformer windings. It was necessary to find a mitigation technique to overcome the challenge of EMI so as to avoid failures and damages in electronic devices.

Hence, passive filters were employed to attenuate the emission from power devices.

Electromagnetic shielding was also employed to reduce the effect of EMI noise and dv/dt, ceramic capacitors were used in place of other discrete components for high reliability, and long operating lifetimes. The SG3524 control circuitry utilized in the circuit performs several functions and contributed in reducing complexity in the dc/dc converter circuit. It has been shown by this study that it is possible to combine DC/DC converter with a boost-derived regulator to produce regulated multiple output converter. The modified digital PWM technique allows for more efficient utilisation of the transformer capacity. Isolation transformer design was done to minimize leakage effects. This study would contribute immensely in reducing the energy consumption in domestic appliances by converting AC voltages to DC voltages for devices that operate internally on low DC voltages. This also reduces losses; by using a low voltage DC distribution network in the residence, AC to DC conversions losses can be minimised and the use of comparatively less efficient adapters can be discarded. Hence, there will be no power factor issues. In addition, DC distribution within the home can probably reduce the number of appliance cords drastically and also give relief from keeping track of which adapter belongs to which device. Also, a DC distribution network in the residence will facilitate to reduce to reduce electricity consumption and harmful emissions, also the line losses due to the absence of reactive power, less current will be needed to transfer the same amount of power. Since losses for distribution of electricity are mainly dependent on the current magnitude and the cable length. Finally, it has been demonstrated that loads can be connected directly to the various output terminals of the DC supply without any conversion.

References

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[18] http://www.datasheetcatalog.org/datasheet/SGSThomsonMicroelectronics/mXyzsrqu.pdf [19] http://www.bcae1.com/trnsfrmr.htm @ 11:55 amm Oct. 27, 2011

Appendix A: Electrical characteristics of SG3524 (datasheetcatalog, 2010)

Appendix B: C1815 electrical characteristics (datasheetcatalog, 2010)

Appendix C: Electrical Characteristic of IRF 1010 E MOSFET (datasheetcatalog, 2010)

Appendix D: Core design data for EI lamination (McLyman, 2004)

Appendix E: Core loss equation factor for EI lamination (McLyman, 2004)

Appendix F: Magnetic wire table (Pressman et al, 2007)

Appendix G: Comparative Information on Rectifiers (SMPSRM, 2007)