Using the HT46R46 I/O Ports to Implement Half-Duplex SPI Communication
D/N: HA0150E
Introduction
This application explains how to use two I/O lines on the HT46R46 to implement half-duplex SPI communication.
SPI Communication Protocol
The Master and Slave use their I/O ports to communicate with each other using a simulated SPI protocol, the following is the method used:
DIR: SPI communication direction control bit. Setup using the switch which is connected to PA.7. When the switch is set to zero then the master is reading and the slave is writing.
When the switch is set high then the master is writing and the slave is reading.
Fig. 1
Master control clock signal SCK, device select CS (consult the above figure /SS condition) and SPI communication baud rate.
In this application, each time the key (connected to PD.) is pressed, the master and slave will conduct communication. The data received will be displayed on the PB port display.
Hardware Block Diagram
Master (HOST) Block Diagram
Fig. 2
Slave Hardware Block Diagram
Hardware Circuit Diagram
Software Flowchart
Master (HOST) Program Flowchart
Start
MCU Initialise RAM and I/O Port
Master Setup CS, CLK, SDO I/O Port as Output, SDI I/O Port as Inputs
Y KEY is Pressed N
Master to SPI Communication Routine SPI_HOST_TO_SLAVE Set DIR bit to Control SPI
to READ or WRITE
Slave Program Flowchart
Fig. 6
SPI_HOST_TO_SLAVE Subroutine Flowchart
SPI_SLAVE_TO_HOST Subroutine
Program Flow Description
• After Power-on, the master and the slave will conduct their respective initialization procedures. The SPI communication will be initiated by the master. When the slave responds to the master the I/O port will be used to simulate SPI protocol half-duplex communication.
• In this application each time the key connected to PD.0 is pressed, the master will conduct SPI communication. This is implemented by the master using the device select signal (CS), and the SPI clock signal (CLK), the read/write control bit (SDIR).
When the slave receives CS, CLK and SDIR signals it will respond to the master. Each time an SPI communication has ended, the master and the slave will determine if the data is to be displayed on the PB port display. Then the program will return and continue with the next SPI communication.
• In the SPI serial communication program, the master and the slave both input data on SDI on the rising edge of SCK. Data is outputted on the SDO line on the falling edge of SCK. Each SCK clock period transmits 1-bit of data. This is repeated 8 times to complete an 8-bit data serial transmission. During this time, according to the condition of SDIR, the direction of the communication is setup. If SDIR = 1 then the data communication is from master to slave or if SDIR is = 0 the data communication is from slave to master.
• This application program I/O timing is shown as follows in Fig. 9:
Program Variables and Communication Setup Description
• CS: SPI serial communication device select signal (consult Fig. 9 /SS condition). The master and slave CS are connected. The master controls the CS signal, and the slave checks its condition. The CS line is active when low.
• SCK: SPI communication clock signal (consult Fig. 9 SCK condition). The master and the slave SCK are connected. The master controls the SCK line and controls the serial transmission speed. The slave checks the condition of the SCK signal and responds to the master with SPI communication.
• SDO: SPI serial communication output signal (consult Fig. 9 MOSI condition). The master and slave output data on SDO on the falling edge of SCK.
• SDI：SPI serial communication input signal (consult Fig. 9 MISO condition). The master and the slave SCK receive data on SDI on the high going edge of SCK.
• SDIR: Setup the SPI serial communication data transfer direction. When SDIR is zero, the master will read from the slave and the communication direction is from slave to master. When SDIR is high, the master writes to the slave and the data communication direction is from master to slave.
• C_BaudRate: The master will setup the SPI serial communication data transmission rate. In this application fSYS is 4MHz and the TIMER clock source is fSYS/4=1MHz. If it is required to implement a 4800 transmission rate, then 1/4800 = 208us is required to transmit 1-bit of data. Therefore the SCK clock period is also 208us. Then setup the TIMER to have a period of 104us after which the SCK bit can change giving a SCK clock period of 208us. Therefore when C_BaudRate = 104us the transmit rate is 4800.
In the same way when C_BaudRate = 52, the SCK clock period is 104us and the transmit rate is 9600. Other transmit rates can be similarly calculated.
• The above constants are defined in the user_setting.inc file. In the file, SDIR and C_BaudRate are setup in the master. When implementing SPI serial communication, the master SDO signal and the slave SDI signal are connected. The master SDI signal and the slave SDO line are connected.
• WRITE_RAM: SPI serial communication output data Buffer
• READ_RAM: SPI serial communication input data Buffer
• CMD_RAM: SPI serial communication CMD data Buffer
