“Wafer Level Testing Challenges for Flip Chip and
Wafer Level Packages”
by
Lim Kok Hwa and Andy Chee
STATS ChipPAC Ltd.
5 Yishun Street 23, Singapore 768442
kokhwa.lim@statschippac.com; kenghwee.chee@statschippac.com
Originally published in the International Wafer Level Packaging
Conference Proceedings,” San Jose, California, November 5 – 8, 2012.
Copyright © 2012. The material is posted here by permission of the SMTA
- The Surface Mount Technology Association.
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copyright laws protecting it.
WAFER LEVEL TESTING CHALLENGE FOR FLIP CHIP AND WAFER
LEVEL PACKAGES
Lim Kok Hwa and Andy Chee
STATS ChipPAC Ltd.
5 Yishun Street 23, Singapore 768442
kokhwa.lim@statschippac.com; kenghwee.chee@statschippac.com
ABSTRACT
Wafer level packages continue to see strong growth driven by mobile phones, portable players, digital cameras and tablets. All these devices use small form factor and low profile packages such as a wafer level chip scale package (WLCSP) as it fits the requirements. Conventional flip chip die with solder bump is growing due to the increasing number of new design packages converting from wire bond and new flip chip interconnects such as copper pillar and micro bump are growing as a result of strong demand in 3D stacked ICs. Both WLCSP and flip chip need to be electrically tested in wafer format at some point in the assembly process, either as a Known Good Die (KGD) in 3D ICs or an end product that goes into the PCB of an electronic gadget.
Wafer sort or wafer level testing was once considered as a method to save packaging cost as this process sorts out bad die before it is assembled into a package. However, today wafer sort or wafer level testing is an important process for yield enhancement of flip chip packages and a final test requirement for WLCSPs.
The challenge of wafer level testing has grown significantly due to the increasing complexity of the die or packages. The current technology started to see limitations in hardware and tools. This paper investigates the challenges facing wafer level testing as well as examining the solutions available to overcome these challenges, identifying the gaps and additional innovation needed to overcome these challenges.
INTRODUCTION
For many years, wafer level testing or wafer sort was employed for two reasons. Firstly, it is to sort out bad dies to prevent them from being assembled into the final package and this would save the cost of packaging. Secondly, the purpose of wafer level testing is to provide yield feedback to the wafer fab in time to control the wafer fabrication process [1]. These two purposes are still valid today. However, as packaging technology advances, wafer level packages such as flip chip and WLCSP changes the wafer test requirements not only for yield enhancement of the final package, but also full coverage of testing as it takes the final form of the end package. These bumped types of wafers need to be contacting at solder bumps instead of pads during test. It seems relatively easy compared to contacting pads as bumps are larger in size and wider in pitch; however, the real
situation is more complex as the challenges of testing these bumped chips are different.
Wafer-Level Packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level and it takes many forms. There are WLCSP, flip chip dies built into flip chip or 3D packages and all these dies or packages need wafer level testing.
PACKAGES REQUIRE WAFER LEVEL TESTING The traditional functions of a semiconductor device package are to provide environmental protection for the die built in it. However, this need of protection becomes less important with the short expected life of the IC and advancement in material used in building the wafer level package. Wafer Level Chip Scale Packaging (WLCSP), as its name “Chip-scale package” implies, is a wafer level packaged die with grid array bumps at pitches of 0.4mm and above. This bumped integrated circuits package goes directly onto printed circuit boards of end electronic products such as mobile phones which are one of the fastest growing package types in the semiconductor industry. Fabrication and testing of WLCSPs are done at the wafer level. As the manufacturing cost drops with increased wafer size and reduced die size, cost competitiveness becomes a main motivation to replace traditional QFN packages in mobile devices with WLCSPs. WLCSP is not new; it started with small size and low I/O a decade ago till today with high pin counts and larger package size as shown in below figure 1.
In the extension of WLCSP, fan-out wafer-level technology overcomes interconnect density limitations on PCBs and
reduces the need for bump interconnects [2]. One typical example of fan-out technology is embedded wafer level BGA (eWLB) show in below figure 2.
Flip chip and wire bond are the two standard processes to connect the die to a substrate. The flip chip device continues to see strong growth with an increasing number of new designs converting from wire bond. The reasons for the conversion can be attributed to the advantages of its thermal and electrical properties, lower cost and ability to support high I/O count with a smaller package relative to the die size; as shown in figure 3 below. The connection area required for flip chip is much smaller than what is required for wire bonding because all the I/Os from the chip are connected through the bottom. [3]
Flip chip packaging uses area array solder bump configurations and its typical bump pitch is 150µm. Figure 4 shows examples of final flip chip packages in the form of fcBGA and fcFBGA that are in high volume manufacturing now.
As the need for increased I/O signal connections grow; the bump pitch has to decrease. In order to maintain standoff height with decreasing pitch, a solid column type bump has to be employed and this is copper column bump. Flip chip with copper column bump is expected to see greater demand as the need the fine pitch solutions increase. There are two approaches for copper column bumps as shown in figure 5 below: one with a solder cap and the other without. Copper column bump pitch can be as low as 40µm and this makes testing them very difficult.
3D packaging is driven by wireless and consumer products that require package level functional integration in a small footprint, low profile and lower in cost. 3D packages come in many different forms. For some, flip chip dies are used in the package and certainly these dies must be known good die (KGD) to ensure the end package quality. Figure 6 shows an example of a 3D package with flip chip die. Figure 2: Embedded Wafer Level BGA (eWLB)
Figure 3: Flip chip connection area compared to wire bond connection area
Figure 4: Flip Chip packages
Figure 5: Copper column bump. (Top photo shows solder cap version)
NEW CHALLENGES IN WAFER LEVEL TESTING The paradigm for wafer level test is changing rapidly. The original intent of final yield enhancement and feedback to the wafer fab for process control for performance wafer sort has expanded. With new package or die types needed to test in wafer level, different challenges have surfaced.
Comparing package handling in a test handler where wafers are effectively all the same, it would appear that the handling of wafers would be an easier task. The actual handling, though, is probably more difficult since wafers are extremely fragile and damaging even one wafer is unacceptable due to the large number of valuable dies lost. The handling equipment or prober needs to be extremely precise and intelligent to handle these fragile wafers.
Wafer level test handling equipment or probers face significant technical challenges in different markets or wafer types. One of the common issues is the need for high parallelism test. For high parallelism requirements, the prober needs to have accurate alignment capability and very high force test chuck for presenting the wafer to probe card for contacting. There is even a need for full wafer contact of a 300mm wafer with thousands of solder bumps and it becomes a challenge for providing increasing insertion force without damaging the fragile wafer.
In wafer handling, different types of wafers need to be processed in the same prober. We see thin wafers at high warpage that need to be tested. These wafers go through back grinding to the required end thickness before wafer testing on the prober. Typically a standard prober can handle up to 350µm thickness. For wafers thinner than 350µm, there is an increased tendency to warp badly and make handling in a prober very difficult. In this case, a special tool or kit will be needed to handle this type of thin wafer. However, any wafer thickness of less than 150µm is still a challenge for the prober to handle.
With the new type of wafers such as eWLB gaining popularity, the prober now needs to handle wafers with different surfaces or materials. These eWLB wafers are different from normal silicon wafers as the backside of the wafers are a mold compound and they tend to have a higher
warpage level with a similar thickness as silicon wafer as shown in figure 7
The above mentioned challenges need to be overcome with good handling equipment. Probers now need to have capability and/or options as listed below:
· High force chuck for high parallelism
· Wafer handling arm and chuck to handle thin and warped wafers
· Chuck that can handle different material of wafer such as eWLB wafers with molded material at backside of the wafer
· Intelligence optical alignment for fine pitch bumps · High speed wafer changing and indexing
As the requirements get more stringent, probers will need to continue improving to meet all the new requirements. The overall end user would need a flexible and cost effective prober to handle different requirements and situations.
PROBE CONTACT CHALLENGES
As the need for increased I/O signal connections grow, the bump pitch has to decrease and maintain a greater standoff height. A solid column type of bump is created either in solid copper column or with an added solder cap.
Fine pitch is always a challenge for probe card geometry and precision. A prober that handles fine pitch wafers needs the precision to achieve an accurate probing. Currently, flip chip die with 150µm pitch is in mass production without Figure 6: Example of 3D package
issue. Typically this type of bumped wafer uses a vertical probe card with buckling beam type of contact pins. As the pitch of copper column bump scales below 100µm, this type of vertical probe card design cannot scale down to the required pitch. Advanced probe cards with MEMS technology will be needed, however by design, the cost of MEMS probe cards are very expensive which eventually drives up the overall cost of test. The MEMS design probe pins are also not easily replaceable and this also drives up the cost of maintenance on the probe card and replacement after end of life of these pins. Some of the copper column bumps are even reaching as low as 40µm in pitch which already hits the limit of probe card technology even with MEMS technology.
For copper column bump type of wafers, there are different types of bumps as shown in below figure 8. The materials for these contacts are different. For copper column with solder cap, the contact is on the solder. The requirement is similar to normal solder bump. However, as the thickness of solder cap is low, care must be taken into consideration on the probe depth which must not be too deep. For copper column without solder cap, the challenges are different as the contact is on copper and it is harder to penetrate and thus a sharper probe tip and high force will be needed for good contact [4].
Probe card companies are investigating various approaches to deal with the challenges mentioned above. Probe card companies with traditional buckling beam notice that this technology can never scale to meet the challenges of fine pitch, especially with pitches below 50µm. Several new approaches using MEMS technology can meet the requirement for fine pitch, but until today, MEMS probe
cards are still expensive in both initial fabrication cost as well as running cost. Probe cards appear to be lacking in the technology for above challenges, as such probe card companies need to innovate to align with the change in requirements.
PROBE TEST CHALLENGES
In the traditional single die IC manufacturing process, most of the defective dies are eliminated during wafer test, but due to inherent limitations of wafer sort and cost to overcome them, the industry approach is to allow some test escapes in wafer sort but filter these rejects at end during package testing [5]. The emergence of selling Known Good Dies (KGDs) has brought the importance of wafer sort to its highest level. For the reason of ensuring final yield of flip chip or 3D ICs, KGDs are also important as the die itself is a building block of the final package. With the need of KGDs, wafer level testing is more challenging and it’s effectively a “final test” requirement.
To meet the final test requirement, one noticeable trend is the use of final test socket technology into wafer sort with pogo pins type of probe cards. However, the challenge is really the scaling of fine pitch requirements of these types of probe cards as the current spring probe pogo pin is limited to about 0.3mm pitch. New technology is needed here to minimize the spring probe in order to meet fine pitch requirements.
Traditional interfacing hardware uses pogo tower in wafer sort, as illustrated in below figure 9. In the need for eliminating the long signal path between tester and the semiconductor device under test, a direct docking probe method is used which effectively removes the layer in between loadboard and probe pins. Direct docking requires a redesign of probe card, prober and docking mechanism.
Figure 8: Different copper column bumps and the contacting point after probe
SUMMARY
Wafer level testing will need to accommodate the many trends affecting the semiconductor manufacturing industry. The changes in wafer level testing are driven by wafer level packages, these include WLCSP and flip chip die. As these packages or die advances; the challenges increase due to their form factor in terms of wafer thickness, size and material, bump material, pitch and shape. Different requirements have complicated the test environment and this is especially true for an outsourced semiconductor company that needs to support many different product types and testing requirements. There is no one solution that can fix all situations. Companies need to manage the complexity by standardizing process, equipment and tooling so as to minimize overall manufacturing cost.
REFERENCES
[1] Mark Allison, “Wafer Probe Acquires a New Importance in Testing” Chip Scale Review _ May/June 2005
http://www.electroglas.com/PDF/Wafer_Probe_Testing_Im portance.pdf
[2] Aaron Hand Contributing editor -- EDN, August 24, 2010 “Wafer-level packaging pushes past new mobile demands”
http://www.edn.com/article/510248-Wafer_level_packaging_pushes_past_new_mobile_demand s.php
[3] Chet Palesko and E. Jan Vardaman "Cost Comparison for Flip Chip, Wire Bond, and Wafer Level Packaging," Chip Scale Review, Volume 2, number 1
http://www.chipscalereview.com/archives/0111/index.php
[4] Senthil Theppakuttai, Bahadir Tunaboylu and Bahadir Tunaboylu "Probing Assessment on Fine Pitch Copper Pillar Solder Bumps" IEEE SW Test Workshop
http://www.svprobe.com/SWTW/SV_FPCopperPillarSolder Bumps.pdf
[5] Steve Pateras, “3D-IC Testing with the Mentor Graphics Tessent Platform”
http://www.mentor.com/resources/techpubs/upload/mentorp aper_66946.pdf
