System-on-Chip Design

(1)

System-on-Chip Design

Embedded System Design Challenges

Pierre Boulet – DaRT project-team

(2)

Embedded System Design Challenges

Definition and Significance

System-on-Chip Today

Main Challenges on Design

Some Answers

(3)

Embedded System Design Challenges

Definition and Significance

System-on-Chip Today

Main Challenges on Design

Some Answers

(4)

Definition

What is an embedded system?

É

system

É

set of components needed to perform a

function

É

hardware + software + ...

É

embedded

É

main function

not computing

É

usually not autonomous

É

usually

É

computer inside a system

É

specific purpose

(5)

Examples

É

very small

É

electronic tags

É

smartcards

É

microcontrollers

É

washing machine, microwave oven, ...

É

computer peripherals

É

keyboard

É

hard drive controller

É

more complex controllers

É

digital camera

É

automotive

É

air bags, ABS, ...

(6)

Examples – continued

É

communications

É

mobile phones

É

network routers, modems

É

software radio

É

multimedia

É

set-top boxes

É

cable, satellite TV

É

HDTV, DVD players

É

video games

É

radar, sonar

(7)

Market Significance

É

huge

market

É

estimation 2002 (VDC) : > 1.7 billion units

É

estimation 2003 (VDC) : $760 million for

embedded software

É

number of HW and SW developpers increases

É

becomes

more important than general

purpose computing

É

number of units

É

already

É

number of developpers

(8)

Technology Trends

Overall Roadmap Technology Characteristics 39

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003

The ORTC metrics are often used by semiconductor companies as a set of targets that need to be achieved ahead of schedule to secure industry leadership. Thus, the highly competitive environment of the semiconductor industry quickly tends to make obsolete many portions of the ORTC metrics and, consequently, the Roadmap. Hopefully, the gathering and analysis of actual data, combined with the ITRS annual update process will provide sufficiently close tracking of the evolving international consensus on technology directions to maintain the usefulness of the ITRS to the industry. For example, the actual data and conference papers, along with company survey data and public announcements will be re-evaluated during the year 2004 ITRS update process, and the possibility of a continued two-year node cycle. In addition, logic and Flash product half-pitch acceleration will be monitored for future header leadership candidates. As mentioned above, to reflect the variety of cycles and to allow for closer monitoring of future roadmap shifts, it was agreed to continue the practice of publishing annual technology requirements from 2003 through 2009, called the “Near-term Years,” and at three-year (node) intervals thereafter, called the “Long-“Near-term years” (2012, 2015, 2018), while retaining the previous 2001 ITRS long-term columns for ease of comparison and to retain the tracking of the three-year cycle nodes.

Figure 7 2003 ITRS—Half Pitch Trends

2003 ITRS Technology Trends - 1/2 Pitch

1 10 100 1000 1995 2000 2005 2010 2015 2020 Year Te c h n o lo gy N ode D R A M H a lf -P it c h ( n m )

DRAM 1/2 Pitch - Node MPU M1 1/2 Pitch

2003 ITRS Period: Near-term: 2003-2009; Long-term: 2010-2018 hp90 hp65 hp45 hp32 hp22 2-year Node Cycle 3-year Node Cycle

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Generations

46 Overall Roadmap Technology Characteristics

Table 1i High-Performance MPU and ASIC Product Generations and Chip Size Model—Near-term Years Year of Production 2003 2004 2005 2006 2007 2008 2009 Technology Node hp90 hp65 DRAM ½ Pitch (nm) 100 90 80 70 65 57 50 MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 120 107 95 85 76 67 60

MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) 107 90 80 70 65 57 50

MPU Printed Gate Length (nm) †† 65 53 45 40 35 32 28

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20

Logic (Low-volume Microprocessor) High-performance ‡

Generation at production ** p03h -- p05h -- p07h -- p09h

Functions per chip (million transistors) 439 553 697 878 1,106 1,393 1,756

Chip size at production (mm2) §§ 310 310 310 310 310 310 310

High-performance MPU Mtransistors/cm2 at production

(including on-chip SRAM) ‡ 142 178 225 283 357 449 566 ASIC

ASIC usable Mtransistors/cm2 (auto layout) 142 178 225 283 357 449 566

ASIC max chip size at production (mm2) (maximum

lithographic field size) 572 572 572 572 572 572 572 ASIC maximum functions per chip at production

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Design Productivity Gap

Today, we have the opportunity to define a

reuse strategy that can not only co-exist for

FPGAs and ASICs but can also work

seam-lessly between the two technologies. The

decision to include FPGAs in a Design

Reuse strategy must be made up-front

because it affects almost all phases of the

Design Reuse process, from design

specifica-tion to verificaspecifica-tion planning.

Sharing RTL Design Methods

One of the most exciting outcomes of the

dramatic improvements in FPGA

architec-tures, pricing, and design tools is that this

technology advancement has made it

possi-ble for ASIC and FPGA designers to share a

common RTL design methodology. A

com-mon RTL design methodology is the basis

for a common design reuse methodology.

Though ASICs will continue to provide

higher levels of design integration, higher

speeds, and new EDA environments,

FPGAs are never far behind. The major

FPGA and EDA companies have made a

conscious decision to keep their design

envi-ronments the same, from the end users

point of view, to make it easy for users to

move from one technology to the another.

This was illustrated by the wide adoption of

RTL synthesis tools and verification tools in

the mid-1990s. In the case of RTL synthesis,

existing ASIC methodology was kept the

same and the synthesis algorithms where

changed to target specific FPGA devices.

Today we are seeing higher-level EDA tools

such as Floorplanners and team-based

design tools using the Internet.

Conclusion

In 1999, the number of ASIC design starts

peaked at only 1000 designs, and despite all

the publicity over the multimillion gates

designs, most of these design starts were

under 200K transistors. The average FPGA

design start in 1999 was between 10K and

50K gates, with the fastest growing size range

between 50K and 100K gates. Considering

that FPGAs are more widely used than ASICs

in digital designs today, it makes sense to

include FPGAs in a design reuse strategy.

There are many benefits of sharing a common

design reuse strategy; one of the most

com-pelling is the flexibility it gives the designer to

choose the IC technology late in the design

cycle. It provides the flexibility to choose the

best method to implement an SLI design

without the overhead of retraining the design

teams. In this fast pace market it is difficult to

predict what features your product will need

and what technology you should use.

A Design Reuse strategy is more than RTL code

and synthesis. Many companies reusing designs

have found more value in the design and test

specifications than the actual RTL design. If

you are currently an ASIC user, the good news

is that many of the elements of a good design

reuse methodology can easily incorporate

FPGAs with minimal modifications.

Xilinx has joined efforts with Qualis Design

Corporation to create the first Reuse Design

Guide for FPGA users. This new FPGA Reuse

Field Guide will walk you through the elements

of building a design reuse strategy and is

avail-able, free of charge, from the Xilinx website at:

www.xiliinx.com/ipcenter.

100 10 10 2010 1990 2000 1980 Schematic Capture Logic Synthesis Design Reuse Productivity Gap Moore’s Law Engineering Productivity System Verification Behavioral Compilers

Gates / designer / day

Figure 2 - The productivity gap

Perspective

Design Reuse

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Embedded System Design Challenges

Definition and Significance

System-on-Chip Today

Main Challenges on Design

Some Answers

(12)

System-on-Chip

É

definition

É

(nearly) complete embedded system

É

on a single chip

É

usualy includes

É

programmable processors

É

memory

É

accelerating function units

É

I/O

(13)

Technology Integration

4 System Drivers

Figure 9 First Integration of Technologies in SOC with Standard CMOS Process

SOC M

ULTI

-

TECHNOLOGY

The need to build heterogeneous systems on a single chip is driven by such considerations as cost, form-factor, connection speed/overhead, and reliability. Thus, process technologists seek to meld CMOS with MEMS, and other sensors. Process complexity is a major factor in the cost of SOC-MT applications, since more technologies assembled on a single chip requires more complex processing. The total cost of processing is difficult to predict for future new materials and combinations of processing steps. However, at present cost considerations limit the number of technologies on a given SOC: processes are increasingly modular (e.g., enabling a flash add-on to a standard low-power logic process), but the modules are not generally “stackable”. Figure 9 shows how first integrations of each technology within standard CMOS processes—not necessarily together with other technologies, and not necessarily in volume production—might evolve. CMOS integration of the latter technologies (electro-optical, electro-biological) is less certain, since this depends not only on basic technical advances but also on SOC-MT being more cost-effective than multi-die SIP alternatives. Today, a number of technologies (MEMS, GaAs) are more cost-effectively flipped onto or integrated side-by-side with silicon in the same module depending also on the area and pin-count restrictions of the respective product (e.g. Flash, DRAM). Physical scale in system applications (e.g., ear-mouth = speaker-microphone separation, or distances within a car) also affect the need for single-die integration, particularly of sensors.

SOC H

IGH

-

PERFORMANCE

Examples of SOC-HP include network processors and high-end gaming applications. Since it reflects MPU-SOC convergence, HP follows a similar trend as MPU and is not separately modeled here. However, one aspect of SOC-HP merits discussion, namely, that instances in the high-speed networking domain drive requirements for off-chip I/O signaling (which in turn create significant technology challenges to Test, Assembly and Packaging, and Design). Historically, chip I/O speed (per-pin bandwidth) has been scaling much more slowly than internal clock frequency. This is partly due to compatibility with existing slow I/O standards, but the primary limitation has been that unterminated CMOS signals on printed circuit boards are difficult to run at significantly greater than 100MHz due to slow settling times. During the past decade, high-speed links in technology initially developed for long-haul communication networks have found increasing use in other applications. The high-speed I/O eliminates the slow board settling problems by using point-to-point connections and treating the wire as a transmission line. Today the fastest of these serial links can run at 10Gbit/s per pin.

A high-speed link has four main parts: a transmitter to convert bits to an electrical signal that is injected into the board-level wire, the wire itself, a receiver that converts the signal at the end of the wire back to bits, and a timing recovery circuit that compensates for the delay of the wire and samples the signal on the wire at the right place to get the correct data. Such links are intrinsically mixed-signal designs since receivers, transmitters, and timing recovery all require analog blocks (e.g., the VCO discussed as part of the Mixed-Signal driver is a key component of a timing recovery circuit). Broadly speaking, high-speed links are used in optical systems, chip-to-chip connections, and backplane connections. We now discuss each of these applications in slightly more detail.

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SoC Examples

É

Canon Digic processor family

É

image processor

É

improved quality, power consumption, speed,

cost

É

STI Cell

É

Sony+Toshiba+IBM

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aim at several TFlops at 65nm integration

É

one PowerPC + 8 SIMD units

É

TI OMAP

É

platform

(15)

STI Cell

http:

(16)

OMAP

9

Frame Buffer/Internal SRAM (2 MBit) Timers, Interrupt Controller, RTC

Security: SHA-1/MD5 DES/3DES RNG

GPS Emulator Pod JTAG/ Emulation I/F McBSP MCSI UART UART/IrDA LED Voice Data Control

OMAP1612

TMS320C55x™ DSP ARM926 LCD Controller PWL USB OTG Liquid Crystal Display LCD Light Controller TCS4105 TCS2100 TCS2010 Modem Chipset Buzzer GPIO Keypad LPG PWT Memory Stick MMC-SD LED LPG Keypad GPIO HDQ/1Wire Battery

Memory Stick Card, MMC-SD Card

Memory Stick

MMC-SD Memory Stick Card,MMC-SD Card

ARM Peripherals Baseband Peripherals Shared ARM and DSP Peripherals Dedicated Ports

I2_C Debug Messaging UART Data Voice BRF6100 Bluetooth™ MCSI Serial Fast IrDA 12 MHz 32 kHz Reset Clock and Reset Mgt. TNETw1130 NAND FLASH Compact FLASH EMIF/CF High Speed WLAN

a/b/g FLASH

Mobile DDR

Client Host

Shared Memory Controller/DMA 2D Graphic Accelerator I2_{C Peripheral} In/Out Audio TLC320AIC23 Audio Codec TSC2301 Audio Codec Touch Screen Controller

Audio Amplifier McBSP

µWire

Camera I/F CMOS Sensor EMT9 Debugger

Typical application using the OMAP1612 device

OMAP1612

application processor

For high-performance, space-constrained product platforms, the OMAP1612 application processor includes all the capabilities of the OMAP1611 device plus the added benefit of stacked mobile double data rate (DDR) memory. The significance of DDR memory to system designers is it allows for a 100-MHz interface clock to memory while providing memory access speeds up to 200 MHz. With stacked memory, mobile device manufacturers can design a sys-tem with a very small footprint but expanded memory storage. The stacked memory options include up to 256 Mb of storage. In addition, the OMAP1612 processor’s stacked memory consumes less power than traditional external memory because of reduced load capacitance on the IOs.

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Requirements for PDA SOC-LP

6 System Drivers

• Die size increases on average by 10% per node through 2018 to accommodate increased functionality; this matches

historical trends for the application domain.

• Layout densities for memory and logic fabrics are the same as for the MPU driver, with eDRAM density assumed to

be 3× SRAM density.

• Maximum on-chip clock frequency is approximately 5–10% of the MPU clock frequency at each node.

Peak power dissipation is limited to 0.1 W at 1000

C, and standby power to 2.1 mW, due to battery life. Table 9 System Functional Requirements for the PDA SOC-LP Driver

YEAR OF PRODUCTION 2003 2006 2009 2012 2015 2018

Process Technology (nm) 101 90 65 45 32 22

Supply Voltage (V) 1.2 1 0.8 0.6 0.5 0.4

Clock Frequency (MHz) 300 450 600 900 1200 1500

Application (maximum required performance)

Still Image Processing

Real Time Video Codec

(MPEG4/CIF) Real Time Interpretation

Application (other) Web Browser TV Telephone (1:1) TV Telephone (>3:1)

Electric Mailer Voice Recognition (Input) Voice Recognition

(Operation)

Scheduler Authentication (Crypto

Engine)

Processing Performance (GOPS) 0.3 2 14 77 461 2458

Required Average Power (W) 0.1 0.1 0.1 0.1 0.1 0.1

Required Standby Power (mW) 2 2 2 2 2 2

Battery Capacity (Wh/Kg) 120 200 200 400 400 400

SOC TRENDS

SOC presents Design, Test, PIDS and other areas with a number of technology challenges, such as development of reusable analog IP. The most daunting SOC challenges are:

• design productivity improvement of > 100% per node, with needs including platform-based design7

and integration

of programmable logic fabrics (Design),8

• management of power especially for low-power, wireless, multimedia applications (Design, PIDS),

• system-level integration of heterogeneous technologies including MEMS and optoelectronics (PIDS, FEP, Design),

and

• development of SOC test methodology, with needs including test reusability and analog/digital BIST.

Since SOC is aimed at low-cost and rapid system implementation, and since power is one of the grand challenges in recent ITRS editions, it is appropriate to consider implications of power management on the achievable space of SOC designs. The following discussion develops trend analyses for the SOC-LP driver with respect to this issue.

Two approaches can be used to derive the power dissipation for the SOC-LP model. The first approach is to accept the system specifications (0.1 W peak power, and 2 mW standby power) in a “top-down” fashion. The second approach is to derive the power requirements “bottom-up” from the implied logic and memory content, as well as process and circuit

7

Platform-based design is focused on a specific application domain. The platform embodies the hardware architecture, embedded software architecture, design methodologies for IP authoring and integration, design guidelines and modeling standards, IP characterization and support, and hardware/software verification and prototyping. Derivative designs may be rapidly implemented from a single platform that has a fixed portion and a variable portion that permits proprietary or differentiated designs. (See: H. Chang et al., Surviving the SOC Revolution: A Guide to Platform-based Design, Boston:Kluwer Academic, 1999.)

8_{A programmable logic core is a flexible logic fabric that can be customized to implement any digital logic function after fabrication.}

The structure of a programmable logic fabric may be similar to an FPGA capability within specific blocks of the SOC. They allow reprogrammability, adaptability and reconfigurability, which greatly improve chip productivity. Applications include blocks that implement standards and protocols that continue to evolve, changing design specifications, and customization of logic for different, but related, applications and customers.

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Embedded System Design Challenges

Definition and Significance

System-on-Chip Today

Main Challenges on Design

Some Answers

(19)

Technology Challenges for SoC

Design

É

design productivity

increase

É

main challenge

É

need >100% increase per technology node

É

management of power

É

especially for low-power, wireless, multimedia

applications

É

system-level integration of heterogeneous

technologies

(20)

Target Design Freedom

100% of Design Productivity Improvement

22 System Drivers

T

HE

I

NTERNATIONAL

T

ECHNOLOGY

R

OADMAP FOR

S

EMICONDUCTORS

:

2001

Figure 13 New and Reused Logic Content versus Memory Content with Constant Die Size and

Insufficient (42% Per Node) Design Productivity Growth

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1999 2002 2005 2008 2011 2014 Year Lo gi c A r e a C ont e n t ( % )

Prod. 10% per node Prod. 50% per node Prod. 100% per node Prod. 200% per node

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% M e m or y P e r c e n t a ge -2.00 4.00 6.00 8.00 10.00 12.00

New Circuit Rat io Reuse Circ uit Rat io Target Design Resour ce

Figure 14a Evolution of Maximum Logic

Content with Different Rates of Design

Productivity Improvement

Figure 14b 100% Productivity Improvement

per Node Will Preserve Designer Freedom at

the End of the ITRS Forecast Period

0% 20% 40% 60% 80% 100% 120% 0% 20% 40% 60% 80% 100% M e m o r y Pe r ce n tag e R e u se/ N e w P e r c en ta g e -2.00 4.00 6.00 8.00 10.00 12.00

New Ci r cui t Rati o Reuse Ci r cui t Rat i o T ar get Desi gn Resour ce

2001

R esou rce

New Logic

Reuse Logic

0% 20% 40% 60% 80% 100% 120% 0% 20% 40% 60% 80% 100% M e m o r y Pe r ce n tag e R e u se/ N e w P e r c en ta g e -2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00

New Ci r cui t Rat i o Reuse Ci r cui t Rati o T ar get Desi gn Resour ce

2004

0% 20% 40% 60% 80% 100% 120% 0% 20% 40% 60% 80% 100% M e m o r y Pe r ce n tag e Re u s e /Ne w P e rc e n ta g e -5.00 10.00 15.00 20.00 25.00 30.00 35.00

New Ci r cui t Rat i o Reuse Ci r cui t Rat i o T ar get Desi gn Resour ce

2010

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Logic vs Memory

with Different Rates of Productivity Improvement

22 System Drivers

T

HE

I

NTERNATIONAL

T

ECHNOLOGY

R

OADMAP FOR

S

EMICONDUCTORS

:

2001

Figure 13 New and Reused Logic Content versus Memory Content with Constant Die Size and

Insufficient (42% Per Node) Design Productivity Growth

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1999 2002 2005 2008 2011 2014 Year Lo gi c A r e a C ont e n t ( % )

Prod. 10% per node Prod. 50% per node Prod. 100% per node Prod. 200% per node

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% M e m or y P e r c e n t a ge -2.00 4.00 6.00 8.00 10.00 12.00

New Circuit Rat io Reuse Circ uit Rat io Target Design Resour ce

Figure 14a Evolution of Maximum Logic

Content with Different Rates of Design

Productivity Improvement

Figure 14b 100% Productivity Improvement

per Node Will Preserve Designer Freedom at

the End of the ITRS Forecast Period

New Ci r cui t Rati o Reuse Ci r cui t Rat i o T ar get Desi gn Resour ce

2001

R esou rce

New Logic

Reuse Logic

0% 20% 40% 60% 80% 100% 120% 0% 20% 40% 60% 80% 100% M e m o r y Pe r ce n tag e R e u se/ N e w P e r c en ta g e -2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00

New Ci r cui t Rat i o Reuse Ci r cui t Rati o T ar get Desi gn Resour ce

2004

0% 20% 40% 60% 80% 100% 120% 0% 20% 40% 60% 80% 100% M e m o r y Pe r ce n tag e Re u s e /Ne w P e rc e n ta g e -5.00 10.00 15.00 20.00 25.00 30.00 35.00

2010

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SoC Design Cost Model

2 Design

Figure 13 Impact of Design Technology on SOC LP-PDA Implementation Cost

This chapter first presents silicon complexity and system complexity challenges, followed by five crosscutting challenges (productivity, power, manufacturing integration, interference, and error tolerance) that permeate all DT areas. The bulk of the chapter then sets out detailed challenges according to a traditional landscape of DT areas (see Figure 14): design

process; system-level design; logical, circuit and physical design; design verification; and design test.1 These challenges

are discussed at a level of detail that is actionable by management, R&D, and academia in the target supplier community, i.e., the electronic design automation (EDA) industry. As appropriate, the detailed challenges are mapped to the MPU, SOC, AMS, and memory system drivers; most challenges map to MPU and SOC, reflecting today’s EDA technology and market segmentation. A brief unified overview of AMS-specific DT is given to reflect the rise of application- and driver-specific DT, and the likely organization of future ITRS Design Chapter editions according to system drivers, rather than traditional areas of DT.

1

Additional discussion of analog/mixed-signal circuits issues is contained in the System Drivers Chapter (AMS Driver). Test equipment and the test of manufactured chips are discussed in the Test Chapter, while this chapter addresses design for testability, including built-in self test (BIST).

$ 1 0 , 0 0 0 , 0 0 0 $ 1 0 0 , 0 0 0 , 0 0 0 $ 1 ,0 0 0 , 0 0 0 , 0 0 0 $ 1 0 ,0 0 0 , 0 0 0 , 0 0 0 $ 1 0 0 ,0 0 0 , 0 0 0 , 0 0 0 1 9 8 5 1 9 9 0 1 9 9 5 2 0 0 0 2 0 0 5 2 0 1 0 2 0 1 5 2 0 2 0 Y e a r R T L M e t h o d o l o g y O n ly W it h A l l F u tu r e I m p r o v e m e n ts T a ll T h in E ngi neer S m al l B loc k R eus e IC I m plem en ta tio n t ools Lar ge B loc k R eus e In te lligent T e st benc h E S Lev el M e thodo logy V e ry Lar ge B loc k R eus e 6 2 9 ,7 6 9 , 2 7 3 2 0 , 1 5 2 , 6 1 7 To ta l D e s ign C o s t In hous e P & R

(23)

Design Cost Problem

É

economy will limit the semiconductor industry

É

before the end of Moore’s law

É

today design time

É

30% design

(24)

Complexity Challenge

É

silicon complexity

É

impact of process scaling and new materials

and architectures

É

previously ignorable phenomena now have

impact

É

system complexity

É

reuse

É

verification and test

É

cost-driven design optimization

É

embedded software design

É

reliable implementation platforms

É

design process management

É

together:

superexponentially increasing

(25)

Methodology Precepts

ITRS

É

exploit reuse

É

evolve rapidly

É

avoid iteration

É

replace verification by prevention

É

improve predictability

É

orthogonalize concerns

É

expand scope

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Embedded System Design Challenges

Definition and Significance

System-on-Chip Today

Main Challenges on Design

Some Answers

(27)

Reuse

É

IP

É

IP = Intellectual Property

É

HW or SW block

É

designed for reuse

É

need of standards

(VSIA)

É

platform

based SoC design

É

organized method

É

to reduce cost and risk

É

by heavy reuse of HW and SW IPs

É

steps in reuse

(28)

Raising the Abstraction Level

É

ESL

(Electronic System Level)

É

from RTL to TLM or higher

É

from VHDL to SystemC to UML

É

HW/SW

co-design

É

need new tools

É

consider the whole system

É

large optimization potential

É

combination of formal, semi-formal and non

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Consumption

Lower Bound for Fixed Chip Size

System Drivers 7

parameters. Logic power consumption is estimated based on αCVdd 2

f + IoffVdd model for dynamic plus static power,

using area-based calculations similar to those in the MPU power analysis. The memory power consumption model also uses αCVdd2f + IoffVdd with a different factor for α.9 For these calculations, we refer to the low-power device roadmap

described in the PIDS Chapter. It is almost certain that future low-power SOCs will integrate multiple (LOP, LSTP, HP) technologies simultaneously within the same core, to afford greater control of dynamic power, standby power, and performance.

Figure 10 shows the “bottom-up” lower bound for total chip power at an operating temperature of 100°C, assuming that all logic is implemented with LOP or LSTP devices and operates as described in Footnote 25. We say that this is a lower bound since in practice some logic would need to be implemented with faster, higher-current devices. The figure suggests that SOC-LP power levels will exceed the low-power requirements of the PDA application, and further provides a breakdown of power contributions for each case. As expected, LOP power is primarily due to standby power dissipation while LSTP power is primarily due to dynamic power dissipation10_{. Total chip power using only LOP devices reaches} 1.39 W in 2018, mostly due to a sharp rise in static power after 2012. Total chip power using only LSTP devices reaches 1.27 W in 2018; almost all of this is dynamic power.

Figure 10 Total Chip Power Trend for SOC-LP PDA Application

9_I

off denotes the NMOSFET drain current at room temperature, and is the sum of the NMOS sub-threshold, gate, and junction leakage

current components, as described in the PIDS chapter. Details of active capacitance density calculations, dependences on temperature and threshold, etc. may be found in the PIDS Chapter documentation and in the following supplemental file. The activity of logic blocks is fixed at 10%. The activity of memory blocks is estimated to be 0.4% based on the following analysis of large memory designs. We first assume that a memory cell contributes 2 gate capacitances of minimum size transistors for switching purposes, accounting for source/drain capacitances, contact capacitances and wiring capacitance along the bit lines. A write access requires power in the row/column decoders, word line and M bit lines, sense amplifiers and output buffers. We consider memory to be addressed with 2N bits and assume that memory power is due primarily to the column capacitances, and that Mx2N_{bits are accessed simultaneously out of}

2N_x2N_{possible bits. Then}_α_=M/2N_{which is the ratio of accessed bit to total bits in the memory. For example, for a 16 Mbit memory,}

M=16 and N=12; hence α=0.4%.

10_{At 25°C, dynamic power dissipation dominates the total power in both the LOP and LSTP cases.}

Power Trend 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 2003 2006 2009 2012 2015 2018 Year Po w e r ( W )

- Dynamic Power LOP (W) - Dynamic Power LSTP (W) - Static Power LOP (W ) - Static Power LSTP (W) - Memory Power LOP (W) - Memory Power LSTP (W) - Power for LOP Bottom-Up (W) - Power for LSTP Bottom-Up (W )