w12_arithematic.pdf

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Computer Arithmetic

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 Does arithmetic and logical operations

 Everything else in the computer is there to service this unit

 Based on digital logic services that can store binary digits

 Handles integers

 May handle floating point (real) numbers

 May be separate FPU (maths co-processor)

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ALU I

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 Only have 0 & 1 to represent everything

 Numbers stored in binary

 e.g. 41=00101001  No minus sign

 No period

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 Left most bit is sign bit

 0 means positive

 1 means negative

 +18 = 00010010

 -18 = 10010010

 Problems

 Need to consider both sign and magnitude in

arithmetic

 Two representations of zero

+010 = 00000000

-010 = 10000000 5

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 +3 = 00000011

 +2 = 00000010

 +1 = 00000001

 +0 = 00000000

 -1 = 11111111

 -2 = 11111110

 -3 = 11111101

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 One representation of zero

 Arithmetic works easily (see later)

 Negating is fairly easy

 3 = 00000011

 Boolean complement gives 11111100  Add 1 to LSB 11111101

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+18 = 0000000000010010 (sign magnitude, 16 bits) -18 = 10010010 (sign magnitude, 8 bits) -18 = 1000000000010010 (sign magnitude, 16 bits)

+18 = 00010010 (Two’s Complement, 8 bits)

+18 = 0000000000010010 (Two’s Complement, 16 bits)

-18 = 11101110 (Two’s Complement, 8 bits )

-32.658 = 1000000000010010 (Two’s Complement, 16 bits)

-18 = 11101110 (Two’s Complement, 8 bits)

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 +18 = 00010010 (Two’s Complement)

 Bitwise not 11101101

 Add 1 to LSB +1

 Result 11101110 = -18

 -18 = 11101110 (Two’s Complement)

 Bitwise not 00010001

 Add 1 to LSB +1

Result 00010010 = +18

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 0 = 00000000

 Bitwise not 11111111

 Add 1 to LSB +1

 Result 1 00000000

 Overflow is ignored, so:

 - 0 = 0

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 -128 = 10000000

 bitwise not 01111111

 Add 1 to LSB +1

 Result 10000000

 So:

 -(-128) = -128 X

 Monitor MSB (sign bit)

 It should change during negation

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 8 bit 2s compliment

 +127 = 01111111 = 27 -1  -128 = 10000000 = -27  16 bit 2s compliment

 +32767 = 011111111 11111111 = 215 - 1  -32768 = 100000000 00000000 = -215

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 Normal binary addition

 Monitor sign bit for overflow

 Take twos compliment of subtrahend and add to minuend

 i.e. a - b = a + (-b)

 So we only need addition and complement circuits

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0000 = 2 +1001 = -7 1011 = -5

(a) M = 2 = 0010 S = 7 = 0111 -S = 1001

0101 = 5 + 1110 = -2 0011 = 3

(b) M = 5 = 0101 S = 2 = 0010 - S = = 1110

1011 = -5 + 1110 = -2

1001 = -7

(b) M = -5 = 1011 S = 2 = 0010 - S = = 1110

0101 = 5 + 0010 = 2 0111 = 3

(b) M = 5 = 0101 S = -2 = 1110 - S = = 0010

0111 = 7 + 1001 = 7 0000 = OF

(b) M = 7 = 0111 S = -7 = 1001 - S = = 0111

1010 = -6 + 1100 = -4

0110 = OF

(b) M = -6 = 1010 S = 4 = 0100 - S = = 1100

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 Complex

 Work out partial product for each digit

 Take care with place value (column)

 Add partial products

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 1011 Multiplicand (11)

 x 1101 Multiplier (13)

 1011 Partial products

 0000 Note: if multiplier bit is 1 copy

 1011 multiplicand (place value)

 1011 otherwise zero

 10001111 (143)

 Note: need double length result

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If numbers are unsigned

1 0 0 1 ( 9 ) + 0 0 1 1 ( 3 ) 1 1 0 0 ( 12 )

If numbers are two’s complement 1 0 0 1 ( -7 ) + 0 0 1 1 ( 3 )

1 1 0 0 ( -4 ) 23

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If numbers are unsigned

1 0 0 1 ( 9 ) x 1 1 0 1 ( 13 ) 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 1 0 1 0 1 (117)

If numbers are represented in two’s complement 1 0 0 1 ( -7 ) x 1 1 0 1 ( -3 ) 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0

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 This does not work!

 Solution 1

 Convert to positive if required  Multiply as above

 If signs were different, negate answer  Solution 2

 Booth’s algorithm

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 More complex than multiplication

 Negative numbers are really bad!

 Based on long division

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001111

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1011

00001101 10010011

1011 001110

1011

1011 100

Quotient

Dividend

Remainder Partial

Remainders Divisor

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1 - Load the divisor into the M register and the dividend into the A, Q registers. The dividend must be expressed as a 2n-bit two’s complement number. This, for example , the 4-bit 0111 becomes 00000111, and 1001 becomes 11111001.

2 - shift A, Q left 1 bit position.

3 - if M and A have the same signs, perform A = A - M otherwise A = A + M

4 – the preceding operation is successful if the sign of A is the same before and after the operation.

a. if the operation is successful or A = 0 then set Q0 = 1 b. if the operation is unsuccessful and A is not equal to 0, then set Q0 = 0 and restore the previous value of A

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5 – Repeat steps 2 through 4 as many times as there are bit positions in Q.

6 – the remainder is in A. if the signs of the divisor and dividend were the same, then the quotient is in Q, otherwise, the correct quotient is the two’s complement of Q.

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 Numbers with fractions

 Could be done in pure binary

 1001.1010 = 23 + 20 +2-1 + 2-3 =9.625  Where is the binary point?

 Fixed?

 Very limited  Moving?

 How do you show where it is?

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 +/- .significand x 2exponent

 Misnomer

 Point is actually fixed between sign bit and body of mantissa

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 Mantissa is stored in 2s compliment

 Exponent is in excess or biased notation

 e.g. Excess (bias) 128 means  8 bit exponent field

 Pure value range 0-255

 Subtract 128 to get correct value  Range -128 to +127

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 FP numbers are usually normalized

 i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1

 Since it is always 1 there is no need to store it

 (c.f. Scientific notation where numbers are normalized to give a single digit before the decimal point

 e.g. 3.123 x 103)

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FP R

 For a 32 bit number

 8 bit exponent  +/- 2256  1.5 x 1077  Accuracy

 The effect of changing lsb of mantissa  23 bit mantissa 2-23  1.2 x 10-7

 About 6 decimal places

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IEEE 754

 Standard for floating point storage

 32 and 64 bit standards

 8 and 11 bit exponent respectively

 Extended formats (both mantissa and exponent) for intermediate results

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IEEE 754 F

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FP A

+/-

 Check for zeros

 Align significands (adjusting exponents)

 Add or subtract significands

 Normalize result

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FP A

& S

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FP A

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/

 Check for zero

 Add/subtract exponents

 Multiply/divide significands (watch sign)

 Normalize

 Round

 All intermediate results should be in double length storage

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 Stallings Chapter 9

 IEEE 754 on IEEE Web site P

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