Simulation and Design Route Development for ADEPT-SiP

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Simulation and Design Route

Development for ADEPT-SiP

Alaa Abunjaileh, Peng Wong and Ian Hunter The Institute of Microwaves and Photonics School of Electronic and Electrical Engineering

The University of Leeds Malcolm Edwards

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Outline

HDI/ Substrate Architecture

Passive Components Modelling

Resistors

Capacitors

Inductors

Transmission lines/resonators

Work Plan and Developments

End Users Demonstrators

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ADEPT-SiP Architecture

embedded passives ADEPT-SiP module HDI substrate active devices encapsulation motherboard

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ADEPT-SiP PCB Substrate Architecture

• The ADEPT-SiP printed circuit board architecture involves:

– 6-layer board construction with 2 conductor layer core

sequential build-up.

– High Density Interconnect (HDI) layers on either side of this

core.

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Design Rules –

HDI/Microvia

• Outer Layer ¾ Track width>100μm

¾ Distance track-track width>125μm

• Inner Layer ¾ Track width>100μm

¾ Distance track-track width>100μm

• Microvia

¾ Standard - padΦ=300μm

¾ Stacked - padΦ=300μm

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Design route development

• Well-defined process architecture • Stable process & known capabilities

• Produce component characterisation boards

• RFOW measurements

• S-parameter extraction • Model generation

• Design kit integration

Ground Signal Ground Ground Signal Ground

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Design route application

• design specification

• schematic capture - hierarchical • simulation & optimisation

• component generation • circuit layout

• re-simulation

• design tolerance & yield

• design for test, reliability.... • mask layout • verification - DRC, LVS • design documentation Design Specification Circuit Description Component & Layout Libraries Analysis Optimisation Layout Verification Fabrication Models Design Rules

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Passive Components Simulations

• Test Vehicle 1 (TV1) Modelling and Simulations

Summery:

– 30 Microstrip transmission lines (including coplanar)

– 48 Spiral Inductors ( Square and Circular)

– 56 Capacitors (PTF and Prepreg)

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Transmission lines

Interconnect coupon is divided into four 25x25mm areas, where the line lengths are 5, 10 and 20mm.

Zo(Ω) Tx line type Structure Line width (μm)

(w-width, s-spacing)

50 Microstrip M1M3 (M1 trace, M3 ground) w50+15=>170

i.w50=>185

ii.w50-15=>200 50 Microstrip M2M3 (M2 trace, M3 ground) w50+15=>113

i.w50=>98

50 CPW M2 coplanar w=1880, s=100

50 CPW M1 coplanar w=1080, s=100

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Transmission Lines and Resonators

• Coplanar Waveguide ¾ M1 (Ground Plane), t= 36 μ m ¾ Zo = 100Ω ¾ l = 5, 10, 20mm, h=60 μ m ¾ εr=5.4, tangent loss=0.035

• Supported Coplanar Waveguide*

¾ M2 (Ground Plane), t= 9 μ m

¾ Zo = 50 Ω, 100Ω

¾ l = 5, 10, 20mm, h=60 μ m

¾ εr=5.4, tangent loss=0.035

.

*S. S. Bedair and I. Wolff, “Fast, Accurate and Simple Approximate Analysis Formulas for Calculating the Parameters of Supported Coplanar Waveguides for MMIC’s,” IEEE Trans. Microwave Theory Tech., Vol.40, No.

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Polymer Thick Film Resistors

• 100Ω/square carbon based inks are used.

Length(mm) Width (mm) 0.5 1 1.5 3 5 0.5mm width family 100 Ω 200 Ω 300 Ω 600 Ω 1000 Ω 1.0mm width family 50Ω 100 Ω 150 Ω 300 Ω 500Ω 2.0mm width family 25Ω 50Ω 75Ω 150 Ω 250Ω 3.0mm width family 16.6 7Ω 33.3 Ω 50Ω 100 Ω 166.6 7Ω

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Capacitors

• Two classes of capacitors:

– Polymer Thick Film Capacitors – Prepreg Capacitors

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PTF Capacitors

•Thickness 20um •Dielectric constant = 40 •Capacitance 16pF/mm2

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Prepreg

Capacitors

– Thickness 50um

– Dielectric constant = 4 – Capacitance 1pF/mm2

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Copyright © 2007 Prepreg Capacitor 0 2 4 6 8 10 12 14 1 1.5 2 2.5 3 3.5 4 Dimensions (Squared mm) C a p a c ita n c e (p F ) M1M2_THRU_M3_KEEPOUTS-Cal M1M2_THRU_M3_KEEPOUTS-Sim M1M2_THRU_M3_GROUNDED-Cal M1M2_THRU_M3_GROUNDED-Sim M1M2_COMMON_ELECTRODE_THRU_M3_KEEPOUTS-Sim

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Prepreg Capacitor 0 2 4 6 8 10 12 14 16 1 1.5 2 2.5 3 3.5 4 Dimensions (Squared mm) R es ona nt Fre q ( G H z) M1M2_THRU_M3_KEEPOUTS-Res M1M2_COMMON_ELECTRODE_THRU_M3_KEEPOUTS-Res M1M2_THRU_M3_GROUNDED-Res

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Inductors

• TV1 include Square and Circular Spiral inductor classes.

• The inductor spirals are defined on Conductive Layer 1 (M1) and the underpass on Conductive Layer 2 (M2).

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Inductors

Inductors; Circular Spirals with Gnd keep outs of 125, 250 and 500um 0 20 40 60 80 100 120 0 1 2 3 4 5 6 7 8 No. of Turns In d u ct an ce n H 0 5 10 15 20 25 30 Q u al it y F act o r L125 L250 L500 L_Q_250 L_Q_125 L_Q_500

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Inductors

Inductors; Circular Spirals with Gnd keep outs of 125, 250 and 500um with the respective cutoff frequency

0 20 40 60 80 100 120 0 1 2 3 _{No. of Turns}4 5 6 7 8 Induc ta nc e nH 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 Fr e q ( G H z) L125 L250 L500 L_CF_125 L_CF_250 L_CF_500

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TV 1 Inductors Coupon

Inductance Line width

Spacing

Number of Turns Rin

Quality Factor Line width

Total length Conductivity

Self resonance frequency Substrate dielectric constant

Substrate thickness Total length

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Future Developments

• Improve inductors performance (L, Q, Fres). • Study various configurations for embedded

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TV 2 Calibration Coupon

• Transmission lines (also resonators)

– Short – Open – Loaded – Terminated • Coupled Lines • Ring resonators – At 3 and 5GHz

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TV2 Partners Contribution

• Filtronic

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AWR Design Environment

• The Designers View … mixed technology

M1 M1 Cap_PTF_M1M1 ID=Cap_PTF1 L=1000 um W=1000 um C=17.7 pF IND ID=L1 L=1 nH IND ID=L2 L=3 nH VIA ID=V1 D=127 um H=1651 um T=17.78 um RHO=0.7 VIA ID=V2 D=127 um H=1651 um T=17.78 um RHO=0.7 SMD Embedded Passive

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AWR Design Environment

• The Designers View … 2D and 3D views

2D View 3D View

The Process Design Kit (PDK) defines

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AWR Design Environment

<SUMMARY>This file contains data for the Wurth Elektronik 6 Layer HDI Process</SUMMARY> <COMPONENT Name="CAP PTF M1M1">

<DESC>PTF Capacitor with 2 Pins and integrated vias to M1</DESC> <SYMBOL>[email protected]</SYMBOL>

</COMPONENT>

Points to a parametric cell (pCELL) located in DLL Points to model located in DLL

Initial Parameter used to define the component

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AWR Design Environment

• Parametric Cells …

– The AWR Design Environment supports ‘CALL BACK’

– Models can report back to the schematic symbol

M1 M1 Cap_PTF_M1M1 ID=Cap_PTF1 L=1000 um W=1000 um C=17.7 pF Edit the size

of the capacitor M1 M1 Cap_PTF_M1M1 ID=Cap_PTF1 L=1000 um W=500 um C=8.85 pF Editing can be conducted using the layout editor

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AWR Design Environment

• The AWR Design Environment supports multiple

technology … load more than one PDK!

SMD Embedded Passive

GaAs MMIC

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Conclusion

• TV2 Should include components with optimum

performance (R, L, C, Q and Fres). Various

configurations will be studied to obtain the best performance.

• The modelled components and results will be

built into the AWR-Process Design Kit (PDK), to design microwave devices (filters, baluns…etc) and partners demonstrators.