D-Type flip-flop (Toggle switch)
The D-type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure 1 shows how the flip-flop (latch) can be made using 2-input logic circuits and Figure 2 shows the input and output waveforms
The enable pin needs to be high for data to be fed to the outputs Q and Q bar.
The output will only change on the falling edge or trailing edge of the applied clk input.
D
Enable
NAND NOT NAND NAND NANDQ
Q
Latch
Figure 1 Simple D-type Flip-flop circuitThe D type flip-flop has only one input (D for Data) apart from the clock. The INDETERMINATE state is avoided with this flip-flop.
When the clock goes high, D (a 0 or a 1) is transferred to Q. When the clock goes low, Q remains unchanged.
Q stores the data until the clock goes high again, when new data may be available.
Figure 2 Output waveforms of the D-type flip-flop. In this circuit the Q output changes state on the leading edge of the clock.
At A, clock and data are high. Q goes high and stays high until B. At B, clock is high and data is low. Q goes low and stays low until C.
At C, clock and data are both high. Q goes high and stays high until E.
Q does not change during clock pulse D, because clock and data are still both high.
At E, data is low, so Q goes low. At F, data is high so Q goes high.
As with the other flip-flop circuits the operation can be improved to eliminate indeterminate states by adding a master latch. The circuit of the master-slave D-type flip-flop is shown in the ADS simulation setup shown in Figure 3.
The inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half-cycles of the clock signal.
Each logic gate is made up of CMOS FETS (based on the 0.8um process) as described in the other tutorials on individual gates.
Clk Q_bar Q D VtPulseDT SRC4 Rout=1 Ohm Period=100 usec Width=50 usec Delay=25 usec Vhigh=5 V Vlow=0 V DT D Tran Tran1 MaxTimeStep=250 StopTime=150 usec TRANSIENT VtPulseDT SRC2 Rout=1 Ohm Period=20 usec Width=10 usec Delay=0 nsec Vhigh=5 V Vlow=0 V DT Clk NAND_buffered X9 buffered NAND OUT Vcc B A V V_DC SRC1 Vdc=5.0 V V Port D Num=1 NAND_buffered X3 buffered NAND OUT Vcc B A V NAND_buffered X2 buffered NAND OUT Vcc B A V NAND_buffered X4 buffered NAND OUT Vcc B A V NAND_buffered X5 buffered NAND OUT Vcc B A V NAND_buffered X6 buffered NAND OUT Vcc B A V NAND_buffered X8 buffered NAND OUT Vcc B A V NAND_buffered X7 buffered NAND OUT Vcc B A V Port Clk Num=1 NOT X10 NOT IN OUT Vcc V Port Q Num=3 Port Q_bar Num=4
Figure 3 ADS simulation setup of the master-slave D-type flip-flop circuit. In this simaulation there are two square wave generators, the clock at 50KHz and the data (with a 25us delay) running at 10KHz. The simulation is a time-domain transient.
The resulting simulation of the circuit shown in Figure 3 is shown in Figure 4. 20 40 60 80 100 120 140 0 160 0 1 2 3 4 5 -1 6 tim e, usec Clk , V 20 40 60 80 100 120 140 0 160 0 1 2 3 4 5 -1 6 tim e, usec D, V 20 40 60 80 100 120 140 0 160 0 1 2 3 4 5 -1 6
D-type Flip-flop transitions occur on the falling
of the Clk input
tim e, usec Q,
V
Figure 4 Simulation of the Master-slave D-type flip-flop. Note that the transitions occur on the falling edge of the applied clock signal+1/2 half clock cycle due to the slave action.
The D-type flip-flop can be configured as a T-type or Toggle flip-flop. With this configuration the Q_bar output is connected to the D input and the signal/clock is connected to the clk input. The output of this flip-flop will have a frequency half that of the input.
The ADS simulation of Figure 6 is shown below (Figure 5)
20 0 40 60 80 100 120 140 160 0 1 2 3 4 5 -1 6
time, usec
Clk
, V
20 40 60 80 100 120 140 0 160 0 1 2 3 4 5 -1 6time, usec
Q,
V
Figure 5 Simulation results of the D-type flop configured as a T-type (Toggle) flip-flop by connecting the D input to the Q_bar output. Such circuits are common in frequency prescalar circuits.
D-type Flip-flop transitions occur on the falling
of the Clk input. This D-type is configured as
a T-type toggle flip-flop
Clk
Q
V_DC
SRC1
Vdc=5.0 V
V
VtPulseDT
SRC2
Rout=1 Ohm
Period=20 usec
Width=10 usec
Delay=0 nsec
Vhigh=5 V
Vlow=0 V
DTClk
Port
Q
Num=3
Tran
Tran1
MaxTimeStep=250 nsec
StopTime=150 usec
TRANSIENT
NAND_buffered
X9
buffered NAND OUT Vcc B AV
NAND_buffered
X3
buffered NAND OUT Vcc B AV
NAND_buffered
X2
buffered NAND OUT Vcc B AV
NAND_buffered
X4
buffered NAND OUT Vcc B AV
NAND_buffered
X5
buffered NAND OUT Vcc B AV
NAND_buffered
X6
buffered NAND OUT Vcc B AV
NAND_buffered
X8
buffered NAND OUT Vcc B AV
NAND_buffered
X7
buffered NAND OUT Vcc B AV
Port
Clk
Num=1
NOT
X10
NOT IN OUT VccV
RF Application
Phase detectors are part of a Phase Locked Loop (PLL) and can be either analogue eg mixer or digital eg D-type flip-flop. When a mixer is used the output consists of the sum and
difference frequencies.
In an analogue mixer a number of different frequencies are generated within the mixer namely the sum of the frequencies and the difference frequency (otherwise known as the beatnote) when both input frequencies are the same is the phase difference is zero and the beatnote is DC.
Most PLL circuits now use digital phase detectors formed from two D-type flip-flops as shown in Figure 7.
