LPC-P1343

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LPC-P1343 development board

Users Manual

All boards produced by Olimex are ROHS compliant

Revision Initial, December 2009

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INTRODUCTION

LPC-P1343 is development board with LPC1343 ARM Cortex-M3 based microcontrollers for embedded applications from NXP. LPC-P1343 featuring a high level of integration and low power consumption. This microcontroller supports

various interfaces such as one Fast-mode Plus I2_{C-bus interface, USB, UART, SSP}

in-terfaces, four general purpose timers, a 10-bit ADC. On the board are available UEXT, Debug Interface, user buttons, USB device and user leds. All this allows you to build a diversity of powerful applications to be used in a wide range of applica-tions.

BOARD FEATURES

• MCU: LPC1343 Cortex-M3, up to 70 Mhz, 32 kB Flash, 8kB SRAM,

UART RS-485, USB, SSP, I2_{C/Fast+, ADC}

• Power supply circuit

• Power-on led

• USB connector and functionality

• USBC led

• Debug interface – SWD (Serial Wire Debug)

• UEXT connector

• Eight user leds

• Two user buttons

• Reset button

• Prototype area

• FR-4, 1.5 mm, soldermask, component print

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ELECTROSTATIC WARNING

The LPC-P1343 board is shipped in protective anti-static packaging. The board must not be subject to high electrostatic potentials. General practice for working with static sensitive devices should be applied when working with this board.

BOARD USE REQUIREMENTS

Cables:The cable you will need depends on the programmer/debugger you use. If

you use ARM-JTAG-EW, you will need USB A-B cable.

Hardware: Programmer/Debugger ARM-JTAG-EW or other compatible programming/debugging tool if you work with EW-ARM.

PROCESSOR FEATURES

LPC-P1343 board use ARM Cortex™-M3 microcontroller LPC1343FBD48/301 from NXP Semiconductors with these features:

– ARM Cortex-M3 processor, running at frequencies of up to 72 MHz

– ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

– 32kB on-chip flash programming memory. Enhanced flash memory

accelerator enables high- peed 72 MHz operation with zero wait states

– In-System Programming (ISP) and In-Application Programming (IAP) via

on-chip bootloader software.

– Serial interfaces:

- USB 2.0 full-speed device controller with on-chip PHY for device - UART with fractional baud rate generation, modem, internal FIFO and RS-485/EIA-485 support.

- SSP controller with FIFO and multi-protocol capabilities.

- I2_{C-bus interface supporting full I}2_{C-bus specification and}

Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.

– Other peripherals:

- 42 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors and a new, configurable open-drain operating mode.

- Four general purpose timers/counters, with a total of four capture inputs and 13 match outputs.

- Programmable WatchDog Timer (WDT). - System tick timer.

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– High-current output driver (20 mA) on one pin.

– High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

– Integrated PMU (Power Management Unit) to minimize power

consumption during Sleep, Deep-sleep, and Deep power-down modes.

– Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

– Single 3.3 V power supply (2.0 V to 3.6 V).

– 10-bit ADC with input multiplexing among 8 pins.

– 40 GPIO pins can be used as edge and level sensitive interrupt sources.

– Clock output function with divider that can reflect the main oscillator clock,

IRC clock, CPU clock, Watchdog clock, and the USB clock.

– Processor wake-up from Deep-sleep mode via GPIO interrupts.

– Brownout detect with four separate thresholds for interrupt and one

threshold for forced reset.

– Power-On Reset (POR).

– Crystal oscillator with an operating range of 1 MHz to 25 MHz.

– 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally

be used as a system clock.

– PLL allows CPU operation up to the maximum CPU rate without the need

for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the Watchdog oscillator.

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SCHEMATIC

C L O S E C L O S E H N 1 x2 T 1 1 5 7 T 1 1 5 7 1 0 0 n F 27 p F 2 7 p F 1 0 0 n F 18p(NA) 18p(NA) 1 0 n F 1 0 0 n F 1 0 u F /6 .3 V /T A N T B A T 5 4 C re d re d re d re d re d re d re d re d 1 2 M H z/ 2 0 p F 5 6 0 R 5 6 0 R 1 0 k 1 0 k 1 0 k 1 0 k 1 0 k 1 0 k 1 k 1 k 3 3 R 3 3 R 1 .5 k/ 1 % 5 6 0 R 2 .0 k 2 .0 k 1 0 k 1 0 k 5 6 0 R 2 4 0 R /1 % 3 9 0 R /1 % IT 11 85 A U 2 B H 2 0 S D T A 1 1 4 Y K A L P C 1 3 4 3 F B D 4 8 B H 10 S B H 10 S B H 10 S B H 10 S B H 10 S B H 10 S B H 10 S B H 10 S B H 10 S B H 10 S M IC R O _ B ye llo w 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V 3 .3 V L M 1 1 1 7 IM P X -A D J # U S B _ C O N N E C T # U S B _ C O N N E C T + 5 V _ JL IN K + 5 V _ JL IN K C S C S D + D -M IS O M IS O M O S I/ S W V M O S I/ S W V M O S I/ S W V R S T N R S T N R X D R X D S C K S C K S C L S C L S D A S D A S W C S W C S W D S W D T X D T X D U 2 D + U 2 D -U S B _ V B U S U S B _ V B U S U S B _ V B U S U S E R U S E R WA K E _ U P W A K E _ U P 1 2 3 3 .3 V 1 2 3 .3 V _ C O R E _ E 1 2 3 .3 V _ IO _ E 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 ₁5 ₁6 ₁7 1 8 1 9 ₂0 2 1 2 2 ₂3 2 4 2 5 2 6 27 28 29 30 3 1 3 2 ₃3 ₃4 ₃5 3 6 3 7 3 8 3 9 4 0 ₄1 4 2 4 3 4 4 4 5 ₄6 ₄7 4 8 1 2 B L D _ E B U T 1 B U T 2 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 D + D -D 1 G N D G N D _ P IN L E D 0 L E D 1 L E D 2 L E D 3 L E D 4 L E D 5 L E D 6 L E D 7 P 0 _ 1 P 0 _ 2 P 0 _ 3 P 0 _ 4 P 0 _ 5 P 0 _ 6 P 0 _ 7 P 0 _ 8 P 0 _ 9 P 0 _ 1 0 P 0 _ 1 1 P 1 _ 0 P 1 _ 1 P 1 _ 2 P 1 _ 3 P 1 _ 4 P 1 _ 5 P 1 _ 6 P 1 _ 7 P 1 _ 8 P 1 _ 9 P 1 _ 1 0 P 1 _ 1 1 P 2 _ 0 P 2 _ 1 P 2 _ 2 P 2 _ 3 P 2 _ 4 P 2 _ 5 P 2 _ 6 P 2 _ 7 P 2 _ 8 P 2 _ 9 P 2 _ 1 0 P 2 _ 1 1 P 3 _ 0 P 3 _ 1 P 3 _ 2 P 3 _ 3 P W R Q 1 R -M A T 1 R -M A T 2 R 1 R 4 R 5 R 6 R 7 R 8 R 9 R 1 0 R 1 1 R 1 2 R 1 3 R 1 4 R 1 5 R 1 6 R 1 7 R 1 8 R 1 9 R 2 0 R 2 1 R E S E T R S T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S W D T 1 #R E S E T /P IO 0_ 0 3 #T R S T /P IO 1_ 2/ A D 3/ C T 32 B 1_ M A T 1 35 P IO 0_ 1/ C LK O U T /C T 32 B 0_ M A T 2/ U S B _F R A M E _T O G G LE 4 P IO 0_ 2/ S S E L/ C T 16 B 0_ C A P 0 10 P IO 0_ 3/ U S B _V B U S 14 P IO 0_ 4/ S C L 15 P IO 0_ 5/ S D A 16 P IO 0_ 6/ #U S B _C O N N E C T /S C K 22 P IO 0_ 7/ #C T S 23 P IO 0_ 8/ M IS O /C T 16 B 0_ M A T 0 27 P IO 0_ 9/ M O S I/C T 16 B 0_ M A T 1/ T R A C E _S W V 28 P IO 1_ 4/ A D 5/ C T 32 B 1_ M A T 3/ W A K E U P 40 P IO 1_ 5/ #R T S /C T 32 B 0_ C A P 0 45 P IO 1_ 6/ R X D /C T 32 B 0_ M A T 0 46 P IO 1_ 7/ T X D /C T 32 B 0_ M A T 1 47 P IO 1_ 8/ C T 16 B 1_ C A P 0 9 P IO 1_ 9/ C T 16 B 1_ M A T 0 17 P IO 1_ 10 /A D 6/ C T 16 B 1_ M A T 1 30 P IO 1_ 11 /A D 7 42 P IO 2_ 0/ #D T R 2 P IO 2_ 1/ #D S R 13 P IO 2_ 2/ #D C D 26 P IO 2_ 3/ #R I 38 P IO 2_ 4 18 P IO 2_ 5 21 P IO 2_ 6 1 P IO 2_ 7 11 P IO 2_ 8 12 P IO 2_ 9 24 P IO 2_ 10 25 P IO 2_ 11 /S C K 31 P IO 3_ 0 36 P IO 3_ 1 37 P IO 3_ 2 43 P IO 3_ 3 48 S W D /P IO 1_ 3/ A D 4/ C T 32 B 1_ M A T 2 39 T C K /S W C LK /P IO 0_ 10 /S C K /C T 16 B 0_ M A T 2 29 T D I/P IO 0_ 11 /A D 0/ C T 32 B 0_ M A T 3 32 T D O /P IO 1_ 1/ A D 2/ C T 32 B 1_ M A T 0 34 T M S /P IO 1_ 0/ A D 1/ C T 32 B 1_ C A P 0 33 U S B _D M 19 U S B _D P 20 V D D (3 V 3) /A V C C /V R E F 44 V D D IO 8 V S S 41 V S S IO 5 X T A LI N 6 X T A LO U T 7 U 1 U E X T -1 U E X T -2 U E X T -3 U E X T -4 U E X T -5 U E X T -6 U E X T -7 U E X T -8 U E X T -9 U E X T -1 0 D + D -G N D GND1 GND2 GND3GND4 ID V B U S U S B U S B C A D J/ G N D IN O U T V R 1 (3 .3 V )

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BOARD LAYOUT

POWER SUPPLY CIRCUIT

LPC-P1343 is power supplied +5V via USB, or via JTAG.

RESET CIRCUIT

LPC-P1343 reset circuit includes LPC1343 pin 3 (#RESET/PIO0_0), R18 (10k) and RESET button.

CLOCK CIRCUIT

Quartz crystal 12 MHz is connected to LPC1343 pin 6 (XTALIN) and pin 7 (XTALOUT).

JUMPER DESCRIPTION

3.3V_CORE_E

This jumper, when closed, enables microcontroller 3.3V power supply. Default state is closed.

3.3V(I/O)_E

This jumper, when closed, supplies 3.3 V voltage to LPC1343 pin 8 (VDDIO). Default state is closed.

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If BLD_E is closed during Reset and USB is connected to computer,

then removable disk will be appeared in My computer. The user can

create via IAR "*.bin" file, which

can be placed into the removable disk. After

this when jumper BLD_E is opened

during reset the

microcontroller will execute program stored in "*.bin" file.

Default state is open.

INPUT/OUTPUT

LED0 (red) connected via R-MAT1 to LPC1343 pin 36 (PIO3_0).

USBC (yellow) shows that USB is connected.

Power-on LED (red) – this LED shows that +3.3V is applied to the board.

User button with name BUT1 (USER) connected to LPC1343 pin 24 (PIO2_9).

User button with name BUT2 connected to LPC1343 pin 40 (WAKEUP).

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EXTERNAL CONNECTORS DESCRIPTION

UEXT

Pin # Signal Name

1 3.3V 2 GND 3 TXD 4 RXD 5 SCL 6 SDA 7 MISO 8 MOSI/SWV 9 SCK 10 CS

SWD

Pin # Signal Name Pin # Signal Name

1 3.3V 2 3.3V 3 NC 4 GND 5 NC 6 GND 7 SWD 8 GND 9 SWC 10 GND 11 pull-down 12 GND 13 MOSI/SWV 14 GND 15 NC 16 GND 17 pull-down 18 GND 19 +5V_JLINK 20 GND

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USB

Pin # Signal Name

1 USB_VBUS

2

U2D-3 U2D+

4 NC

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ORDER CODE

LPC-P1343

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assembled and tested board

How to order?

You can order to us directly or by any of our distributors.

Check our web www.olimex.com/dev for more info.

Revision history

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Disclaimer

The information in this document is provided in connection with Olimex products. No license, express or implied or otherwise, to any intellectual property right is granted by this document or in

connection with the sale of Olimex products.

Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material from except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous development and improvements. All particulars of the product and its use contained in this document are given by OLIMEX in good faith. However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded.

This document is intended only to assist the reader in the use of the product. OLIMEX Ltd. shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product.