MSP430 Seminar Questions and Answers
1)
Explain with a neat diagram, the architecture of msp430 microcontroller?Or
Explain the functional block diagram of the MSP430F2003/2013 microcontroller? Ans: The MSP430 is a 16-bit processor with a von Neumann architecture, designed for low-power applications by Texas instuments. The CPU is a reduced instruction set computer (RISC) address and data buses are 16 bits wide.
• The registers in the CPU are also all 16 bits wide and can be used interchangeably for either data or addresses.
• The MSP430 fits between traditional 8- and 16-bit processors. The 16-bit data bus and registers clearly define it as a 16-bit processor.
• On the other hand, it can address only 2^16 = 64KB of memory. The absence of pages or banks in the memory makes the MSP430 very simple to use. Another feature of the MSP430 that stems from its recent introduction is that it is designed with compilers in mind. Most small microcontrollers are now programmed in C, and it is important that a compiler can produce compact, efficient code.
• The MSP430 has 16 registers in its CPU, which enhances efficiency because they can be used for local variables, parameters passed to subroutines, and either addresses or data.
• This is a typical feature of a RISC, but unlike a “pure” RISC, it can perform
arithmetic directly on values in main memory. Microcontrollers typically spend much of their time on such operations.
• Watch dog timer: this is a safety feature, which resets the processor if the program becomes stuck in an infinite loop.
• The main blocks are linked by the memory address bus (MAB) and memory data bus (MDB).
• Random access memory: Used for variables. This always starts at address 0x0200 and upper limit depends on the size other RAM. The F2013 has 128B.
• Information memory: A 256B block of flash memory that is intended for storage of nonvolatile data.
• Code memory: Holds the program, including the executable code itself and any constant data. The F2013 has 2KB but the F2003 only 1KB
• The brownout protection comes into action if the supply voltage drops to a dangerous level. On the left is the CPU and its supporting hardware, including the clock
generator. The emulation, JTAG interface and Spy-Bi-Wire are used to communicate with a desktop computer when downloading a program and for debugging.
• Six blocks are shown for peripheral functions (there are many more in larger devices). All MSP430s include input/output ports, TimerA, and a watchdog timer, although the details differ. The universal serial interface (USI) and sigma–delta Analog-to-digital converter (SD16_A) are particular features of this device.
• The CPU is clocked by an internal, digitally controlled oscillator (DCO), which restarts in less than 1s in the latest devices. Therefore the MSP430 can wake from a standby mode rapidly, perform its tasks, and return to a low-power mode.
• SCLK, SDO, and SCL are used for the universal serial interface, which communicates with external devices using the serial peripheral interface (SPI) or inter-integrated circuit (I2C) bus.
• XIN and XOUT are the connections for a crystal, which can be used to provide an accurate, stable clock frequency.
• There are ground and power supply connections. Ground is labelled as VSS and is taken to define 0V. .
• RST is an active low reset signal. Active low means that it remains high near VCC for normal operation and is brought low near VSS to reset the chip
• The supply connection is VCC. For many years, the standard for logic was VCC =+5V but most devices now work from lower voltages and a range of 1.8–3.6V is specified for the F2013.
• The performance of the device depends on VCC. For example, it is unable to program the flash memory if VCC < 2.2V and the maximum clock frequency of 16MHz is available only if VCC ≥ 3.3V.
Central Processing Unit
• The central processing unit (CPU) executes the instructions stored in memory. It steps through the instructions in the sequence in which they are stored in memory until it encounters a branch or when an exception occurs (interrupt or reset).
• It includes the arithmetic logic unit (ALU), which performs computation, a set of 16 registers designated R0–R15 and the logic needed to decode the instructions and implement them.
• The CPU can run at a maximum clock frequency fMCLKof 16MHz in the
MSP430F2xx family and some newer MSP430x4xx devices, and 8MHz in the others. • It is built using static logic, which means that there is no minimum frequency of
operation: The CPU can be stopped and will retain its state until it is restarted. This is essential for low-power operation to be straightforward.
• The registers can hold a word of 16 bits.
• The first four registers have dedicated functions with alternative names, while the remaining 12 R4–R15 are working registers for general purposes.
• Either words or bytes can be written to the CPU registers but the behaviour for bytes is different from main memory: The destination is always the low byte and the high byte is cleared (reset to 0).
Stack Pointer (SP)
• When a subroutine is called the CPU must jump to the subroutine, execute the code there, and finish by returning to the instruction after the call.
• It must therefore keep track of the contents of the PC before jumping to the subroutine so that it can return afterward. This is done with a stack, which is also known as a last in–first out (LIFO) data structure.
• The MSP430 is conventional and allocates the stack in general-purpose RAM the stack is allocated at the top of RAM and grows down toward low addresses. The stack pointer holds the address of the top of thestack.
• The MSP430 has a last used or full descending stack, meaning that the SP contains the address of the most recently added word. (The alternative is a next available or empty descending stack, in which case the SP holds the address of the next available The Stack Pointer (SP/R1) is located in R1.
• The lsb of the stack pointer is hardwired to 0 in the MSP430, which guarantees that it always points to valid words.
• A byte is therefore wasted to preserve the alignment to words if a single byte is placed on the stack. The wasted byte is unchanged; it is not cleared as in a CPU register following a byte operation.
Operation of the stack in the MSP430F2013,Whose RAM lies from 0x0200 to 0x027F
Status Register (SR)
This contains a set of flags (single bits) , whose functions fall into three categories. The reserved bits are not used in the MSP430 but some have been up in the MSP430X to extend the length of addresses.
The carry flag c is set when the result of an arithmetic operation is too large to fit in the space allocated. i.e an overflow occurred. Example The hexadecimal sum 0x75 +0xc7+0Xc7=0x13c, where the result is too large to be held in a single byte .The processor would put 0x3c in the destination and set the carry bit to show that result had overflowed and that a 1 should be carried into the next more significant byte. The carry flag also takes part in rotations and shifts.
The zero flag Z is set when the result of an operation is 0.common application is check whether two values are equal.
The negative flag N is made equal to msb of the result, which indicates a negative number if the values are signed.
The signed overflow flag V is set when the result of a signed operation has over flowed, even though a carry may not be generated.
Enable Interrupts
Setting the general interrupt enable or GIE bit enables maskable interrupts, provided thatthe individual sources of interrupts have themselves been enabled.
Clearing the bit disables all mask able interrupts. There are also non-maskable interrupts, which cannot be disabled with GIE.
Control of Low-Power Modes
The CPUOFF, OSCOFF, SCG0, and SCG1 bits control the mode of operation of the MCU. All systems are fully operational when all bits are clear. Setting combinations of these bits puts the device into one of its low-power modes.
R2/R3: Constant Generator Registers (CG1/CG2) Depending of the source-register addressing modes (As) value, six commonly used constants can be generated without a code word or code memory access to retrieve them. This is a very powerful feature, which allows the implementation of emulated
instructions, for example, instead of implementing a core instruction for an increment, the constant generator is used.
R4 - R15: General–Purpose Registers
These general-purpose registers are used to store data values, address pointers, or index values and can be accessed with byte or word instructions.
The outside view –pin-out
Pin-out of the MSP430F2003 and F2013, taken from the data sheet.
VCC and VSS are the supply voltage and ground for the whole device (the analog and digital supplies are separate in the 16-pin package).
P1.0–P1.7, P2.6, and P2.7 are for digital input and output, grouped into ports P1 and P2.
TACLK, TA0, and TA1 are associated with Timer A; TACLK can be used as the clock input to the timer, while TA0 and TA1 can be either inputs or outputs.
A0−, A0+, and so on, up to A4±, are inputs to the analog-to-digital converter. It has four differential channels, each of which has negative and positive inputs. VREF is the reference voltage for the converter.
ACLK and SMCLK are outputs for the microcontroller’s clock signals. These can be used to supply a clock to external components or for diagnostic purposes. SCLK, SDO, and SCL are used for the universal serial interface, which communicates with external devices using the serial peripheral interface (SPI) or inter-integrated circuit (I2C) bus.
XIN and XOUT are the connections for a crystal, which can be used to provide an accurate, stable clock frequency.
RST is an active low reset signal. Active low means that it remains high near VCC for normal operation and is brought low near VSS to reset the chip. Alternativenotations to show the active low nature are _RST and /RST. NMI is the nonmaskable interrupt input, which allows an external signal to interrupt the normal operation of the program.
TCK, TMS, TCLK, TDI, TDO, and TEST form the full JTAG interface, used to Program and debug the device.
SBWTDIO and SBWTCK provide the Spy-Bi-Wire interface, an alternative to the Usual JTAG connection that saves pins.
2) List out the features,that make MSP430 suitable for lower power and portable applications.
The MSP430 is the simplest microcontroller in TI’s current portfolio. The letters MSP stand for mixed signal processor .several features make the MSP430 suitable for low-power and portable applications:
The CPU is small and efficient, with a large number of registers. 16 bit RISC CPU :
The CPU is small and efficient, with a large number of registers.
Instructions processing on either bits, bytes or words.
Compact core design reduces power consumption and cost.
Compiler efficient;
27 core instructions;
7 addressing modes;
Zero-power Brown-Out Reset (BOR).
The brownout protection comes into action if the supply voltage drops to a dangerous level. it is a circuit that forces the microprocessor to reset if there is a short
interruption of power.
On-chip analogue devices :
10/12/16-bit Analogue-to-Digital Converter (ADC).
12-bit dual Digital-to-Analogue Converter (DAC).
Comparator-gated timers.
Operational Amplifiers (OP Amps).
Supply Voltage Supervisor (SVS).
It is extremely easy to put the device into a low-power mode. No special instruction is needed: The mode is controlled by bits in the status register. The MSP430 is
awakened by an interrupt and returns automatically to its low-power mode after handling the interrupt.
There are several low-power modes, depending on how much of the device should remain active and how quickly it should return to full-speed operation.
There is a wide choice of clocks. Typically, a low-frequency watch crystal runs continuously at 32 KHz and is used to wake the device periodically The CPU is clocked by an internal, digitally controlled oscillator (DCO), which restarts in less than 1s in the latest devices. Therefore the MSP430 can wake from a standby mode rapidly, perform its tasks, and return to a low-power mode.
A wide range of peripherals is available, many of which can run autonomously without the CPU for most of the time.
.Many portable devices include liquid crystal displays, which the MSP430 can drive directly.
Some MSP430 devices are classed as application-specific standard products (ASSPs) and contain specialized analog hardware for various types of measurement.
3) Explain different addressing modes in msp430?
The MSP430 supports seven addressing modes for the source operand and four addressing modes for the destination operand. They are
• Register mode • Indexed mode • Symbolic mode • Absolute mode • Indirect register mode
• Indirect auto increment mode • Immediate mode
1) Register Mode
• Register mode operations work directly on the processor registers, R4 through R15, or on special function registers, such as the program counter or status register. They are very efficient in terms of both instruction speed and code space.
• Ex : MOV.W R4, R5
• Move (copy) the content (word) of source (register R4) to destination (register R5). Register R4 is not affected.
2) Indexed mode
The Indexed mode commands are formatted as X(Rn), where X is a constant and Rn is one of the CPU registers. The absolute memory location X+Rn is addressed.
• Indexed mode addressing is useful for applications such as lookup tables • Ex : MOV F000h(R5), R4
• Move (copy) the contents at source address (F000h +R5) to destination (register R4)
3) symbolic mode
• Symbolic mode allows the assignment of labels to fixed memory locations, so that those locations can be addressed. This is useful for the development of embedded programs.
• MOV XPT, YPT
• Move the content of source address XPT
• (x pointer) to the destination address YPT (y pointer). 4) Immediate mode
• Immediate mode is used to assign constant values to registers or memory locations. • MOV #E2h, R5
• Move the immediate constant E2h to the destination (register R5). 5) Indirect auto increment mode
Similar to indirect register mode, but with indirect auto increment mode, the operand is incremented as part of the instruction. The format for operands is @Rn+. This is useful for working on blocks of data.
• Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for byte instructions and by 2 for word instructions.
• Ex: MOV.W @R4+, R5
• Move the contents (word) of the source address (contents of R4) to the destination (register R5), then increment the value in register R4 to point to the next word. 6) Indirect register mode
• The data word addressed is located in the memory location pointed to by Rn. Indirect mode is not valid for destination operands, but can be emulated with the indexed mode format 0( Rn). Here Rn is used as a pointer to the operand.
• Mov.b @(R4), R5
• Move the content (byte) of the source address (contents of R4) to the destination (register R5). Register R4 is not modified
7) Absolute mode
Similar to Symbolic mode, with the difference that the label is preceded by “&”.The word following the instruction contains the absolute address. X is stored in the next word. Indexed mode X(SR) is used.
mov.b &XPT, &YPT Move the content (byte) of source address XPT to the destination address YPT.
4) Explain Memory map of MSP430?
All memory, including RAM, Flash/ROM, information memory, special function registers (SFRs), and peripheral registers are mapped into a single, contiguous address space.
The CPU is capable of addressing data values either as bytes (8 bits) or words (16 bits). Words are always addressed at an even address , which contain the least significant byte, followed by the next odd address, which contains the most significant byte
For 8-bit operations, the data can be accessed from either odd or even addresses, but for 16-bit operations, the data values can only be accessed from even addresses.
Memory map of the MSP430F2013
Special function registers: mostly concerned with enabling functions of some modules and enabling and signaling interrupts from peripherals and located at memory addresses from 0000h to 000Fh. SFRs must be accessed using byte instructions only.
Peripheral registers with byte access and peripheral registers with word access: Peripheral modules consist of all on-chip peripheral registers that are mapped into the address space. These modules can be accessed with byte or word instructions,
depending if the peripheral module is 8-bit or 16-bit respectively. The 16-bit
peripheral modules are located in the address space from addresses 0100 through to 01FFh and the 8-bit peripheral modules are mapped into memory from addresses 0010h through to 00FFh .it provides the main communication between the CPU and peripherals
Random access memory: Used for variables. This always starts at address 0x0200 and upper limit depends on the size other RAM. The F2013 has 128B.
Bootstrap loader: Contains a program to communicate using a standard serial protocol, often with the COM port of a PC.
Information memory: A 256B block of flash memory that is intended for storage of nonvolatile data.
Code memory: Holds the program, including the executable code itself and any constant data. The F2013 has 2KB but the F2003 only 1KB.
Interrupt and reset vectors: The interrupt vector table is mapped at the very end of memory space (upper 16 words of Flash/ROM), in locations 0FFE0h through to 0FFFEh (see the device-specific datasheets). The priority of the interrupt vector increases with the word address .Used to handle “exceptions”. When normal operation of the processor is interrupted or when the device is reset.
