IRF640, RF1S640, RF1S640SM

18A, 200V, 0.180 Ohm, N-Channel Power MOSFETs

These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits.

Formerly developmental type TA17422.

Features

• 18A, 200V

• r

= 0.180

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speed

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Symbol

Packaging

JEDEC TO-220AB JEDEC TO-263AB

JEDEC TO-262AA

Ordering Information

PART NUMBER PACKAGE BRAND

IRF640 TO-220AB IRF640

RF1S640 TO-262AA RF1S640

RF1S640SM TO-263AB RF1S640

NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S640SM9A.

G

D

S

GATE

DRAIN (FLANGE)

SOURCE DRAIN

DRAIN (FLANGE) GATE

SOURCE

DRAIN SOURCE DRAIN GATE

(FLANGE)

Data Sheet January 2002

Absolute Maximum Ratings

IRF640, RF1S640, RF1S640SM UNITS Drain to Source Breakdown Voltage (Note 1) . . . V_DS 200 V Drain to Gate Voltage (R_GS = 20kΩ) (Note 1) . . . V_DGR 200 V Continuous Drain Current . . . I_D

T_C = 100^oC . . . I_D

18 11

A A Pulsed Drain Current (Note 3) . . . I_DM 72 A Gate to Source Voltage . . . V_GS ±20 V Maximum Power Dissipation . . . P_D 125 W Dissipation Derating Factor . . . 1.0 W/^oC Single Pulse Avalanche Energy Rating (Note 4). . . E_AS 580 mJ Operating and Storage Temperature . . . T_J, T_STG -55 to 150 ^oC Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . T_L Package Body for 10s, See TB334. . . T_pkg

300 260

oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. T_J = 25^oC to 125^oC.

Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV_DSS I_D = 250µA, V_GS = 0V, (Figure 10) 200 - - V

Gate Threshold Voltage V_GS(TH) V_GS = V_DS, I_D = 250µA 2 - 4 V

Zero Gate Voltage Drain Current I_DSS V_DS = Rated BV_DSS, V_GS = 0V - - 25 µA

V_DS = 0.8 x Rated BV_DSS, V_GS = 0V, T_J = 125^oC - - 250 µA On-State Drain Current (Note 1) I_D(ON) V_DS > I_D(ON) x r_DS(ON)MAX, V_GS = 10V (Figure 7) 18 - - A

Gate to Source Leakage Current I_GSS V_GS = ±20V - - ±100 nA

Drain to Source On Resistance (Note 1) r_DS(ON) I_D = 10A, V_GS = 10V (Figures 8, 9) - 0.14 0.18 Ω

Forward Transconductance (Note 1) gfs ^VDS ≥ 10V, I_D = 11A (Figure 12) 6.7 10 - S

Turn-On Delay Time t_d(ON) V_DD = 100V, I_D ≈ 18A, R_GS = 9.1Ω, R_L = 5.4Ω, MOSFET Switching Times are Essentially Independent of Operating Temperature

- 13 21 ns

Rise Time t_r - 50 77 ns

Turn-Off Delay Time t_d(OFF) - 46 68 ns

Fall Time t_f - 35 54 ns

Total Gate Charge

(Gate to Source + Gate to Drain)

Q_g(TOT) V_GS = 10V, I_D ≈ 18A, V_DS = 0.8 x Rated BV_DSS (Figure 14) Gate Charge is Essentially Independent of Operating Temperature

I_G(REF) = 1.5mA

- 43 64 nC

Gate to Source Charge Q_gs - 8 - nC

Gate to Drain “Miller” Charge Q_gd - 22 - nC

Input Capacitance C_ISS V_DS = 25V, V_GS = 0V, f = 1MHz (Figure 11) - 1275 - pF

Output Capacitance C_OSS - 400 - pF

Reverse Transfer Capacitance C_RSS - 100 - pF

Internal Drain Inductance L_D Measured From the

Contact Screw on Tab to Center of Die

Modified MOSFET Symbol Showing the Internal Devices Inductances

- 3.5 - nH

Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die

- 4.5 - nH

Internal Source Inductance L_S Measured From the

Source Lead, 6mm (0.25in) from Header to Source Bonding Pad

- 7.5 - nH

Thermal Resistance Junction to Case R_θJC - - 1 ^oC/W

Thermal Resistance Junction to Ambient

R_θJA Free Air Operation, IRF640 - - 62 ^oC/W

R_θJA RF1S640SM Mounted on FR-4 Board with Minimum Mounting Pad

- - 62 ^oC/W

L_S L_D

G

D

S

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I_SD Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode

- - 18 A

Pulse Source to Drain Current (Note 2)

I_SDM - - 72 A

Source to Drain Diode Voltage (Note 2) V_SD T_J = 25^oC, I_SD = 18A, V_GS = 0V, (Figure 13) - - 2.0 V

Reverse Recovery Time t_rr T_J = 25^oC, I_SD = 18A, dI_SD/dt = 100A/µs 120 240 530 ns

Reverse Recovery Charge Q_RR T_J = 25^oC, I_SD = 18A, dI_SD/dt = 100A/µs 1.3 2.8 5.6 µC

NOTES:

2. Pulse Test: Pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive Rating: Pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. V_DD = 50V, starting T_J = 25^oC, L = 3.37mH, R_G = 25Ω, peak I_AS = 18A.

Typical Performance Curves

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE G

D

S

0 50 100 150

0

T_C, CASE TEMPERATURE (^oC)

POWER DISSIPATION MULTIPLIER

0.2 0.4 0.6 0.8 1.0 1.2

8

4

0

25 50 75 100 125 150

16

ID, DRAIN CURRENT (A)

T_C, CASE TEMPERATURE (^oC) 20

12

t_P, RECTANGULAR PULSE DURATION (s)

10

ZθJC, TRANSIENT THERMAL IMPEDANCE (oC/W)

10^-3 10^-2 10^-1 1

10^-5 10^-4

10

0.01 0.1

NOTES:

DUTY FACTOR: D = t₁/t₂ PEAK T_J = P_DM x Z_θJC + T_C

P_DM

t₁ t₂

0.001 1

SINGLE PULSE 0.1

0.02 0.2 0.5

0.01 0.05

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

V_DS, DRAIN TO SOURCE VOLTAGE (V) 1 10

10

1

ID, DRAIN CURRENT (A

) 100

100 T_C = 25^oC

SINGLE PULSE

1000 OPERATION IN THIS AREA MAY BE LIMITED BY r_DS(ON)

DC 100µs 10µs

1ms

10ms T_C = 25^oC

1000 T_J = MAX RATED

V_DS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

0

0 12 24 36 48

6 12 18 24 30

60 7V

6V

5V 4V 10V

8V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

0 6

0 1.0 2.0 3.0 5.0

12 18

ID, DRAIN CURRENT (A)

V_DS, DRAIN TO SOURCE VOLTAGE (V) V_GS = 6V 24

4.0 V_GS = 7V

30 V_GS = 8V

V_GS = 10V

V_GS = 5V V_GS = 4V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

0 2 4 6 8 10

0.1 1 10

ID, DRAIN CURRENT (A)

V_GS, GATE TO SOURCE VOLTAGE (V) 100

150^oC

25^oC PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX V_DS ≥ 50V

0 0.6 0.9 1.2

15 30 45 60

rDS(ON), DRAIN TO SOURCE

I_D, DRAIN CURRENT (A)

75 1.5

0

0.3 V_GS= 10V

V_GS = 20V

ON RESISTANCE (Ω)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

NORMALIZED DRAIN TO SOURCE

3.0

1.8

1.2

0.6

0

-60 -40 -20 0 20 40 60

T_J, JUNCTION TEMPERATURE (^oC)

100 120 140 160 2.4

80

ON RESISTANCE

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V_GS = 10V, I_D = 18A

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

1.05

0.95

0.85

0.75

-60 -40 -20 0 20 40 60

T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE

100 120 140 160 1.15

80

I_D = 250µA 3000

600

0

1 10 100

C, CAPACITANCE (pF)

1800

V_DS, DRAIN TO SOURCE VOLTAGE (V) 2400

1200

C_ISS

C_OSS

C_RSS

C_ISS = C_GS + C_GD C_RSS = C_GD C_OSS ≈ CDS + C_GD V_GS = 0V, f = 1MHz

25^oC

I_D, DRAIN CURRENT (A)

gfs, TRANSCONDUCTANCE (S)

0

0 6 12 18 24

3 6 9 12 15

30 150^oC

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

0 0.4 0.8 1.2 1.6 2.0

1 10 100

ISD, SOURCE TO DRAIN CURRENT (A)

V_SD, SOURCE TO DRAIN VOLTAGE (V) 1000

25^oC 150^oC

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

Q_g, GATE CHARGE (nC)

VGS, GATE TO SOURCE VOLTAGE (V)

0

0 15 30 45 60

4 8 12 16 20

75 I_D = 28A

V_DS = 100V

V_DS = 160V V_DS = 40V

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS t_P

V_GS

0.01Ω L

I_AS

+ - V_DS

V_DD R_G

DUT VARY t_P TO OBTAIN

REQUIRED PEAK I_AS

0V

V_DD V_DS BV_DSS

t_P

I_AS

t_AV 0

V_GS

R_L

R_G

DUT +

-

V_DD

t_ON t_d(ON)

t_r 90%

10%

V_DS

90%

10%

t_f t_d(OFF)

t_OFF

90%

50%

50%

10% PULSE WIDTH

V_GS 0

0

0.3µF 12V

BATTERY 50kΩ

V_DS S

DUT D

G

I_G(REF) 0

(ISOLATED V_DS

0.2µF

CURRENT REGULATOR

I_D CURRENT SAMPLING I_G CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR SAME TYPE AS DUT

Q_g(TOT) Q_gd Q_gs

V_DS

0

V_GS V_DD

I_G(REF)

0

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As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

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