Gating Signal Generation and Hardware
Implementation of Multi-Level Inverter Fed
Induction Motor by SVPWM Method Using
µ- Controller
B. Muralidhara1
1Assistant professor, Department of Electrical and Electronics Engineering, BMSIT, Yelahanka, Bangalore, Visvesvaraya Technological University, Belgaum, India.
A. Ramachandran2
2Principal, Vemana Institute of Technology, Koramangala, Bangalore, Visvesvaraya Technological University, Belgaum, India.
H.D. Kattimani1
1Assistant Professor, Department of Electrical and Electronics Engineering, BMSIT, Yelahanka, Bangalore, Visvesvaraya Technological University, Belgaum, India.
M. Channa Reddy2
2Director, Vemana Institute of Technology, Koramangala, Bangalore, Visvesvaraya Technological University, Belgaum, India
Abstract: Multilevel power conversion technology is a very rapidly growing area of power electronics with
good potential for further development. Multilevel voltage-fed inverters with space vector pulse width modulation strategy have gained importance in high power high performance industrial drive applications. This paper proposes a simplified Space Vector PWM Algorithm for a NPC three-level inverter fed induction motor drive. In this work, a three-level inverter using space vector modulation strategy has been developed and gating signals have been generated using PIC µ- controller and it is added with additional auxiliary circuit and is tested with induction motor load. The workability of the Three level Inverter has given satisfactory results for a (low voltage) 15% of the input supply voltage.
Key words : Space Vector PWM (SVPWM), Multilevel Inverters (MLI), Three-Level Inverters, Neutral Point Clamped (NPC), µ- controller.
I. Introduction
With the development of power electronic devices like the insulated gate bi-polar transistor (IGBT), the power MOSFET and the advances in microcontrollers, the ac induction motor is becoming popular in variable speed drives with PWM drive circuits[5]-[15]. Since the rise time and fall time of the IGBT’s are less than 200nsecs, the dissipation loss across the device becomes very less, which increases the performance of the device and circuit. However due to the fast switching action of the device the dv/dt of the inverter output becomes large. This high dv/dt voltage transition coupled with parasitic stray capacitance in the system causes high frequency line to ground current or common mode voltage and current introducing large EMI in the system. The schematic circuit diagram of the power electronic conversion system for the three phase induction motor is as shown in fig.1.
Vdc CONTROLLER SVPWM N TX1 3-PHASE SUPPLY INDUCTION MOTOR D1 Sc3 Sa1 D3 1 2 D17 Sa1 Sc2 D11 Vdc/2 D4 D10 D12 D2 D6 Sa4 D8
3- Phase Induction Motor
1 2 Vdc D7 Sa1 D13 Sa3 D9 D16 Sc4 D15 Sa2 Vdc/2 0 C2 D18 D5 D1 C1 1 2 D14 .
A three level inverter known as “neutral point clamped” Inverterconsists of two capacitors in series and uses center tap as the neutral [2]. Each phase leg of three level inverter has two pairs (2(m-1)) switching devices, (m=level, here m=3). The center of each device pair is clamped to neutral through two clamping (m-1) diodes. The wave form obtained from a three-level inverter is a quasi –square output. The main reason for this popularity is that the output voltage waveforms in multilevel inverters can be generated at low switching frequencies with high efficiency and low distortion and large voltage between the series devices is easily shared. Space vector PWM (SVPWM) technique is one of the most popular techniques gained interest recently [5], [25], [26],[27]. This technique results in higher magnitude of fundamental output voltage available as compared to sinusoidal PWM. However, SVPWM algorithm used in three-level inverters is more complex because of large number of inverter switching states [3]-[19]. One of the advantages of multilevel inverters is that the voltage stress on each switching device is reduced. In addition, multilevel waveforms feature have less harmonic content compared to two level waveforms operating at the same switching frequency [4],[22],[23],[24]. In this paper, experimentation of a multilevel inverter using NPC inverters with separated DC sources has been performed with induction motor load. In multilevel inverters, it is easy to reach high voltage levels in high power applications with lower harmonic distortion and switching frequency, which is very difficult to get this performance with conventional two level inverter.
II. Generation of SVPWM for Neutral Point Clamped Three level Inverter
System Description: As shown in Fig. 2, the studied system is constituted of a DC supply, and a three-level voltage
inverter bridge based on MOSFET’s (IBGTs)/Diodes pairs. Each arm contains four MOSFET/IGBTs, four anti-parallel diodes and two neutral clamping diodes. The inverter is feeding an AC load Induction Motor.
Functioning: The three-level voltage source inverter outputs three-level voltages (–Vdc/2, 0, Vdc/2) depending on
the DC-bus voltage Vdc and the variable state Ci, where 'i' is the phase indicator (i = a, b, c). Si1, Si2, Si3, Si4 are the switches of one leg, and Vio is the phase-to-fictive middle point voltage.
Fig.1. The schematic of the power electronic conversion system for induction motor.
Fig.3 Space vector diagram of Three-Level Inverter. Table.1. Definition of Inverter states.
The functioning principle is displayed on Table 1. Fig.3. represents the space vector diagram of Three-Level Inverter. In order to obtain the desired three-level voltages, the converter must ensure complementarities between the pairs of switches: (Si1,Si3) and (Si2,Si4). In principle all modulation schemes aim to create trains of switched pulses which have the same fundamental volt- second average (the integral of the voltage waveform over time) as a target reference waveform at any instant. The major difficulty with these trains of switched pulses is that they also contain unwanted harmonic components which should be minimized. Hence for any PWM scheme, a primary objective can be identified which is to calculate the inverter switch ON times which create the desired (low frequency) target output voltage or current [1]-[18]. Having satisfied this primary objective, the secondary objective for a PWM strategy is to determine the most effective way of arranging the switching processes to minimize unwanted harmonic distortion, switching losses or any other specified performance criterion The pulse pattern arrangement of SVM1 (Right aligned sequence) is used. The right aligned sequence is the simple way to synthesize the output voltage vector is to turn ON all the bottom (or top) switches at the beginning of switching cycle and then to turn them OFF sequentially so that the zero vector is split between them equally which is similar to Two- Level inverter [12-16]. The switching time T1, T2, T0 Can be calculated based on volt-second integral of vref
III. Hardware Implementation
This section presents the hardware implementation in the laboratory. There are several steps involved in implementing the hard ware This (Fig.1.) involves the Line impedance stabilization network (LISN), converter system to convert the supply voltage and currents to DC quantities. Then the inversion stage converts the DC voltage to variable voltage frequencies, as demanded by the speed of the motor. These two stages are connected by a DC link which is generally a filter capacitors. In majority of applications the DC to AC inversion stage is a voltage source inverter (VSI). Following steps involved in implementing the hard ware for gating signal generation which can be represented in the block diagram shown in Fig4. Here 5 V DC supply is given to PIC µ- controller and the Timer circuit , the output of the µ- controller is fed to interfacing circuit, than to the opto- isolator circuit , which is
for the isolation purpose , then the output of this is fed to the gate of each switching device, is a semiconductor device that allows signals to be transferred between circuits or systems, while keeping those circuits or systems electrically isolated from each other. Opto- isolators are used in a wide variety of communications, control, and monitoring systems. The Three- Level Inverter Bridge is as shown in fig.5. Here 2Sk962 power MosFETs are
used along with anti parallel diodes.
Definition of Inverter States
State Switch position Pole
voltage w,r,t, Vdc Sa1 Sa2 Sa3 Sa4
1 ON ON OFF OFF Vdc/2
0 OFF ON ON OFF 0
CONTROLLER
5 V
DC
0
SWITCHING
DEVICE
0
FACING
CIRCUIT
ISOLATOR
CIRCUIT
FACING
CIRCUIT
TIMER
IV. Experimental Results
The proposed Three Level inverter is implemented with MOSFET’s as switching elements and is tested with a 370 watts three phase 440 volts squirrel cage induction motor. The open loop V/f controller based on multilevel space vector PWM is implemented on PIC16F877 microcontroller. Gating signals are generated for 40 hertz which is stored in 16 channel Agilent make Digital storage oscilloscope which is as shown in fig. 6.The phase to fictive middle point voltage (pole voltages) Vao, Vbo, Vco is as shown in fig.7. which is recorded for 20ms/Div.Fig.8 gives the output of the Three-level inverter bridge which is operated at 60 volts supply through a three phase autotransformer, channel 1,2,3 represents the phase voltage applied to an induction motor, (recorded 20ms/Div). Fig.9. ch1 gives the phase voltage, ch2 gives the line voltage, ch3 gives star point stator of induction motor to general ground and ch4 gives vector sum of phase currents.
Fig.5.Experimental setup of Three level inverter Fig.4. Black diagram of generation of
gating signal to control Speed of I.M
V. Conclusion
The space vector pulse width modulation pulses for Three level inverter have been generated using the PIC μ -Controller. Here the pulses are generated to get 40Hz a.c supply output from the inverter bridge. The signal generated has been suitably added with high frequency pulses, after Opto - isolation the same has been monitored and the wave forms are shown in the figs. 6 and 7. For the experimental verification of the pulses, the same has been checked with the inverter bridge by applying small voltage of say 60volts ac input and it gives the satisfactory results which are shown in the fig. 8 and 9. Further suitable snubber circuit has to be designed to apply higher voltage. The same methodology can also be used for the closed loop system with some modifications and the same has not been dealt here Hence it is concluded that the SVPWM pulses can be generated using the PIC μ-Controller for multilevel inverter.
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