12.
1.
,
.
,
1
.
.
Flip-Flops
:
,
Flip-Flops
,
Flip – Flop
.
(
MOD).
.
-8
8
,
0
7 (
000
111
).
1.
n
Flip-Flops
.
n
Flip-Flops
: 2
n.
2
n,
Modulo
.
-5)
0-4 (
000-100),
(
-11)
0-10
0000-1010)
.
A B C
A B C
A B C
0
0 0 0
0 0 0
0 0 0
1
0 0 1
0 0 1
0 0 1
2
0 1 0
0 1 0
0 1 0
3
0 1 1
0 1 1
0 1 1
4
1 0 0
1 0 0
1 0 0
5
MOD-5
1 0 1
1 0 1
6
MOD-6
1 1 0
7
MOD-7
8
9
A B C
A B C
A B C
0
0 0 0
0 0 0 0
0 0 0 0
1
0 0 1
0 0 0 1
0 0 0 1
2
0 1 0
0 0 1 0
0 0 1 0
3
0 1 1
0 0 1 1
0 0 1 1
4
1 0 0
0 1 0 0
0 1 0 0
5
1 0 1
0 1 0 1
0 1 0 1
6
1 1 0
0 1 1 0
0 1 1 0
7
1 1 1
0 1 1 1
0 1 1 1
8
MOD-8
1 0 0 0
1 0 0 0
9
MOD-9
1 0 0 1
MOD-10
1.
.
:
1.
(
- )
.
2.
n (
2
n)
FF .
. JK SR
PETr / NETr (
) (
).
3.
(
)
FF (
).
4.
FF,
,
’
,
. (
,
FF).
5.
(
)
FF.
2.
-8
JK-FF
NETr
-8 JK-FF
NETr
,
FF
1 0
).
.
:
1.
-8 (
0-7).
2.
2
n= 8
n = 3 FF ( JK-FF
NETr).
3.
FF.
/
(
.)
(
.)
FF
A B C A
+B
+C
+J
AK
AJ
BK
BJ
CK
C0
0 0 0 0 0 1 0
0
1
1
0 0 1 0 1 0 0
1
1
2
0 1 0 0 1 1 0
0 1
3
0 1 1 1 0 0 1
1
1
4
1 0 0 1 0 1
0 0
1
5
1 0 1 1 1 0
0 1
1
6
1 1 0 1 1 1
0
0 1
7
1 1 1 0 0 0
1
1
1
2.
-8.
FF
FF
000
001).
(CLK)
FF
:
J
A=0, K
A=X
A-FF
J
B=0, K
B=X
B-FF
J
C=1, K
C=X
C-FF
‘0’
‘1’.
.
4.
FF.
,
’
,
. (
,
).
.
FF
.
:
.
AB
00 01 11 10 AB
00 01 11 10
C
0
X X
C
0
X X
1
1 X X
1
X X 1
J
A= B.C
K
A= B.C
AB
00 01 11 10 AB
00 01 11 10
C
0
X X
C
0
X
X
1
1 X X 1
1
X 1 1 X
J
B= C
K
B= C
AB
00 01 11 10 AB
00 01 11 10
C
0
1 1 1 1
0
C
X X X X
1
X X X X
1
1 1 1 1
J
C= 1
K
C= 1
5.
(
.)
FF. (
1).
J K Q Q P A J K Q Q P B J K Q Q P C H 1 CP H 1 4 2 1 and1.
-8 JK-FF.
3.
0,7,4,2,5,3 (
) JK-FF
NETr
0,7,4,2,5,3
) JK-FF
NETr.
.
/
.
.
FF
A B C A
+B
+C
+J
AK
AJ
BK
BJ
CK
C0
0 0 0 1 1 1 1 1 1
7
1 1 1 1 0 0
0
1
1
4
1 0 0 0 1 0
1 1 0
2
0 1 0 1 0 1 1
1 1
5
1 0 1 0 1 1
1 1
0
3
0 1 1 0 0 0 0 X
1 X 1
1
0 0 1
D D D D D D
6
1 1 0
D D D D D D
3.
0,7,4,2,5,3.
1.
,
0,7,4,2,5,3.
2.
2
n7 ( 2
n)
n = 3 FF (
JK-FF
NETr).
3.
FF.
4.
FF.
,
’
.
1,6
. (
).
.
FF
.
FF
.
AB
00 01 11 10 AB
00 01 11 10
C
0
1 1 D X
0
C
X X D 1
1
D X D
1
D X
1
J
A= C’
K
A= B’
AB
00 01 11 10 AB
00 01 11 10
C
0
1 X D 1
0
C
X 1 D X
1
D X X 1
1
D 1 1 1
J
B= 1
K
B= 1
AB
00 01 11 10 AB
00 01 11 10
C
0
1 1 D
C
0
X X D X
1
D X X X
1
D
1
1
J
C= A’
K
C= B
5.
(
.)
FF. (
).
4.
1.
0,7,4,2,5,3 JK –
FLIP-FLOP
2.
mod-11 JK Flip-Flops.
3.
0, 6, 3, 7, 1, 2, 5 JK
Flip-Flops.
4.
MOD-8
-,
State
Editor
.
.
Finite State Machine (FSM) Editor
.
1
FSM.
1.
File New
,
2
.
CLK
reset
.
q
3bits
.
2.
3.
FSM
Editor,
(S1,…,S8)
,
3.
FSM Editor,
VHDL,
1.
vhd
,
File
Export
(VHDL code).
-- Generated : 11/16/2013 5:51:49 PM library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity SAMPLE is port ( reset: in std_logic; CLK: in std_logic;q: out std_logic_vector ( 2 downto 0 ));
end;
architecture SAMPLE_arch of SAMPLE is
-- SYMBOLIC ENCODED state machine: SMachine0 type SMachine0_type is (S1,S2,S3,S4,S5,S6,S7,S8); signal SMachine0: SMachine0_type := S1;
begin
-- concurrent signals assignments
--- Machine: SMachine0 ---SMachine0_machine: process (CLK) begin if reset='1' then SMachine0 <= S1;
elsif CLK'event and CLK = '1' then
-- Set default values for registered outputs/signals and for variables
case SMachine0 is when S1 => q<="000";
if reset='0' then SMachine0 <= S2; end if;
when S2 => q<="001";
if reset='1' then SMachine0 <= S1; elsif reset='0'then
SMachine0 <= S3; end if;
when S3 => q<="010";
if reset='1' then SMachine0 <= S1; elsif reset='0'then
SMachine0 <= S4; end if;
when S4 => q<="011";
if reset='1' then SMachine0 <= S1; elsif reset='0'then
SMachine0 <= S5; end if;
when S5 => q<="100";
if reset='1' then SMachine0 <= S1; elsif reset='0'then
SMachine0 <= S6; end if;
when S6 => q<="101";
if reset='1' then SMachine0 <= S1; elsif reset='0'then
SMachine0 <= S7; end if;
when S7 => q<="110";
if reset='1' then SMachine0 <= S1; elsif reset='0'then
SMachine0 <= S8; end if;
when S8 => q<="111";
if reset='1' then SMachine0 <= S1; elsif reset='0'then SMachine0 <= S1; end if; when others => null; end case; end if; end process; end SAMPLE_arch;
1.
Tools
New Macro Wizard.
4.
Macro Name
,
Counter 1.
From File
counter1.vhd,
VHDL
.
4.
5.
Next,
5
TSM
.
Save.
6
.
Insert
,
7.
6.
7.
8.
Pin
Bus Pin
Meters
Voltage Pin,
q
3bits.
Counter1 clk reset q U1 Counter18.
VHDL
.
bit
.
FSM Editor
Counter1
File
Edit Ports.
9,
bits
q2, q1, q0.
1.
9.
S1
S2
S3
S4
q2<='0'
;
q1<='0'
;
q0<='0'
;
q2<='0'
;
q1<='0'
;
q0<='1'
;
q2<='0'
;
q1<='1'
;
q0<='0'
;
q2<='0'
;
q1<='1'
;
q0<='1'
;
S5
S6
S7
S8
q2<='1'
;
q1<='0'
;
q0<='0'
;
q2<='1'
;
q1<='0'
;
q0<='1'
;
q2<='1'
;
q1<='1'
;
q0<='0'
;
q2<='1'
;
q1<='1'
;
q0<='1'
;
1.
VHDL
Counter1b.vhd
,
Tools
New Macro
VHDL.
10
Analysis
Digital VHDL Simulation,
11.
10.
11.
VHDL
.
IF
1-
(0-->9-->0).
bit
(clk)
4-bit
(digit).
IF.
temp
4 Flip-Flops
4-bit
.
LIBRARY ieee; USE ieee.std_logic_1164.all; Counter1 clk reset q U1 Counter1 H L Reset clk 1k q H L Reset clk 1k Counter1b reset clk q0 q2 q1 U2 Counter1b q2 q1 q0 q2 q1 q0 T Time (s) 0.00 2.00m 4.00m 6.00m 8.00m q2 L H q1 L H q0 L HENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
ARCHITECTURE counter OF counter IS BEGIN
count: PROCESS(clk)
VARIABLE temp :
INTEGER RANGE 0 TO 10; BEGIN
IF (clk'EVENT AND clk='1') THEN temp := temp + 1;
IF (temp=10) THEN temp := 0; END IF;
END IF;
digit <= temp; END PROCESS count; END counter;
reset
temp
toy digit).
temp
4-bit
.
.
WAIT UNTIL
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY counter IS PORT (clk : IN STD_LOGIC;digit : OUT INTEGER RANGE 0 TO 9); END counter;
ARCHITECTURE counter OF counter IS BEGIN
PROCESS -- no sensitivity list
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
temp := temp + 1;
IF (temp=10) THEN temp := 0; END IF; digit <= temp; END PROCESS; END counter;
,
7 segment display (SSD)
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY counter IS PORT (clk, reset : IN STD_LOGIC;digit1, digit2 : OUT
STD_LOGIC_VECTOR (6 DOWNTO 0)); END counter;
ARCHITECTURE counter OF counter IS BEGIN PROCESS(clk, reset) VARIABLE temp1: INTEGER RANGE 0 TO 10; VARIABLE temp2: INTEGER RANGE 0 TO 10; BEGIN IF (reset='1') THEN temp1 := 0; temp2 := 0;
ELSIF (clk'EVENT AND clk='1') THEN temp1 := temp1 + 1; IF (temp1=10) THEN temp1 := 0; temp2 := temp2 + 1; IF (temp2=10) THEN temp2 := 0; END IF; END IF; END IF; ---- BCD to SSD conversion:
---CASE temp1 IS
WHEN 0 => digit1 <= "1111110"; --7E WHEN 1 => digit1 <= "0110000"; --30 WHEN 2 => digit1 <= "1101101"; --6D WHEN 3 => digit1 <= "1111001"; --79 WHEN 4 => digit1 <= "0110011"; --33 WHEN 5 => digit1 <= "1011011"; --5B WHEN 6 => digit1 <= "1011111"; --5F WHEN 7 => digit1 <= "1110000"; --70 WHEN 8 => digit1 <= "1111111"; --7F WHEN 9 => digit1 <= "1111011"; --7B WHEN OTHERS => NULL;
END CASE;
CASE temp2 IS
WHEN 0 => digit2 <= "1111110"; --7E WHEN 1 => digit2 <= "0110000"; --30 WHEN 2 => digit2 <= "1101101"; --6D WHEN 3 => digit2 <= "1111001"; --79 WHEN 4 => digit2 <= "0110011"; --33 WHEN 5 => digit2 <= "1011011"; --5B WHEN 6 => digit2 <= "1011111"; --5F WHEN 7 => digit2 <= "1110000"; --70 WHEN 8 => digit2 <= "1111111"; --7F WHEN 9 => digit2 <= "1111011"; --7B WHEN OTHERS => NULL;
END CASE; END PROCESS; END counter;
FOR/LOOP:
FOR i IN 0 TO 5 LOOP
x(i) <= enable AND w(i+2); y(0, i) <= w(i); END LOOP;
FOR/LOOP (
GENERATE),
.
.
FOR I IN 0 TO CHOICE
LOOP,
CHOICE
(
),
.
WHILE/LOOP:
WHILE (i < 10) LOOPWAIT UNTIL clk'EVENT AND clk='1'; (other statements) END LOOP;
EXIT:
, EXIT
,
(
,
LOOP
).
«0»
:
FOR i IN data'RANGE LOOP CASE data(i) IS
WHEN '0' => count:=count+1; WHEN OTHERS => EXIT;
END CASE; END LOOP;
NEXT:
NEXT
LOOP
i=skip:
FOR i IN 0 TO 15 LOOP NEXT WHEN i=skip;-- jumps to next iteration (...)
END LOOP;
Carry Ripple Adder
generic,
bits.
8bit
.
FOR/LOOP,
IF.
--Solution 1: Generic, with VECTORS
LIBRARY ieee;
USE ieee.std_logic_1164.all; ENTITY adder IS
GENERIC (length : INTEGER := 8);
PORT ( a, b: IN
STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cin: IN STD_LOGIC; s: OUT
STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cout: OUT STD_LOGIC); END adder;
ARCHITECTURE adder OF adder IS BEGIN
VARIABLE carry :
STD_LOGIC_VECTOR (length DOWNTO 0); BEGIN
carry(0) := cin;
FOR i IN 0 TO length-1 LOOP
s(i) <= a(i) XOR b(i) XOR carry(i); carry(i+1) := (a(i) AND b(i)) OR (a(i) AND
carry(i)) OR (b(i) AND carry(i)); END LOOP; cout <= carry(length); END PROCESS; END adder; --Solution 2: non-generic, --with INTEGERS LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY adder IS PORT ( a, b: IN INTEGER RANGE 0 TO 255; c0: IN STD_LOGIC;
s: OUT INTEGER RANGE 0 TO 255; c8: OUT STD_LOGIC);
END adder;
ARCHITECTURE adder OF adder IS BEGIN PROCESS (a, b, c0) VARIABLE temp : INTEGER RANGE 0 TO 511; BEGIN IF (c0='1') THEN temp:=1; ELSE temp:=0; END IF; temp := a + b + temp; IF (temp > 255) THEN c8 <= '1'; temp := temp---256; ELSE c8 <= '0'; END IF; s <= temp; END PROCESS; END adder;
(Bad clocking)
(
) (
).
. CPLDs)
flip-flop
.
«signal
does not hold value after clock edge»
.
(
).
:
PROCESS (clk) BEGINIF(clk'EVENT AND clk='1') THEN counter <= counter + 1;
ELSIF(clk'EVENT AND clk='0') THEN counter <= counter + 1; END IF; ... END PROCESS;
,
,
counter
.
,
.
EVENT
.
IF(clk'EVENT AND clk='1')
,
IF(clk'EVENT),
(
.
AND clk='1)
: clock not locally stable.
,
.
:
PROCESS (clk) BEGIN IF(clk'EVENT) THEN counter := counter + 1; END IF; ... END PROCESS;PROCESS
clk
,
.
,
,
.
,
,
.
,
.
,
PROCESS,
.
.
:
PROCESS (clk) BEGIN counter := counter + 1; ... END PROCESS;counter
clk (
),
«ignored unnecessary
pin clk».
,
,
.
,
.
PROCESS (clk) BEGINIF(clk'EVENT AND clk='1') THEN
x <= d; END IF; END PROCESS; ---PROCESS (clk) BEGIN
IF(clk'EVENT AND clk='0') THEN
y <= d; END IF; END PROCESS;
VARIABLE
SIGNAL
0-7
.
VARIABLE
.
SIGNAL
.
:
--Solution 1: With a VARIABLEENTITY counter IS
PORT ( clk, rst: IN BIT;
count: OUT INTEGER RANGE 0 TO 7); END counter;
ARCHITECTURE counter OF counter IS BEGIN
PROCESS (clk, rst)
VARIABLE temp: INTEGER RANGE 0 TO 7;
BEGIN
IF (rst='1') THEN temp:=0;
ELSIF (clk'EVENT AND clk='1') THEN
temp := temp+1; END IF; count <= temp; END PROCESS; END counter;
1
VARIABLE
.
(clk)
.
:
-- Solution 2: With SIGNALS only
ENTITY counter IS
PORT ( clk, rst: IN BIT;
count: BUFFER INTEGER RANGE 0 TO 7);
END counter;
ARCHITECTURE counter OF counter IS BEGIN
PROCESS (clk, rst) BEGIN
IF (rst='1') THEN
count <= 0;
ELSIF (clk'EVENT AND clk='1') THEN
count <= count + 1; END IF; END PROCESS; END counter;
2,
SIGNALS.
,
, count
BUFFER,
(
).
SIGNAL
VARIABLE
.
std_logic_1164
STD_LOGIC
.
flip-flops
(
3bit
count).
4bit
4bit
.
.
Clear Count
1
0
0
0
1
VHDL
.
USE
IEEE.STD_LOGIC_UNSIGNED.ALL
STD_LOGIC_VECTOR.
value
.
clear
1,
value
0000
OTHERS =>
‘0’.
,
count
1, value
1
.
count
Q
Q<=value,
PROCESS.
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to -- add STD_LOGIC_VECTORs ENTITY counter IS PORT ( Clock: IN STD_LOGIC; Clear: IN STD_LOGIC; Count: IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END counter;ARCHITECTURE Behavioral OF counter IS
SIGNAL value:
STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS (Clock, Clear)
BEGIN
IF Clear = '1' THEN
value <= (OTHERS => '0');
-- 4-bit vector of 0, same as "0000" ELSIF (Clock'EVENT AND Clock='1') THEN IF Count = '1' THEN value <= value + 1; END IF; END IF; END PROCESS; Q <= value; END Behavioral;
-.
.
Clear Count Down
1
0
0
0
1
0
0
1
1
VHDL
.
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY udcounter IS PORT ( Clock: IN STD_LOGIC;Clear: IN STD_LOGIC; Count: IN STD_LOGIC; Down: IN STD_LOGIC;
Q: OUT INTEGER RANGE 0 TO 15);
END udcounter;
ARCHITECTURE Behavioral OF udcounter IS
BEGIN
PROCESS (Clock, Clear)
VARIABLE value:
INTEGER RANGE 0 TO 15;
BEGIN
IF (Clear = '1') THEN
value := 0;
ELSIF (Clock'EVENT AND Clock='1') THEN IF (Count = '1') THEN IF (Down = '0') THEN value := value + 1; ELSE value := value - 1; END IF; END IF; END IF; Q <= value; END PROCESS; END Behavioral;