IS MECHTRON 3TB4 Final

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DAY CLASS

MECHTRON 3TB4

Embedded Systems Design II

DURATION OF EXAMINATION:

_{3 hours}

MCMASTER UNIVERSITY FINAL EXAMINATION

Examiner: Franjo Plavec

April 22, 2008

THIS EXAMINATION PAPER INCLUDES

₁₈

PAGES AND

₆

QUESTIONS. YOU ARE RESPONSIBLE FOR ENSURING THAT YOUR COPY OF THE PAPER IS COMPLETE. BRING ANY DISCREPANCY TO THE ATTENTION OF YOUR INVIGILATOR.

SPECIAL INSTRUCTIONS:

• Write your name and student number on the front page of the exam paper. • Write your student number on

each page of the exam paper.

• Each question has a different assigned value, as indicated.

• The use of course notes, lab notes and textbooks is permitted during this exam. •

No calculator use is allowed.

• Answer all questions in the space provided on the exam paper.

• Show the procedure you used to derive your answers.

Question

Ql

[15]

Q2

[15)

Q3

[10)

Q4 [15)

QS [15]

Marks

(2)

Student Number: __________ _

Question 1 [15 marks]

Page 2 of IS

MECHTRON 3TB4 Final Exam

a) Modem Field Programmable Gate Arrays (FPGAs) often contain functional blocks other than basic LUTs and flip-flops. One common functionality included in FPGAs is memory. The following figure shows a section of such an FPGA that contains 4 x 2 memory blocks (i.e. memory with 4 words, each word having 2 bits). Show how you can use the section of this FPGA shown in the figure to implement a 4 x 4 memory. Do not forget to route (i.e. connect) all input and output pins required to implement the 4 x 4 memory. Two figures are provided for your convenience. You can use one of them for rough work.

I I I I

-

-A, A,

-"" ""

-ROUGH WORK:

4K2 Q, 4K2 Q,

0, raw 0, _raw

Q, Q,

-""'91 ""'91

-- =

=

-�

Possible connection:

+

I _{I I I} Established connection:

+

.

-

-=

::

-A, A,

"" ""

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Student Number: �� Page3 ofl8 MECHTRON 3TB4 Final Exam

b) Using only the section of the FPGA shown in the figure, can you implement an ₈x ₂ memory? If your answer is yes, show your work in the following figure. If your answer is no, explain why not (i.e. explain what is missing).

I

-

-= ₌

-

-A, A, �

"' "'

-4x2 a, 4x2 a, D, RAM D, RAM

a, Q,

-\l'ffN \l'ffN -

--

(4)

-Student Number: _{��} Page4ofl8 MECHTRON 3TB4 Final Exam

Question

₂

[15 marks]

You were hired by a car company to build controllers for the new protocol called "CAN-Lite". This protocol has all characteristics identical to the CAN protocol discussed in class with

exception of the length of different fields in a frame. The length of different fields in a data frame in the "CAN-Lite" protocol you are building is as shown in the following figure:

:a

:a�

�

4 bits

�

3 bits

8 bits

4 bits

� N

ID

t

_t

t

End Of Frame

Start Of

Frame RTR bit ACK

As can be seen in the above figure, the frame starts with 1 dominant start bit, followed by 4 bits of a message ID and 1 bit corresponding to Remote Transmission Request (RTR - the meaning of this signal has been explained in class). CTRL field contains the length of the data field to follow (in bytes). Data represents useful data, while the "Hash" field corresponds to a hash function similar to the one described in class. Finally, the acknowledge field has one bit, and the frame ends with two recessive bits.

a) Assume there are two devices, A and B, transmitting data on this bus, as shown below. The first row in the figure below does NOT represent any data. It is there just to help you identify different parts of the other frames. Show the information that a receiving device

C

would observe on the bus in the absence of errors:

u

ID

LJc!�L�

Data

�

Hash

u

.

i

I I I I I I I I I I I

u Lil n n n

•

A

I

! ! ! !

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Page 5 ofl8 MECHTRON 3TB4 Final Exam

b) In part a) of this question devices A and B were transmitting two different

types

of frames. Identify these two types of frames:

Device A was transmitting ________ frame

Device _Bwas transmitting---frame

c) The procedure used for computing the hash function in the "CAN-Lite" protocol you are building is as follows:

• The hash function does not consider the start bit

• The remaining bits (i.e. ID, RTR, CTRL and Data) are grouped into 4-bit groups and

converted into hexadecimal digits. These digits are then all added up

modulo

16. The result is converted into binary

(4

bits) and is used as a hash.

As an example, consider the frame sent by device A in part

a)

of this question. Disregarding the start bit, the bits before the "Hash" field were: 1101 0001 0001 oooi. Converted into hexadecimal, this corresponds to OxD111. Adding these digits produces decimal number

16, which corresponds to o in modulo 16 arithmetic. Hence, the "Hash" field in this frame contains 0000.

Assuming the described hashing function is used, consider the following three messages received by a device in the network. For each message, determine whether it has been received correctly, or if there is an error in the message frame.

Circle your choices below.

Show your work (Answers without justification will not be accepted).

Message 1

Message 2

Message 3

Message 1 was received Message 2 was received Message 3 was received

i. Correctly i. Correctly i. Correctly

Data

�

Hash

I

ii. With error ii. With error ii. With error

u

I I

(6)

Student Number: __________ _ Page6ofl8 MECHTRON 3'fB4 Final Exam

Question

₃

[10 marks]

A computer system with main memory containing 256 words (1 word = 1 byte) has a direct

mapped cache that can store 16 bytes of data. The cache is divided into

4

cache lines.

a) Determine· the following quantities:

i. Number of words per cache line:

ii. Number of bits of the address that will be used for the word offset:

ii. Number of bits of the address that will be used for indexing into the cache:

iii. Number of bits of the address that will be used for the tag:

b) Assume that the direct mapped cache described in part a) of this question has a miss rate of 50%. Cost of memory access when the word is found in the cache is 1 cycle, but if the word is not found in the cache, cost of memory access is 10 cycles. You are presented with three choices for your system; you can:

- _{Keep the cache as is, or}

Increase the cache size to 512 words, which will increase the cost of memory access when the word is found in cache to 3 clock cycles, but will reduce the miss rate to 30%, or

- _{Leave the cache size as is, but implement the cache as fully associative, which will}

increase the cost of memory access when the word is found in cache to

4

clock

cycles, but will reduce the miss rate to 10%.

You can assume that the cost of memory access when the word is not found in the cache

does not change from the base case. Which of the three options would you choose if your

goal is to maximize performance?

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Student Number:. __________ _ Page 7 of18 MECHTRON 3TB4 Final Exam

Question

4 (15 marks]

a) Using Verilog, describe a circuit that takes

N

bits as an input and produces

N/2

bits as an

output.

N

is an

even number

specified as a

parameter to your module.

The circuit

implements

N/2

OR logic gates, in a way that neighbouring bits of the input are OR-ed to

produce one bit of the output. For example, if

N

is

4,

the following circuit should

be

produced:

in[O]

:

in[1]

�

>----C::::J>

out[O]

D

in[2]

:

in[3]

�

>----C::::J>

out[1]

D

(8)

Student Number:. ___________ _ Page 8 ofl8

b) Given digital filter's transfer function in the figure below, and sampling frequency of 400Hz, calculate the filter's output y(t) for the following input signal

x(t) = 1 + 2*sin(2*X*100*t) + 3*sin(2*X*120*t)

0.8

' ' '

' '

--_---:..----_---:..-- -_---_--_-- -_:..--_---_---:---_-----_--- -_:..-_--_--_-- - -_--:..- - -- -_---_---_:--_----:- - - - -- - -- - - -r--_---_---

-I I 1 I • I I I I

I 0 t I I I I I

: : _. : _. : _' : _. : _' : _' : '

I ' I I > I I I

-_---_-- -_-- -:-_----_----_-- -_,- _-- ---_-- -:- - - - -_---- - - -:-_---- - -_-- -- -:-_--- -_--_{- . -}--:--_-- - -_---_---_:-_--- --_--- -- -_:- -- -_{-- - . -}-_--:- -_{-- - -}-_--

-I I I I I I I I , I

: : : : : : : :

' ' . ' _. '

. . . . ' . '

• I I I I f I I I

--_-----_---1.------- .\. -_----_--'-- -- ---- --_{11. -}---'--- - - --- ----'---·--_------_{--... -}- -_--- -- ___ ._ ---- -_-

---: : : : : : I I :

O • I 0 I I I

: : : . : :

: : : . ' : : '

0.2 -_-- - -_----_-:-_---- - -_--_--:- ---_:--_--_--- - - -_:-- - ---_--_-:---- -_-- --_{- -}- _--- -_---- -_--:-- - - --- -₇-_-----_---_-• _---

-. . . . : : :

0 ' o I 0 t >

I I I I I I '

0 I ' I I I I

0.3 0.4 0.5 0.6 0.7 0.8

Normalized Frequency (xn rad/sample) 0.9

c) Convert the following real numbers into an appropriate fixed-point representation. You can express your solution as either _{a binary}_or_{a decimal number.}

i. Convert 0.75 into 015 _format

ii. Convert 3.25 _into03. 12 _format

iii. Convert -3.5 _into03.2 _format

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Question 5 [15 marks]

Page9ofl8 MECHTRON 3TB4 Final Exam

a) The following waveform shows a read operation on an asynchronous bus that uses

handshaking protocol for communication. Signals ADDRESS, REQUEST and R/W are driven by the master device, while signals ACK and DATA are driven by the slave device.

ADDRESS

REQUEST

-R/W

ACK

DATA

(10)

Page 10 of18 MECHTRON 3TB4 Final Exam

b) The following table shows instruction encoding for the stepper controller ASIP that you built

in lab 5. Write an assembly level program that moves the motor one step clockwise, then moves it three half-steps counter-clockwise. The delay between the steps should be 3/100

of a second. The program should repeat these movements forever.

1 O O

I I I I I

I

BR

immS

1 o 1

I I I I I

I

BRZ

immS

0 0 0

I I I

R R

ADDI reg, inon3

0 0 1

I I I

R R SUB!

reg, imm3

0J1 0 0

I I I I

SRO

imm4

0!1\0 1

I I I I

SRHO

imrn4

0!1 1 oJo 0 R R CLR

reg

011 1 1 I

R0

Rs Rs

IR,

MOV

regd, regs

111 0 o Io 0 R R MOVA

reg (BOWS)

111 oJoJo 1JR R MOVR

reg i

i

1 o 1 o·

i

0 IR R MOVRHS

reg

1lilii1i1 iii 1 PAUSE

(11)

Question

6 [30 marks]

We wish to build a custom single-purpose processor that implements a simple calculator. The calculator should support two arithmetic operations (addition and multiplication), and an "undo" operation, which restores the output of the calculator to a state it was in before the previous operation had been performed. The functionality of this calculator is described by the following FSMD:

RESET

Reset

All registers +-0 if (add or mul)

A +-input

II not( add) AND not(mul) AND not(undo) add mul undo ADD Rt-R+A TEMPt-R MUL Rt-R*A TEMPt-R UNDD Rt-TEMP TEMPt-R

The datapath for the above FSMD is given in the following figure

... •

...

,,__.,...., - _""-"'

""'1e_A

--- TElvP

dela_in • - Q _•

-A •

• ---· • Mix

ALU •

..-i _R

to WAIT

taWArr

to WAIT

Q

Q ...._ ..

In the RESET state all registers are reset to

0.

In the WAIT state the processor waits for an operation to be specified. The user specifies the operation by asserting (i.e setting to one)

only

one

of the three operation signals {add, mul or undo)

for exactly one clock cycle.

If the operation is either addition or multiplication, the processor captures the input data into the register A and then adds or multiplies it with the number currently in the register R. At the same time the processor stores the previous value of R into the TEMP register to support the undo operation.

If the operation is undo, the input data is ignored. The processor restores the old value from TEMP and, at the same time, it loads TEMP with the current value of R to support "undoing the undo".

(12)

Student Number: __________ _

""" RESET

AH reglsters+-0

WAIT

f(addormul)

A+-input

lfnot(addJ AND ntll(ITlllJ AN:> not{ undo)

R+-R+A lEMP+-R

'""

UNDO R+-1EMP

TEMP+-R IDWAIT

._ ... 8 dlfa - Q

A

alu_q>

1EM'

....

--·

l'l.U - _Q --�

R

a) Given the declaration for the datapath module of this processor, provide Verilog code that implements the datapath.

You can assume that the following elements of the datapath have been built elsewhere, and

you do NOT have to provide Verilog code that implements them:

module

alu

(input

alu_op,

input [7:0]

opA, opB,

output [7:0]

result};

II

if alu op is

0

then

add,

otherwise

mul

module

reg

(input

elk, en

a

ble, reset_n,

input [7:0]

da

ti;'"

output [7:0]

out};

module

mux

(input

select,

input [7:0]

inO, inl,

output [7:0]

result};

Provide your answer below:

module

datapath

(input

elk, reset n, enable A, enable TEMP, enable_R,

alu_op, select,

input [7:0]

data_in,

(13)

This page intentionally left blank for your answer to question 6 a). The diagrams below are provided for your convenience, and are the same as the ones on the previous pages.

RESET Reset

WAIT

f(addormul) A+--lnplJt

II not(add) AN:l not(m1.1Q AIDnot{undo)

ADD

R<-R+A TEMP ... R

..,,

UNDO

R+--TEMP TEMP ... R

__ ii B dalll.- Q

-A

.... _.

PLU ..- a __ a1.

R

(14)

RESET ""'"

WAIT ifladdOfmul)

A ... input

If ncil(add) AID nol(llll� AfIDnot(Undo)

ADD

R ... R+A TEMP-R

.• ,.

__ ,

A

Page 14of18

---·

J>W .- a --""

R

b)

_Draw_an_FSM_{diagram for the controller unit needed to implement the processor. You do}

(15)

Rooot RE<Er

WAIT if(addorrrolJ

A<-irtJut

If not( add) AND nol(rrul) AflDnol{undo)

ADD

R...-R+A TE!.f'<-R

'""

UNOO

R...-TEMP lEMf'-+-R

_ _,

A

to WAIT

Page 15of18 MECHTRON 3TB4 Final Exam

�-"'

....

ALU

c) Given the dedaration of a control unit for this processor, provide Verilog code that implements logic for the control unit.

Make sure to indicate if any of the outputs of the module should be reg type!

module control {input elk, reset_n, add, mul, undo,

output enable_A, output enable_TEMP,

output enable_R, output alu_op,

output select);

(16)

This page intentionally left blank for your answer to question 6 c

₎

. The diagrams below are provided for your convenience, and are the same as the ones on the previous pages.

RESET All reij$1ers �

.,..,.

if(addOfmul) A-input

lfnol(add}ANDnot(mun ANDnol(Undo}

ADD

R

...

R+A

TEMP

....

R ""'

UNDO

R+-lEMP TEMP._R

__ ,

"""

-

" 8

A

ALU

(17)

Reset _{W'CaddorlN.lt)}WAIT A+- input

If nol(add) AID not(mulj AIDnot{undo}

R+-R+A TElif'l+-R

"'"

UNDO

R+-TEMP

lEr.tF'+-R IDWAIT

--·

__ n e .,.,., .... Q

A

Page 17 of IS MECHTRON 3TB4 Final Exam

--·

ALU - Q __ ...

R

d

)

Given the following timing diagram of input signals to the processor, draw the values on the outputs of registers

A, R

_and

TEMP

_{if the processor operates according to the given}

FSMD.

You can assume that all registers initially contain O and that the

FSM

_{is initially in the}

WAIT

state.

FSMD

_{and the datapath are given above again for your convenience.}

add mul undo

data in

0 x

5 x

0 x

.i

x

0 )

A

0

R

0

(18)

Student Number: ________ _ _ _ Page 18of18