Semiconducting CNTFET Based Full Adder/Subtractor Using 18nm Technology

International Journal of Research in Information Technology (IJRIT)

www.ijrit.com ISSN 2001-5569

Semiconducting CNTFET Based Full Adder/Subtractor Using 18nm Technology

Dr.V. Saravanan

SRR Engineering College, Chennai - 603 103, Tamilnadu, India

Abstract: In this paper semi-conducting carbon nanotube field effect transistor is introduced for designing the full adder/subtractor circuits and various reversible logic gates. This paper proposes the reversible gates can be used for logic circuit design and to reduce the power dissipation in the circuits. Performance of design is compared with CMOS technology in terms of average power, power delay product and delay. All the simulations are done in HSPICE environment.

Keywords: carbon nanotube, reversible gates, CNTFET, logic gates.

I. INTRODUCTION

In the last few decades CMOS technology have been used for designing most of the digital circuits. In order to reduce the fabrication area required to implement the digital circuit on chip, the size of the MOS devices used in CMOS technology are scaled down. When the physical gate length of conventional device is reduced to below 90 nm, the semiconductor industry has started to face the problems such as large parametric variations and increase in leakage current. Hence the I-V characteristics substantially depart from the traditional MOSFETs, thus research has started to explore the devices at deep sub micro and Nano scales. CNTFETs have received widespread attention, as one of the promising nano device for replacing MOSFETs at the end of the Technology Roadmap [1]-[3]. Technology scaling demands a decrease in both supply voltage and threshold voltage (VT) to sustain delay reduction, while restraining active power dissipation Scaling of threshold voltage is done, however this leads to substantial increase in the sub-threshold leakage power, this causes considerable constituent of the total dissipated power. Hence the MOSFET can not be used for low power and nano application. This paper introduces the carbon nanotube field effect transistor to design reversible logic gates, which are used in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. In the conventional gates such as AND, OR and EX-OR the power dissipation is more since they are not reversible and the power dissipation is directly proportional to the number of bits erased during computation. Each reversible gate is of different type and computational complexity, and hence each will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost [4]-[6].

Carbon nanotube field effect transistor (CNTFET) based reversible logic gates are proposed in this paper.

The paper is organized as follows: Section II presents the CMOS Technology, Section III presents CNTFET Technology, Section IV discusses the HSPICE MODEL OF CNTFET, Section V discusses the Design of Full Adder/Subtractor using Reverisible Logics section VI presents the simulation results and discussion, conclusion are contained in section VII.

II. CMOS TECHNOLOGY

The prime reason for the success of the MOSFET was the development of digital CMOS logic which uses p- and n- channel MOSFETs as building blocks. Structure of the MOSFET is shown in fig (1).

Fig (1) Structure of the MOSFET

Gradually MOSFET channel size is being scaled down in size. It has been reduced from several micrometers to few tens of nanometers in modern integrated circuits using MOSFETS. Scaling of CMOS devices in the last few decades has led to increase the no of devices on chip to sustain any integrated circuits (ICs) as per Moore’s law. As per the Moore’s law number of transistors fabricated on IC is approximately doubled for every two years. Traditionally, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation. Producing MOSFETs with channel lengths much smaller than a micrometer is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology[7]-[8].

III. CNTFET TECHNOLOGY

Carbon nanotube field effect transistor (CNTFET) are currently considered, one of the main building block for the replacement of MOSFET based CMOS technology. The core of a CNTFET is carbon nanotube. CNTs are the hollow cylinder which is formed from the graphene sheet. Fig (2) shows the structure of graphene sheet. Two atoms in the graphene sheet are chosen, one of which serve as origin. The sheet is rolled until the two atoms coincide.

Fig (2) structure of graphene and Single Walled CNT

The vector pointing from the first atom towards the other is called the chiral vector and its length is equal to the circumference of the nanotube. Depending on their chiral vector, carbon nanotubes with a small diameter are either semi-conducting or metallic in nature. [9]-[11].

Fig (3) shows the structure of single walled carbon nanotube (SWCNT). The CNT may be either single walled or multi-walled. Carbon nanotube field effect transistors (CNTFETs) utilize semi conducting single-wall CNTs to assemble electronic devices. A single-wall carbon nanotube consists of one cylinder only, and the simple manufacturing process of this device makes it very promising alternative to today’s MOSFET.

Fig (3) structure of graphene and Single Walled CNT

An SWCNT can act as either a conductor or a semiconductor, depending on the angle of the atom arrangement along the tube. This is referred to as the chirality vector and is represented by equation (1), Fig (4) shows the schematic of the CNTFET

1 2

C

=

na

+

ma

(1)

The diameter of the CNT can be calculated based on the following equation (2) [12].

^{12 1 2 22}

C N T

a n n n n

D π

+ +

=

(2)

Similar to the MOSFET device, the CNTFET has also four terminals. The current-voltage (I-V) characteristics

Fig (4) Schematic diagram of a carbon nanotube transistor

of the CNTFET are similar to MOSFET’s. The threshold voltage is defined as the voltage required to turn on transistor. The threshold voltage of the intrinsic CNT channel can be approximated to the first order, as the half band gap is an inverse function of the diameter and the equation for threshold voltage is given below [12]

3

2 3

g

CNT

E aV

Vth e eD

≈ = π

(3)

where a = 2.49 Å is the carbon to carbon atom distance, V

π = 3.033 eV is the carbon π-π bond energy in the tight bonding model, e is the unit electron charge, and D

CNT is the CNT diameter [14]-[16]. As D

CNT of a (19, 0) CNT is 1.487 nm, the threshold voltage of a CNTFET using (19, 0) CNTs as channels, is 0.293V, The device channel consists of a (19,0), zigzag CNT with a band gap of 0.53 eV and a diameter of 1.5 nm.[13]-[16].

IV. HSPICE MODEL OF CNTFET

Fig (4) shows the schematic of MOSFET like CNTFET used for designing the reversible gates and adder circuits. It’s HSPICE model is shown in fig (5).

Ids Cgs

D

S

Rd

Rs

G

Csg Cdg

Fig (5) HSPICE model of CNTFET

Gate capacitance (Cgate) of the device is given by equation (4)

_{g o x}[ _{Q s}

(

1

)

_c

g a te

to t Q s Q d

L C C C

C C C C

β

+ −

= + +

(4)

Source capacitance with respect to gate voltage is given by equation (5) and drain capacitance with respect to gate voltage is given by equation (6), RD is drain resistance and RS is the source resistance.

( )

1 2 1

2 /

g tot c

sg ox

G B

L C C

C C

e V

− − β

 

=  − 

∂ ∂∆Φ

  (5)

2 1

2 /

g t o t c

d g o x

G B

L C C

C C

e V

 − β 

=  − 

∂ ∂ ∆ Φ

 

(6)

The drain to source current of the carbon nanotube field effect transistor is given by equation (7).

( ) ( )

, , ,

2 0 , ,

km kl

M L

D S ml B ml c h D S B

I = ∑ ∑ J ∆ Φ − J V ∆ Φ 

(7)

Where M and L are the sub-bands and sub-states respectively. Vch, DS is the Fermi level difference with in the channel.

J m, l is the sub-states current. Fig (6) shows the device current versus voltage characteristics for both CNTFET and MOSFET. Simulation carbon nanotube FET gate length is 18nm and MOSFET it is 180nm. CNTFET shows the better performance in terms of high on-state current, high speed and high linearity.

fig (6) Characteristics of CNTFET and MOSFET

V.DESIGN OF FULL ADDER/SUBTRACTOR USING REVERISIBLE LOGICS

In digital design energy loss is considered as an important performance parameter. Part of the energy dissipation is related to non-ideality of switches and materials. Higher levels of integration and new fabrication processes have dramatically reduced the heat loss over the last decades. The power dissipation in a circuit can be reduced by the use of Reversible logic. irreversible computations generates heat of K*Tln2 for every bit of information lost, where K is Boltzmann’s constant and T the absolute temperature at which the computation performed. Reversible logic plays an important role in low power digital design due to their ability to reduce the power dissipation in the circuits.

Reversible gates have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Using traditional irreversible logic gates such as AND or multiplexer leads inevitably to energy dissipation in a circuit, regardless of the realization of the circuit. However, if the Moore’s Law will continue to be in effect, energy losses due to non-reversible design would become essential in 2020 or earlier. Moreover, quantum logic is reversible, and the problem of searching for efficient designs of quantum circuits includes as its sub-problem the problem of synthesis using classical reversible gates, Most of the gates used in digital design are not reversible for example NAND, OR and EXOR gates. [18]

The simplest Reversible gate is NOT gate and is a 1*1 gate. Controlled NOT (CNOT) gate is a 2*2 gate. There are many 3*3 Reversible gates such as F, TG, PG and TR gate. The Quantum Cost of 1*1 Reversible gates is zero, and Quantum Cost of 2*2 Reversible gates is one. The Quantum Cost of a Reversible gate is calculated by counting the number of V, V+ and CNOT gates [19].

A. Feynman / CNOT Gate

The Reversible 2*2 gate with Quantum Cost of one having mapping input (A,B) to output (P ,Q) is as shown in the Figure (7)

Fig (7) Feynman gate

B. TR Gate

The gate has 3 inputs and 3 outputs having inputs (A, B, C) mapped to the outputs (P, Q, R). TR gate is shown in Figure (8).

Figure (8) TR gate

Reversible full Adder/Subtractor is implemented with eight Reversible gates of which five FG, two F and a TR gates is shown in the Figure 9. The numbers of Garbage outputs are three represented as g1 to g3, Garbage inputs are two represented by logical zero and Quantum Cost is 21 as it requires five FG gates each costing one, two F gates each costing five each and one TR gate costs six.

Fig (9) Full Adder /Subtractor using reversible gates

VI.SIMULATED RESULTS AND DISCUSSIONS

The simulated output of Full Adder/Subtractor using carbon nanotube field effect transistors in reversible logic is shown in fig (10). The results shows that circuit will act as either adder or subtractor depends upon the control input. Table 1 shows the simulated parameters, number gates, number of Garbage inputs/outputs , average power, delay and power delay product. Average power of the CNTFET based design is 0.147µW, where as for CMOS design is 2.5µW and delay is 5.07ns for CNTFET design, 30.06ns for CMOS design. The power delay product of CNTFET design is 0.75 aJ and for CMOS design is 32.7f.

Fig (10) simulated results of CNTFET based full adder/subtractor

Table1. Comparison of full adder/subtractor

Parameters CMOS CNTFET

No Of Reversible

Gates 8 8

Garbage

Outputs 5 5

Garbage

Inputs 3 3

Average

Power(W) 2.5µ 0.147µ

Delay (S) 13.06n 5.07n

Power Delay Product

(Joules) 32.7f 0.75a

VII. CONCLUSION

The carbon nanotube field effect transistors are used to design reversible gates and half Adder/Subtractor are designed using Reversible gates. In this paper, CNTFET are introduced to design full Adder/Subtractor unit. From the simulated results it shows that design using the CNTFET gives the better performance than CMOS based design, CNTFET has been proposed in this paper to achieve high-speed operation with low power .As the threshold voltage of the CNTFET can be easily controlled by changing the chirality vector of the CNTs, digital circuit can be designed for the required threshold voltage.

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Authors Bibilography

Dr.V. Saravanan was born in vellore, Tamil nadu, India in 1981. He received his bachelor degree in Electronics and communication Engineering from Ganadhipathy Tulsi’s Engineering college, vellore, TamilNadu in the year 2004, ME and Ph.D., in Applied Electronics and nano technology from Sathyabama University, Chennai in the year 2007 and 2013 respectively. He is presently working as Associate Professor in the Department of Electronics and communication Engineering in SRR Engineering College. He has 11 years of teaching experience. He is a life member of ISTE.