High-Speed Electronics

(1)

Page 1 C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch .

High-Speed Electronics

Mentor User Conference 2005 - München

Dr. Alex Huber, [email protected]

Zentrum für Mikroelektronik Aargau, 5210 Windisch, Switzerland

(2)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Outline 1. Motivation

2. Speed Limitation of CMOS logic

3. Current Mode Logic: Advantages and Features 4. Current Mode Logic Gates

5. Example Application: Clock-Data Recovery 6. Conclusion

(3)

Page 3 C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . 1. Motivation

(4)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Applications

• Serial Data Communication (PCI-Express, Serial-ATA, etc.) • Fiber-Optical Communication (e.g. 10G Ethernet)

• Flash-ADC, high-speed Σ∆-ADC

• Ultra-Wideband (UWB) = “wireless digital interconnect” • Fractional-N PLL (Prescaler)

(5)

Parallel I/O Bottleneck

•CPU •Graphics-P. •Display •Harddisk •Memory 64bit, 3GHz D0 D1 Dn CLK D0 D1 Dn CLK f_CLK C_coup⇒ X-Talk • Clock/Data Skew • Clock Jitter • Data Jitter •CPU •Graphics-P. •Display •Harddisk •Memory f_CLK < 166…500 MHz @ l = 1 m…10 cm, 16…64bit 64bit, 3GHz

(6)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch .

Serial Data Communication

D0 D1 Dn CLK f_CLK f_ser MUX DEMUX D0 D1 Dn CLK f_CLK CR DEC f_ser 2/n D₀ f_ser = n/2 · f_CLK D₁D2 D₃ D_n f_CLK

High-Speed Digital Electronics required! CLK g

enera

ted at Rx

f_CLK = 2 GHz, n = 16 bit f_SER = 8 · 2 GHz = 16 GHz (32 Gb/s)

Clock not transmitted: Unlimited number of parallel links

(7)

I/O Technology Trend

Optical PCI Express Serial-ATA IEEE 1394b PCI Bus ISA Bus

f

_SER = signaling clock rate

Year 66MHz 1GHz 5GHz 10GHz 20GHz 1980 ₁₉₉₀ ₂₀₀₀

12GHz Copper Signaling Limit (attenuation)

1GHz Parallel Bus Limit (cross-talk)

MCAEISA VESA PCI-X AGP 2x Parallel Bus Architectures

Serial Bus Architectures

(8)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Technologies

• Earlier: Dominated by bipolar processes (GaAs, Si, SiGe, InP)

• Nowadays: CMOS at 130nm, 90nm, (65nm)

(9)

(10)

Repetion: Some Basics of MOSFET

Transconductance

(

)

0 2 2 > − ≥ − = GS T _DS _GS _T n,p ox D V U V V U L W C I µ for v_GS g_mv_GS i_D G S S D C_GS C_DS

DC Drain Current _{Threshold Voltage}

Design Variables W_n L I_D V_GS V_DS G D S V_DS W_p L I_D V_GS S G D 2 2 GS T n,p ox GS D m U V L W C V I g = ⋅ − ∂ ∂ = µ

(11)

Speed Limitation of CMOS Gates

V_inCgs,n C_gs,p V_gs,n V_gs,p i_d,p=g_m,p*V_gs,p i_d,n=g_m,n*V_gs,n C_ds,p C_ds,n V_out V_in _V out W_p L W_n L V_DD

• With ideal voltage drive: t_d = ∆V_out·C_ds,p/i_d,n

• For V_p=V_DD/2: W_p ≈ 2…3 W_n (due to µ_n ≈ 2...3µ_p) • To reduce delay t_d: C_ds,p L ; W_p W_n i_d,n L ; g_m,n W_n Given technology: No improvement possible! Technology scaling: L=1µm (1990) L=90nm (2004)

(12)

Reduction of Delay Time

Basic idea: Decouple charging current and switch transistor

V_in V_out Load W_n L V_DD i_charge

Common Mode Voltage V_cm?

Load: PMOS, resistor, inductor, …?

• I_charge ; W_n t_d

• Limits: W_n large enough for a) V-Gain = g_m,n·R_Load > 1

(13)

Current Mode Logic (CML)

Advantages for high-speed operation:

1. Independent choice of W_n and i₀

2. Differential mode: higher SNR 3. Free choice of load:

PMOS, Resistor, Inductor

4. With Inductor: BW_ind ≈ 2·BW_res

⇒ f_CLK,CML ≈ (2..3)·f_CLK,CMOS @ same L

Disadvantages:

1. Static DC power consumption V_DD·i₀

2. Area consumption:

2 {PMOS | Res | Ind}, 3 NMOS

V_in V_out i₀ Load W_n L V_DD Load W_n L V_DD V_cm Differential topology: independent of V_cm

(14)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . 1. Motivation

3. Current Mode Logic: Advantages and Features

4. Current Mode Logic Gates

(15)

CML vs. CMOS: Figures of Merit

Delay t_d CMOS CML I C V N RC N ⋅ = ∆ ⋅ _α µ( _DD _t) ox DD U V C V C N − ⋅ ⋅

Logic swing _{Load Capacitance}

~∆V Power P N ⋅I ⋅V_DD ( 1 ) , 2 d CLK CMOS d DD t f t C V N = ⋅ ⋅ Power-Delay Product

[

]

C V V N I C V N V I N t P DD DD d ⋅ ∆ = ⎥⎦ ⎤ ⎢⎣ ⎡ ∆ ⋅ ⋅ ⋅ ⋅ = ⋅ 2 C V N t t C V N DD CMOS d CMOS d DD ⋅ ⋅ = ⋅ ⋅ ⋅ ₂ , , 2 Energy-Delay Product

[

]

I C V V N I C V N C V V N t P DD DD d 2 2 3 2 2 ) (∆ = ⎥⎦ ⎤ ⎢⎣ ⎡ ∆ ⋅ ⋅ ⋅ ∆ = ⋅ α µ( ) 2 3 2 , 2 t DD ox DD CMOS d DD U V C C V N t C V N − = ⋅ ⋅ ⋅ Logic depth ~I

(16)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . CML vs. CMOS: Trade-Off Energy-Delay-Product EDP: α µ( ) 2 3 2 t DD ox DD CMOS U V C C V N EDP − = I C V V N EDP_CML DD 2 2 3 ₍_∆ ₎ = V_DD[V] 0.5 1 1.5 2 100 200 300 400 Delay CMOS t_d [ps] I[µA] 1 10 100 100 200 300 400 Delay CML t_d [ps] 1000 1 1.5 2 2.5 EDP [pJ·ps] Energy-Delay (N=4) Advantage for CML: low logic depth, very high speed

Example: • 0.25µm technology • V_DD=2.5V • PMOS load No low bound on CML delay with current!

(17)

3. Current Mode Logic: Advantages and Features

4. Current Mode Logic Gates

(18)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Inverter Logic Level: V_h = I₀·R_C Gate Delay t_d V_DD

(19)

Page 19 C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Multiplexer V_DD V_DD

(20)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . EXOR V_A=1, V_B=1: V_Q=-1~0 V_A=-1, V_B=1: V_Q=1 V_A=1, V_B=-1: V_Q=1 V_A=-1, V_B=-1: V_Q=-1~0 V_DD VDD V_DD V_DD

(21)

Page 21 C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . D-Latch V_DD V_DD

(22)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Master-Slave D-FlipFlop Negative edge triggered FF with respect to CLK

(23)

Design Techniques for CML

• CMOS design kits typically don‘t provide CML standard cells

(some Bipolar/BiCMOS kits might, but typically only in very mature = “old” = “slow” technologies and only symbol/layout)

• System design can be done on cell-level

• Cell design is done with analog (= transistor-level) techniques

• Simulation must reflect the analog nature of CML gates (= dependence of delay/transition-time on input/output impedance)

(24)

C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . 1. Motivation

5. Example: Clock-Data Recovery for Serial Data Communication

(25)

Clock-Data Recovery (I)

DEMUX D0 D₁ D_n CR DEC f_ser 2/n CLK D_in PFD LF VCO DFF D_in DEMUX Full-Rate

Architecture _external?Passive,

PLL Analog

DFF (CML) and VCO operate at f_ser

(e.g. 40GHz at 40Gb/s)

Î“low” complexity

(26)

Clock-Data Recovery (II)

DEMUX D0 D₁ D_n CR DEC f_ser 2/n CLK D_in VCO D_in DFF DFF DFF Edge Detector Loop Filter D₀ D₁ D_n 2n DFF 2n VCO Phases Reference Frequency n-th Rate Architecture Digital (CML) Analog (?) • Clock frequency at DFF: f_{CLK, full-rate}/n • 2n phases required (∆t = 1/(2f_{CLK, full-rate}))

(27)

Page 27 C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Edge Detection D_in DFF DFF DFF Edge Detector 2n DFF

2n Phase Clk to Loop Filter

d₀ e₀ e_n CLK locked: CLK in-phase with DATA D0 D1 D2 D3 d₀ d₁ e₀ e₁ d_n≠ d_n+1 <e_n> = 0.5 DATA CLK CLK D0 D1 D2 D3 CLK is early w/ respect to DATA d₀ d₁ e₀ e₁ d_n = e_n DATA CLK

(28)

Generation of Variable Clock Phase

V

_ctrl

VCO: _cos([ω₀₊_K_vco_·_V_ctrl_]_·_t_{) = cos(ω}₀_t _{+ ∆φ)}

∆φ = K_vco·V_ctrl·t = ∫K_vco·V_ctrldt

Phase Rotator:

n-phase VCO φ-rot cos(ω₀t) φ₁

···

∆ϕ = δϕ·n·T no Integration! cos(ω₀t +∆φ) δϕ UP DN φ_n

I

Q

= ϕ₀ = ϕ₁ = ϕ₂ = ϕ₃

(29)

Clock-Data Recovery (III): HIGHSCORE 16 16 Edge- Detec-tor D E Early Late 16 16 8 parallel Sampler Rate Reduction Early Late 1 1 D D D D E E E E 4 0°, 45°, ... , 315° 8-phase DLL up

dn up/down_counter Digital Loop_Filter

0°, 45°, ... , 315° Ref-VCO (8 phase) Phase-Rotator 40 Gb/s optical input 4x 10Gb/s electrical output 10GHz 2.5GHz 1.25GHz 1.25GHz _1x/Link 1x for 8 Links

CML (“analog”) CMOS (“digital”)

8:32 DEMUX

“High-Speed Communication Receiver for 40 Gb/s in CMOS”: CTI Project of zma, BFH Burgdorf, ETHZ, IBM ZRL

(30)

HIGHSCORE Key Features

• Goal: Serial Communication Receiver (=CDR) at 40 Gb/s • 90 nm CMOS state-of-the-art (IBM)

• FO4-Delay of CMOS: 20 ps

• Typical clock frequencies of CMOS logic: 1.25 GHz

• CML operates at f_CLK = 10 GHz, partially inductor-peaked • Quarter-Rate Architecture

• No external passive components (except 1 XTAL) • Fully digital loop-filter (complex functions possible!)

• Simulation-friendly: VHDL/Verilog representation for system characterization possible

(31)

Page 31 C opy right by Zent ru m fü r M ikr oe lekt ron ik Aa rgau , C H -5 210 Win di sch . Conclusion

• CMOS logic maximum speed can only be scaled by technology improvements (reduce Gate-Length)

• CML logic offers 2-3 times higher clock frequencies with

improved Energy-Delay product compared to CMOS at same frequencies and same Gate-Length

• CML gates are designed and simulated with analog

techniques while the system function is digital by nature • A main application of very high speed digital electronics is

Serial Data Communication for highest I/O Bandwidth to overcome the parallel I/O Bottleneck

• Highly parallel architectures allow fully digital designs with complex functions in CMOS replacing bulky passive