w5_top_level_view_interrupts_amp_internal_memory_2.pdf

TOP LEVEL VIEW OF COMPUTERS

2/40

3/40

I

-C

 All the units must be connected

 Different type of connection for different type of unit

 Memory  Input/Output  CPU

5/40

M

C

 Receives and sends data

 Receives addresses (of locations)

 Receives control signals

 Read  Write  Timing

6/40

I

/O

C

(1)

 Similar to memory from computer’s viewpoint

 Output

 Receive data from computer  Send data to peripheral

 Input

7/40

I

/O

C

(2)

 Receive control signals from computer

 Send control signals to peripherals

 e.g. spin disk

 Receive addresses from computer

 e.g. port number to identify peripheral

 Send interrupt signals (control)

CPU C

 Reads instruction and data

 Writes out data (after processing)

 Sends control signals to other units

9/40

B

 There are a number of possible interconnection systems

 Single and multiple BUS structures are most common

 e.g. Control/Address/Data bus (PC)

 e.g. Unibus (DEC-PDP)

10/40

W

B

?

 A communication pathway connecting two or more devices

 Usually broadcast

 Often grouped

 A number of channels in one bus

 e.g. 32 bit data bus is 32 separate single bit channels

11/40

D

B

 Carries data

 Remember that there is no difference between “data”

and “instruction” at this level

 Width is a key determinant of performance

 8, 16, 32, 64 bit

A

 Identify the source or destination of data

 e.g. CPU needs to read an instruction (data) from a given location in memory

 Bus width determines maximum memory capacity of system

 e.g. 8080 has 16 bit address bus giving 64k address

13/40

C

B

 Control and timing information

 Memory read/write signal  Interrupt request

 Clock signals

14/40

15/40

B

Y

?

 What do buses look like?

 Parallel lines on circuit boards  Ribbon cables

 Strip connectors on mother boards

e.g. PCI

 Sets of wires

17/40

S

B

P

 Lots of devices on one bus leads to:

 Propagation delays

Long data paths mean that co-ordination of bus use can

adversely affect performance

If aggregate data transfer approaches bus capacity

 Most systems use multiple buses to overcome these problems

T

(ISA)

H

P

B

B

T

 Dedicated

 Separate data & address lines

 Multiplexed

 Shared lines

 Address valid or data valid control line  Advantage - fewer lines

 Disadvantages

21/40

B

A

 More than one module controlling the bus

 e.g. CPU and DMA controller

 Only one module may control bus at one time

 Arbitration may be centralised or distributed

22/40

C

D

A

 Centralised

 Single hardware device controlling bus access

Bus Controller Arbiter

 May be part of CPU or separate

 Distributed

23/40

T

 Co-ordination of events on bus

 Synchronous

 Events determined by clock signals  Control Bus includes clock line  A single 1-0 is a bus cycle  All devices can read clock line  Usually sync on leading edge  Usually a single cycle for an event

A

T

– R

D

A

T

– W

27/40

PCI B

 Peripheral Component Interconnection

 Intel released to public domain

 32 or 64 bit

 50 lines

INTERNAL MEMORY

30/40

31/40

F

M

33/40

T

ROM

34/40

35/40

S

M

T

Memory Type Category Erasure Write Mechanism Volatility

Random-access

memory (RAM) Read-write memory

Electrically,

byte-level Electrically Volatile

Read-only memory (ROM)

Read-only memory Not possible

Masks Nonvolatile Programmable ROM (PROM) Electrically Erasable PROM (EPROM) Read-mostly memory

UV light, chip-level

Electrically Erasable PROM (EEPROM)

Electrically, byte-level

Flash memory Electrically, block-_level

S

M

 RAM

 Misnamed as all semiconductor memory is random

access

 Read/Write  Volatile

37/40

P

C

 Basic element of semiconductor memory is a cell.

 They exhibit two states, represent binary 0 and 1

 They are capable of being written into to set the state

 They are capable of being read to sense the state

38/40

39/40

D

RAM

 Bits stored as charge in capacitors  Charges leak

 Need refreshing even when powered  Simpler construction

 Smaller per bit  Less expensive  Need refresh circuits  Slower

 Main memory  Essentially analogue

 Level of charge determines value

41/40

D

RAM S

42/40

DRAM O

 Address line active when bit read or written

 Transistor switch closed (current flows)  Transistor switch open (no current flows)

 Write

 Voltage to bit line

High for 1 low for 0

 Then signal address line

Transfers charge to capacitor

 Read

 Address line selected

transistor turns on

 Charge from capacitor fed via bit line to sense amplifier

Compares with reference value to determine 0 or 1

43/40

S

RAM

 Bits stored as on/off switches  No charges to leak

 No refreshing needed when powered  More complex construction

 Larger per bit  More expensive

 Does not need refresh circuits  Faster

 Cache  Digital

 Uses flip-flops

45/40

S

RAM O

 Transistor arrangement gives stable logic state

 State 1

 C1 high, C2 low  T₁ T₄ off, T₂ T₃ on

 State 0

 C2 high, C1 low  T₂ T₃ off, T₁ T₄ on

 Address line transistors T₅ T₆ is switch  Write – apply value to B & compliment to B

 Read – value is on line B

46/40

SRAM

DRAM

 Both volatile

 Power needed to preserve data

 Dynamic cell

 Simpler to build, smaller  More dense

 Less expensive  Needs refresh  Larger memory units

 Static