{?,*,,,;.:43.i,... 1 Introduction

MOTOROLA

_by Order this document

_{MC68HC972B32TS/D}

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SEMICONDUCTOR-TECHNICAL

DATA

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MC68HC912B32

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Technical

Summary

16-Bit Microcontroller

1 Introduction

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The MC68HC912B32 microcontroller unit (MCU) is a 16-bit device compose~.@~~f~~dard on-chip

pe-ripherals including a 16-bit central processing unit (CPU I 2), 32-Kbyte fla:~j~E~~OM, 1-Kbyte RAM,

768-byte EEPROM, an asynchronous serial communications interface (~iQ~:w’SSerial peripheral

inter-face (Spl), an 8-channel timer and 16-bit pulse accumulator,

an 8-bit qnal~-lti-digital

convefler (ADC),

a

four-channel pulse-width modulator (PWM), and a JI 850-compa~]+q,Qyte data link communications

module (BDLC). The chip is the first 16-bit microcontroller to incl@&~~ith byte-erasable EEPROM and

flash EEPROM on the same device. System resource mappi~~,o~%~k generation, interrupt control and

bus intetiacing are managed by the Lite integration modul~ (h~). The MC68HC932B32 has full 16-bit

data paths throughout, however, the multiplexed externa@$,us can operate in an

8-bit

narrow mode so

single 8-bit wide ‘memory can be interfaced for lower @~$s~tems.

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1.1 Features ,.*i;.,<’..,>.,“.$;$+..:.,4,$:/$:_,...

0

● 16-Bit CPU12 \.,\,{.$~

— Upward Compatible with M68H~$&,lnstruction Set

— Interrupt Stacking and Progr%&r’& Model Identical to M68HC11

— 20-Bit ALU _SP,,i,s$:”!*t_~~$~.

— Instruction Queue aa<\.~’rr+t.\&t,,,*.,,>’.

— Enhanced Indexed fi~*ri9

— Fuzzy Logic lnstru~~i~~

●Multiplexed Bus ~~~:f?~ .’i:.:+$,$~:i

— Single Chip ,~t,,~~$nded

— 16/16 Wide$br ~$/8 Narrow Modes_{,,.,.3.. :!~}

\f~r~,x$i..\.hN.

●Memory 4:3,,,~

— 32-Kbyte%&sh EEPROM with 2-Kbyte Erase-Protected Boot Block

— 7Q$i~’~$e EEPROM

-:%.%&y?e RAM with Single-Cycle Access for Aligned or Misaligned ReadMrite

: 8~~nnel, 8-Bit Analog-to-Digital Converter

.<,.x$-~hannel

Timer $,

,*,\,,.:*- Each Channel Fully Configurable as Either Input Capture or Output Compare

,#a;J*.’\,>,_,.,,..,<} ,<:,.”,,\

l“i,~l,._..$:<;.,\l....y.lJ., — Simple PWM Mode

.:*,*.,~...,J$ — Modulo Reset of Timer Counter

‘* ‘:.LJ_..:..*J.V.*

“:>,.,. ●16-Bit Pulse Accumulator

:*.

— External Event Counting — Gated Time Accumulation

●Pulse-Width Modulator

— 8-Bit, 4-Channel or 16-Bit, 2-Channel

— Separate Control for Each Pulse Width and Duty Cycle

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This document contains information on a new product. Specifications and information herein are subject to change without notice,

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MOTOROLA

— Programmable Center-Aligned or Left-Aligned Outputs

●Serial Interfaces

— Asynchronous Serial Communications Intetiace (SCI)

— Synchronous Serial Peripheral Interface (SPI)

— JI 850 Byte Data Link Communication (BDLC) o

●COP Watchdog Timer, Clock Monitor, and Periodic Interrupt Timer

●80-Pin QFP Package

— Up to63 General-Purpose l/O Lines *,\

— 2.7V-5.5V Operation at @MHz $J,$<,.‘!i.t,:,,.,’~*’X,l,1+ts.,,’$:.

●Single-Wire Background DebugTM Mode (BDM)

<p$ ‘..<$* ,.~”..\x../i*-*_..+,

●On-Chip Hardware Breakpoints

‘,’*I. ,’;>,....\\*.,,;$~, .%,,,...>*., ,i#’&*u:,,. .~:...1,.. ,,’.)*%,:.F,,. 1.2Ordering Information .,.“,,1.. ,$J2.’~,k,*,,,.,,1. ,,,*.:%:,$

The MC68HC912B32 is,packaged in 80-pin quad flat pack (QFP) packaging and isfh~~~%~”(n two-piece

sample packs, 50-piece trays, or 250-piece bticks. Operating temperature ran~~;~~d ‘voltage

require-ments are specified when ordering the MC68HC912B32 device. Refer to Tah@,~,;?&rpart numbers._{~~,.~, ‘...*l.\}

Temperature ,.,.;,..-.::

Order Number Voltage,J$~.$~~&~uency

Range Designator _i!, ~~<:$_\ MC68HC912B32FU8 o to +70 “c — _.x*,,,3f,.~y,*~*s!:’_*

‘.:*.,

MC68HC912B32CFU8 –40 to +85 ‘C c

MC68HC912B32VFU8 -40 to+105 “c v ,F.~:..3.4B:,\~~4?i(-5.5v

~-MC68HC912B32MFU8 -40 to+125 ‘C M (.,:ff~k,,,}_{,.,, .} 8 MHz MC68C912B32FU8 oto+70 “c — “$:~~ ~

MC68C912B32CFU8 -40 to +85 ‘C ., c $y’ ‘ 2.7V–3.6V

MC68B912B32FU8 o to +70 ‘c _,:..,..Y;:.,.i‘:T>:- 2.7U–5,5U

Package

80-Pin QFP Single Tray 50 Pcs

NOTE: This part is also available in 2-~f@&rnple packs and 250-piece bricks.

Evaluation boards, assemblers,,&#~~j&rs, and debuggers are available from Motorola and from

third-party suppliers. An up-to-date:~~.$+~roducts that suppoti the M68HC12 family of microcontrollers can

be found on the World Wid~ ~~~%t the following URL:

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MOTOROLA _MC68HC912B32

1.3 MC68HC912B32 Block Diagram

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32-KB~E FLASH EEPROM v~~ —

v~p VRI —

1-KBVE RAM

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768-B~E EEPROM

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I

CPU12

I

BKGD — SMOON /~ PERIODIC INTERRUPT

COP WATCHDOG SINGLE-WIRE

BACKGROUND CLOCK MONITOR DEBUG MODULE BREAK POINTS EXTAL — XTAL — RESET — PEO — - XIRQ PE1 — — ~Npp PE2 — -u m

PE3 - ₊ - LSTRB / TAGLO LITE

PE4 - K_g - ECLK INTEGRATION

PE5 - - lPIPEO/MODA MODULE

PE6 - - IPIPE1 / MODB (LIM)

PE7 — - DBE I I NARROW BUS : .--- --- , POWER FOR INTERNAL CIRCUITRY

Figure 1 MC68HC912B32 Block Diagram

2Centra1

Processing

Unit

,.

The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal

reg-isters (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset

of the M68HC11 instruction set. The CPU 12 allows instructions with odd byte counts, including many

●

single-byte instructions. This provides efficient use of ROM space. An instruction queue buffers

pro-gram information so the CPU always has immediate access to at least three bytes of machine code at

the start of every instruction. The CPU I 2 also offers an extensive set of indexed addressing capabilities.

,,.,, . 15

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15 IY 15 SP . s:. 15 “ Pc _,? .i)~~.._\ .... o PROGRAMCOUNTER ,i.>x,;~,$, “.*$:k\, f:?l~ ,= coND’T’oNcoDEREG’sTER ~~~ -+:.\ .,s.**-,+::k(~t>~‘_\!*\*:.i:j$~ Hc12 PROG MODEL ~>,>, +)>~!,. ~>\>2k,,, :i::?,,>, ,% ,?,!t.tj$

‘%’’’$$’ Figure 2 Programming Model

*’.&_\\i. *.*ly,k*...!:,>:!.,$’ -..

:,? !, “_j)’ ~.. l.>{,l$?

Accumulators ~~~qd~ are general-purpose 8-bit accumulators used to hold operands and results of

arithmetic c~ul~whs or data manipulations. Some instructions treat the combination of these two

8-bit accum@rs as a 16-bit ‘double accumulator (accumulator D).

~3,..?~tyw

lnde~,,$~~ers X and Y are used for indexed addressing mode. In the indexed addressing mode, the

co@~~@:bf a 16-bit index register are added to 5-bit, 9-bit, or 16-bit constants or the content of an

ac-~~~;~tor to form the effective address of the operand to be used in the instruction.

., ‘,,.

#f$,#fack pointer (SP) points to the last stack location used. TheCPU12 suppofls an automatic program

$j~i~~~:stack that is used to save system context during subroutine calls and interrupts, and can also be used

‘+~ for temporay storage of data. The”stack pointer can also be used in all indexed addressing modes.

‘:$,q”, 3:,,

Program counter is a 16-bit register that holds the address of the next instruction to be executed. The

program counter can be used in all indexed addressing modes except auto-increment/decrement.

Condition Code Register (CCR) contains five status indicators, two interrupt masking bits, and a

STOP disable bit. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow

-(C). The half-carry flag is used only for BCD arithmetic operations: The N, Z, V, and C status bits allow

for branching based on the results of a previous operation. ~

2.2 Data Types

The CPU12 suppofls the following data types:

0 Bit data

●8-bit and 16-bit signed and unsigned integers

●16-bit unsigned fractions

●16-bit addresses _*,\

A byte is eight bits wide and can be accessed at any byte location. A word is composed of two con+%&$.

*’X,l,

utive bytes with the most significant byte at the lower value address. There are no special require#e&W”

for alignment of instructions or operands. _,,+?.it’?$::,<~:$+$...?,*:,???..

\,.? ,.,..,,~:,?::$ ,.$“h.. ~,:J 2.3 Addressing Modes ,,+,:.*” .{~l.,\\\!. ..,,.*J~,:?’-\ .$4+:$.~$..:i<’

Addressing modes determine how the CPU accesses memory locations to be op&$t@upon. The

CPU12 includes all of the addressing modes of the M68HCI 1 CPU as well as s%Ykal ~~w forms of

in-dexed addressing. Table 2 is a summay of the available addressing modes.w$;!++~~;$ ,.:,:1~?,. ~+’f?

Addressing Mode Source Format Abbreviation ~~$,:,,,;,:,,...>:,.,A.,*~.~.:,.,$~,. ~Description ~>b::’’’’,”.,;l),~’.>$

INST

Inherent (no externally supplied INH .~~~~nds (if any) are in CPU registers

operands) _,,4: ‘s.i<$~\ ..”,

INST#opr8i >’>...,

Immediate or IMM $2’”9+“ ‘%$,F.Operand is included in instruction stream

INST#opr76j _i,>>‘<!’{.. ,,,_~$>.$<>...~j$ 8- or 16-bit size implied by context

,:,:y*,.,:~.>~\:,,

Direct INSTopr8a Dl~;’;i Operand is the lower 8-bits of an address in the

~b.i range $0000 – $OOFF

Extended INSTopr16a \yi\,J$r,$,e‘:’ EXT Operand is a 16-bit address

‘.:,,\

INSTre/8 F...}~,,,,:i:$*l:,,+, ).

Relative $ ‘~i.ifl ..‘. REL An 8-bit or 16-bit relative offset from the current

lNS;;ell~k~{~~~ “< pc is supplied in the instruction

it .\*i\,‘.,2‘

Indexed ....,,,,,!},..$\.,$+

(5-bit offset) INSTOp~~fW_{‘*.,\ ..} ~~>;. IDX 5-bit signed constant offset from x, y, sp, or PC ~<,,..

Indexed <t>,.,,: +:%,7$ lN~~ o~x3,-xys

(auto pre-decrement) *:@:.j$,:’.,)>,,,%?~ IDX Auto pre-decrement x, y, or sp by 1-8 ,., _\/::

(auto ::-:::: merit) ,#?%t~w* opm3,+xys ~?j.,

IDX Auto pre-increment x, y, or sp by 1-8 .,>.,,\ :1:

Indexed ~~,,. “[2

(auto post$~~,< ‘ INST opm3,xys- IDX” Auto post-decrement x, y, or sp by 1-8

decreqq~~:$ “” lnd~~~,’ ‘“

(auto,Q~*~n&ement) INST opm3,xys+ IDX Auto post-increment x, y, or sp by 1-8

,P<~$,Jn$exed

INSTabd,xysp Indexed with 8-bit (A or B) or 16-bit (D)

accumu-,~~,k~ulator offset) IDX Iator offset from x, y, sp, or pc

~...,,‘~~ Indexed 9-bit signed constant offset from x, y, sp, or pc

‘“ (9-bit offset) INST oprx9,xysp IDX1 (lower 8-bits of offset in one extension b~e)

Indexed

INST0PH76,XYSP IDX2 16-bit constant offset from x, y, sp, or pc

(16-bit offset) (16-bit offset in two extension bytes)

Indexed-Indirect Pointer to operand is found at...

(16-bit offset) INST [oprx76,xysp] [IDX2]. 16-bit constant offset from x, y, sp, or pc (16-bit offset in two. extension bytes) Indexed-Indirect

(D accumulator INST [D,xysp] [D,IDX] Pointer to operand is found at...

offset) x, y, sp, or pc plus the value in D

MC68HC912B32 MOTOROLA

2.4 Indexed

Addressing Modes

The CPU12indexed

modes reduce execution time and eliminate code size penalties for using the Y

index register. CPU I 2 indexed addressing uses a postbyte plus zero, one, or two extension bytes after

the instruction opcode. The postbyte and extensions do”the following tasks:

●

●

Specify which index register is used

●

Determine whether a value”in an accumulator is used as an offset

Postbyte Source Code Comments

Code (xb) Syntax rr; OO=X, Ol=Y, 10=SP, ll=PC

rr Onnnnn ,r 5-bit constant offset

n =

-16to+15

n,r r can specify X, Y, SP,’ orPC

—n, r

lllrrOzs n,r :Constant offset (9-

or 16-bit

signed)

–n, r -256<

n c

255

1 =16-bit .,,.{,*... 0< n c 65,535

if z =s = 1, 16-bit offset indexed-indirec~,~&:’Wlow) r can specify X, Y, SP, orPC _>..\*t<\..* t~$“’

lllrrOll [n,r] 16-bitoffset indexed-indirect -~~+?“X’*~

rr can specify X, Y, SP, or PC,,2$ “’%~l. 0 c n <65,535

rrlpnnnn n,-r Auto pre-decrementincr+h%nr Auto post-decrementincrement;

n,+r

P = Pre-(o)or post-(l)) Q#T8@ –1, +1 to +8

n,r- rcanspecify X, Y, or,,.SF<@Jhot a valid choice)_~~i:{p,kt$w

n,r+ +8=0111 \,..., ~

~f~

lllrrlll

(&fator offset (unsigned 8-bit or 16-bit)

*$ ..s ...., ,\~. ~..:s~,,e\:\...

2.5 Opcod,@,#~~’Operands -,.,9. ... ‘:.?..

Th@~~,~12 uses 8-bit opcodes. Each opcode identifies a patiicular instruction and associated

@ ~.de to the CPU. Several opcodes are required to provide each instruction with a range of

address-. lB~,~pabilitiesaddress-.

,1.;.$.’i.>

..,‘,,

‘

.’ti::.~

~:?,c:~

:,“

$+~!,h.~S:Only256

opc’odes.would be available if the range of values were restricted to the number that can

be

.,ti.h~.,k,s,+.s..

“l$\

_{represented by 8-bit bina~ numbers. To expand the number of opcodes, a second page is added to the}

:F

opcode map. Opcodes on the second page are preceded by an additional byte with the value $18.

To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension

bytes. Postbytes implement cetiain forms of indexed addressing, transfers, exchanges, and loop

prim-itives. Extension bytes contain additional program information

such as addresses, offsets, and

immedi-ate data.

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MOTOROLA

MC68HC9!2B32

13 Serial Interface

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The serial intedace of the MC68HC912B32 consists of two independent serial 1/0 sub-systems: the

se-rial communication interface (SCI) and the serial peripheral interface (SPI). Each serial pin shares

func-tion with the general-purpose port pins of poti S. The SCI is an NRZ type system that is compatible with

standard RS-232 systems. The SCI system has a single wire operation mode which allows the unused

pin to be available as general-purpose I/O. The SPI subsystem, which is compatible with theM68HC11

SPI, includes new features such as SS output and bidirectional mode. *{iv

13.1 Block Diagram

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13.2 Serial Communication Interface (SCl]:j~, ““

The serial communication intedace aQt~~R,~~68HC91 2B32 is an NRZ format (one start, eight or nine

data, and one stop bit) asynchron@&~@rnunication system with independent internal baud rate

gen-eration circuitry and an SCI tranq~~~’~nd receiver. It can be configured for eight or nine data bits (one

of which may be designated ,~~;~wfity bit, odd or even). If enabled, parity is generated in hardware for

transmitted and received dqt~~ceiver parity errors are flagged in hardware. The baud rate generator

is based on a modulus @fi~~@~ allowing flexibility in choosing baud rates. There is a receiver wake-up

feature, an idle line .*@~ature, a loop-back mode, and various error detection features. Two port

pins provide the e.xt&n.# interface for the transmitted_{,\.$sa;\&i:’*>+$*.} data (TXD) and the received data (RXD).

,.$>\.:+?>.> \{... /t

MC68HC912B32 MOTOROLA

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I f’: ., I&eMl\/cD lNTi:NAL LOGIC 7 LSB 1. -I I I I I I I I I I I I I ,, I I 1, I ,. I 1’ . HC12B32 SCI BLOCK

‘*’:Y$’;$?’@*~nidle-line in the high state before transmission or reception of a message.

~):t,

,.i.~,.~>;.~.s,.s,

FJ.F,,, ‘\t*$ ●A stati bit (logic zero), transmitted or received, that indicates the start of each character.

$%_~:;,...<$.>,.._,<~~))~

* Data that is transmitted or received least significant bit (LSB) first.

& ...

●A stop bit (logic one), used to indicate the end of a frame. (A frame consists of a start bit,. a

char-acter of eight or nine data bits and a stop bit.)

●A BREAK is defined as the transmission or reception of a logic zero for one frame or more.

●This SCI -supports hardware parity for transmit and receive.

.,

MOTOROLA” _MC68HC912B32

84 _{,, MC68HC912B32TS/D}

13.2.2 SCI Baud Rate Generation

The basis of the SCl baud rate generator is a 13-bit modulus counter. This counter gives the generator

m the flexibility necessary to achieve a reasonable level of independence from the CPU operating

frequen-cy and still be able to produce standard baud rates with a minimal amount of error. The clock source for

the generator comes from the P Clock.

Table 28 Baud Rate Generation

Control and data registers for the SCI subsystem are d~c~b below. The memory address indicated

for each register is the default address that is in use a~&I{eset. The entire 51 2-byte register block can

be mapped to any 2-Kbyte bounda~ within the sta~~$ 64-Kbyte address space.

\.,:/,r!*

SCOBDH — SCI Baud Rate Control Register .:?,.y,v~.,~:,,,,>.“’%8,..,,,,.” _$Ooco

..,4\r,,

Bit 7 6 5. _~->?,%s4$ ‘ 3 2 1 Bit O

. BTST BSPL BRLD ~sm12 SBR11 SBR1O SBR9 SBR8 High

RESET: 0’ 0 Q$’’.,?;%:%:’o 0 0 0 0

,,,,

Bit 7 6_,,.,..V.t~i_{“+>\h>.,.ii\}~,!,:,,?,{.,.,,;.5 4 3 2 1 Bit O

SBR7 _{*&t*QW:? I SBR5} SBR4 SBR3 SBR2 SBR1 SBRO Low

RESET: o .,..,?<$*,,$ o 0 0 1, 0 0

.*L.\.

SCOBDH aqd @DL are considered together as a 16-bit baud, rate control register.

Read [email protected] SBRII 2:0] anytime. Low order byte must be written for change to take effect. Write

SBR[lQ:$~~~&fily in special modes. The value in SBR[12:O] determines the baud rate of the SCI. The

desi{~~~~d rate is determined by the following formula:

?~>.:”” ‘ *],

BR = MCLK

16x SCI Baud Rate

BR is the value written to bits SBR[l 2:0] to establish baud rate.

NOTE

- The baud rate generator is disabled until the TE or RE bit in SCOCR2 register is set

for the first time after reset, and/or the baud rate generator is disabled when

- _{SBR[12:O] = o.}

MC68HC9,12B32 _MOTOROLA

BRLD — Baud -Rate Reload

Reserved for test function _*{iv

SCOCRI — SCI Control Register 1 $oog~$+ ,.

.-1$“’.::,:;*,.!~,+ Bit 7 6 .!,. ~ 4 3 2 1 Bit O _*i.%‘?;:$t,h,11) \,>,, ... ,&yi:

LOOPS WOMS RSRC M WAKE ILT PE PT _,.,,.~):i, .*v.:~%~~,’,,~~~l<\

RESET: o 0 0 0 o 0 0 ; .$<+$t,yw .,,. ... .~’\~+~*,’.~*.\<..:,‘ ,,*,*_{,.>.+.> ‘~} :,. Read or write anytime.

... ,},.. r*iF ,fe.,\ . .. ~.$$.s:).\,:?;\<\. ~%~.3&). ~t\3~ ,*

LOOPS — SCI LOOP Mode/Single Wire Mode Enable’ ,,$* ,.,;\. \\,)t,~,\.*

O = SCI transmit and receive sections operate normally. ‘~~$,~<$+!,.,>.;~”.$,..,+,.,,.,;..~~,,,)..

I = SCI receive section is disconnected from th,e RXD pin and the R~~,@’is available as generai

purpose 1/0. The receiver input is determined, by the RSRC ,W$ThQ transmitter output is

con-trolled by the associated DDRS bit. Both the transmitter ~ql~e “receiver must be enabled to

use the LOOP or the single wire mode. ,.::,,~\:.?>,; .$!..,

If the DDRS bit associated with the TXD pin is set during the L~,~~#= 1, the TXD pin outputs the SCI

waveform. If the DDRS bit associated with the TXD pin is}xar *ring the LOOPS = 1, the TXD pin

be-comes high (IDLE line state) for RSRC = O and high iw,a%e for RSRC = 1. Refer to Table 29.

>j;: :+, ~ %:

WOMS — Wired-Or Modefor Serial Pins _{l!\*..;,~.\>.:..:,.&,,,”*.,\}:, .,.,,:*:.,$.,.,,~{;+, *:Y

This bit controls the two pins (TXD and RXD) assoc~%$edwith the SCI section.

O = Pins operate in a normal mode with$othhigh and low drive capability. To affect the RXD bit,

that bit would have to be configurq~%~::an output (via DDRS) which is the single wire case when

using the SCI. WOMS bit still a@*,general-purpose output on TXD and RXD pins when SCI

is not using these pins. _>*,,~+tk,,*j?:_{.$,. \}~ .J.:%.t~,\, ..,

1 = Each pin operates in an ~,@~&~n fashion if that Din is declared as,an output..

5.;s_\>+::!J?:;i..!.,+.s,::,,,!

RSRC — Receiver Source _{>.,“*$...,.~}“’ptj~~

-When LOOPS = 1, the R~~~;b}fd.etermines the internal feedback path for the receiver.

O = Receiver inpu~:is&ected to the transmitter internally (not TXD pin)

1 = Receiver int~~${~,~bnnected to the TXD pin_.,\x~..\.“

~:::: ~

‘i~!:.!e,><,:: _{Table 29 Loop Mode Functions}

~.$.* , ;,J’:’,:~ \

LOOPS R:@j_.. (#~DSl WOMS Functionof Port SBit 1

0 .o:?~;~ >~“‘$a)~:l.. x x Normal Operations

1 !4,ti,,N$?p o 0/1 LOOP mode without TXD output (TXD = High Impedance)

‘1 o LOOP mode with TXD output (CMOS)

1 1 LOOP mode with TXD output (open-drain)

~<::.~~,.,,,,:!.).1 _{1 0} Single wire mode without TXD output x

“,‘i. ,$.,..’.._{.$.8 (the pin is used as receiver input only, TXD = High Impedance)} ,~)._.’

1 1 ,1 0 Single wire mode with TXD output

(the output is also fed back to receiver input, CMOS)

1 1 1 1 Single wire mode for the receiving and transmitting (open-drain)

M — Mode (select character format)

O = One start, eight data, one stop bit

1 = One start, eight data, ninth data, one stop bit

w

MOTOROLA MC68HC912B32

WAKE — Wakeup by Address Martildle O = Wake up by IDLE line recognition

1 = Wakeup by address mark (last data bit set)

[LT — Idle Line Type

Determines which of two types of idle line detection will be used by the SCI receiver.

O = Short idle line mode is enabled.

1 = Long idle line mode is detected. ,*!.,.::~.<~

In the short mode, the SCI “circuitry begins counting ones in the search for the idle line condition

jw~~-.,&., !.,,. .*,;>:?,+.:i:.:li~~. diately after the start bit. This ,means that the stop bit and any bits that were ones before th~t$~~~lt

could be counted in that string of ones, resulting in earlier recognition of an idle line. *,$:.*.i$:t,.,

[n the long mode, the SCI circuitry does not begin counting ones in the search for the idl~ti~##ndition

until a stop bit is received. Therefore, the last byte’s stop bit and preceding “1” bits ,~~~@$$affect how

quickly an idle line condition can be detected. :~+~.:l,y:~~’.:.:,J

“.:y>:i:.:? .;* PE — Parity Enable %. $i::~.’:tj, ,.~>$:,~:7+~,,

O = Parity is disabled. .,.~,,,,.:$i. ‘m.o:~:,~~,,~~<<~..~.i‘

1 = Parity is enabled. ,.,‘“*<.:.:;::_‘+.!<>+,J:>f,

t~pAvw:,Qb?

PT — Parity Type _,,*,:..’~j] -’:Q,‘**

If parity is enabled, this bit determines even or odd parity for bo~$~~~~heiver and the transmitter.

O = Even parity is selected. An even number of ones in tQ&dd$ ‘character causes the parity bit to

be zero and an odd number of ones causes the .pag~~~b~f?bbe one.

1 = Odd parity is selected. An odd number of ones i~the’~ta character causes the parity bit to be

zero and an even number of ones causes th~~~ly bit to be one.

~{.., ~,:

SCOCR2 — SCI Control Register 2 ,~ ‘*::.‘ !,~,.“,,R<$”?~ ,+. $OOC3

‘+:i\,,. a?xft$av,$,t

Bit 7 6 5 4 ‘;~>,...{,$ 3“ 2 1- Bit O

TIE TCIE RIE I ,,<q~lE “p’ TE RE RWU SBK

RESET

o

0

0

,%j:$&t&

o

0

0.

0

,:+

_\‘$’

_$:.,,

‘.

Read or write anytime. ,,,)i:.tt~f.i$$:\x, .,,>,SFJ.*:!

-:{’$,,~.~+>..,y $$<:,~y

TIE — Transmit Interrupt

Enabl@$l~#~:-0 = TDRE interruptq,~?~~~d

1 = SCI interruptlw$+b~jr equested whenever the TDRE status flag is set.

~’,!.,.

TCIE — Transmit Co~&$~lnterrupt Enable

O = TC inte#~)p@-’disabled

1 = SC~~fi~errd~t will be requested wh,enever the TC status flag is set. *S.>.,>#.~’;,)$

RIE — Rec@~&?fl~errupt Enable

&+~”i~~F and OR interrupts disabled

‘++.?YSCI interrupt will be requested whenever the RDRF status flag or the OR status flag is set.

~~ , ~>b<’: .<,(:/-?..,,,%_,,

,l&~~&.&”; Line Interrupt Enable

$s\*:t.*,’_{. .>y.),,O = IDLE interrupts disabled}

:.,<~,‘ $,$, ..;+/_{.,.,,;<,,J.,,3},y.~$, ,.~

1 = SCI interrupt will be requested whenever the IDLE status flag is set.

,::y :..

TE — Transmitter Enable

O = Transmitter disabled

1 = SC! transmit logic is enabled and the TXD pin (pofl S bit 1) is dedicated to the transmitter. The

TE bit can be used to queue an idle preamble.

RE — Receiver Enable

O = Receiver disabled

1 = Enables the SCI receive circuitry

MC68HC912B32 MOTOROLA

‘RWU — Receiver Wake-Up Control

,.

0 = Normal SCI Receiver”

1 = Enables the wake-up function and inhibits further receiver interrupts. Normally hardware wakes

the receiver by automatically clearing this bit.

SBK —

Send Break

O = Break generator off

.,

1 = Generate a break code (at least 10 or 11 contiguous zeros)

As .Iong as SBK remains set the transmitter will send zeros. When SBK is changed to zero, the current:$+~+

frame of,

ail

zeros is:finished before the TxD line goes to the idle state. If SBK ii toggled on and offf$$$~

transmitter will send 10 (or 11) zeros and then revert to.rnark idle or sending data.

!+

>J

v;

f~i,$

,,,;%r$:’

SCOSR1 — SC!

Status Register 1

~;4&c4

,.

p4* \ =,&

Bit 7 6 ‘5 4 .+.,.~+~.~.’$~l 3 ..2 1 Bit#:~:;:)~+’J ~~?$,;... \’

TDRE

TC

RDRF

IDLE

OR

NF

FE ., ?R$R$3 ~~ ~.!+!, ~ RESET: 1 .,,,’.>~..,. 1. “o 0’ 0 0 0 _.“):$),:.1.,::’:4):_~,l:y,~..::~:~ .!$-,7

The bits in these registers are set by various conditions in the SCI hard~~~~~nd are automatically

cleared by special acknowledge

sequences. The receive related flag bits ~%iWiO~Rl (RDRF, IDLE, OR!

NF, FE, and PF) are all cleared by a read of the SCOSR1 register f~ik.we~+by a read of the transmiti

receive data register L. However, only those bits which were set whG@.*Rl

_$.y

_.:~>.’,,

_,<$.,,

was read will be cleared

by the subsequent read of the transmi~receive ”data register L.:~h~:trbnsmit related bits in SCOSRI

(TDRE and TC) are cleared by a read of the SCOSR1 register~~wd

by a write to the transmitireceive

data register L.

,.{.,,

‘..t~>.

Read anytime (used in auto’ clearing mechanism). Writ~%~~~,~o’*rneaningor effect.’

..,*

TDRE — Transmit Data Register Empty Flag

>ik,?,\;.R:>

~\

New data will not be transmitted unless SCOSR1 i~$w’’before

writing to the transmit data register.

Re-set Re-sets this bit.

_~i,+...

“~$i.

,.

O = SCODR busy

~r~

,+?

,,

1 = Any byte in the transmit data reg~~~~$ transferred to the serial shift register so new data may

now be written to the transmi$%$w%egister.

>**$:$’‘$$’

TC — Transmit Complete Flag

~~<:,,$,

l!:;,~l>wq,

-P,!,,

_.!..l.t.

,.?

\<>

Flag is set when the transmittqfl$&&~&‘(no data, preamble, or break transmission in progress). Clear by

reading SCOSR1 with TC sq$~’~%hen writing to SCODR.

O = Transmitter busy$’i$’‘~*~*$s

I = Transmitter is&@~~

,.

,/,

RDRF — Receive Da,@~@ter

Full Flag

Once cleared,,lDL~,{$ not set again untilthe RxD line has been active and becomes idle again. RDRF

is set if a re@fie~ character is ready to be read from SCODR. Clear the

RDRF

flag by reading SCOSRI

with RD~F~@$~~fidthen reading SCODR.

O ~:,&,@@Rempty

l/~@~~DR full

,.

$>+$+

lDL~~,~~~&

Line Detected Flag

g.~~~eiver

idle line is detected (the receiptofaminimumof10/11

consecutive ones). This bit will not be

~~.,,~%etby the idle line condition when the RWU bit is set. Once cleared, IDLE will not be set again until after

~~

RDRF has been set (after the line has been active and, becomes idle again).

O = RxD line is idle

1 = RxD line is active

OR — Overrun Error Flag

New b~e is ready to be transferred from the receive shift register to the receive data register and the

receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit-is cleared.

O = No overrun

1 = Overrun detected

MOTOROLA

MC68HC912B32

NF — Noise Error Flag

Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR).

O = Unanimous decision

1 = Noise on a valid start bit, any of the data bits, or on the stop bit FE — Framing Error Flag

Set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCOSR1 with

FE set and then reading SCODR. ,*!.‘*{,3,

O = Stop bit detected ,&.,.-.>sg:.;y>~i<t~,.,it. ~

1 = Zero detected rather than a stop bit .:,., ,,,.> :<.,*.3,,~R“~:}..

\7.:fi_,,-\\,, ,t$”i,._..+,,.,,,:>)~~ <+~:}~.\e,

‘PF — Parity Error Flag “ ,,r ..,> \?~.a‘:**L>*,::““‘

Indicates if received data’s parity matches parity bit. This feature is active only when @k#.I&enabled.

The type of parity tested for is determined” by the PT (parity type) bit in SCOCRI. .$~”;~, ‘<

O = Parity correct h:, ~..$.,$?:”_*}!

,*<,*y:\

1 = Incorrect parity detected \*\,~y:\\.~:$,.‘k&.$$.,,,:$.,

*~t$.*.J,:~:\\ ,$sf::$”

SCOSR2 — SCI Status Register 2 _{~,\ ‘.~yi.}->:..<,:$~”,>*.,.,, _$OOC5

‘+$tt...k.r$ ...?\.,,,)}, .~’. Bit 7 6 5 4 3 2 “~4~TT Bit O ;?.?<. ~.,:i o 0 0 0 0 .*~~<&:’**. o .s.., RAF RESET o 0 0 0 0 ~ $:>0‘$$;‘“ o .J“ *:,,,:,i,+,,’ 0. 4?”.+*> ?:>::,:$.

Read anytime. Write has no meaning or effect. .,s~~ \~*,ii,

.,,<$!,, ~),,~~

RAF — Receiver Active Flag _‘:.::~1.:>,$. ,..><..‘~:~, ,-.

This bit is controlled by the receiver front end. It ~~~~~~d+;ng the RTI time period of the start bit search.

It is cleared when an idle state is detected or w~qthe receiver circuitry detects a false start bit

(gener-ally due to noise or baud rate mismatch). .. <y ‘

O =A character is not being receive~~~,

1 = A’character is being receive~,.,a‘+~tx~_{‘..$},:?,><,t::\%,,}

,/..,%:*,\

SCODRH- SCI Data Register High~{4~~,<&.~ _$OOC6

~.$’~;>,..,,<,,:~.’ Bit 7 6 ,+,W*~:$1, , , , , _{Bit O} R8 T8bva’z;+;> ‘b 0. 0 0 0 0 RESET: o ,,$$,.,, ,:~ o 0 0 0 ,$V“ :i,,’~~ o 0 :\k $+* ~,!~i, ~ ..,.:~v,{~>..>y:r,$\*

SCODRL — SCI D~,@gister Low _$OOC7

~~, *3P’ 6 _{5 4 3 2} >. 1 Bit O ~g~~y _{R6m6 R5~5 R4f14 R3f13 R2f12 fll~l RO~O} .*. ‘=’;*,>++ RES~$;~~,~ O 0 0 0 0 0 0’0 .@,t.,~.$.“ ,$:P _+*,,& ~~k~J@ceive Bit 8

i~~~%ead anytime. Write has no meaning or affect. **.*::t\

‘$$’This bit is the ninth serial data bit received when the SCI system is configured for nine-data-bit

opera-.*..“.+.*;@> ‘*,$_‘!.?.’

.. tion.

T8 — Transmit Bit 8

Read or write anytime.

This bit is the ninth serial data bit transmitted when the SCI system is configured for nine-data-bit

oper-ation. When using 9-bit data format this bit does not have to be written for each data word. The same

- value will be transmitted as the ninth bit until this bit is rewritten.

w—

MC68HC912B32 _MOTOROLA

,, ,.-.

R7f17-ROf10 — Receive~ransmit Data Bits 7 to O

Reads access the eight bits of the read-only SCI receive data register (RDR). Writes access the eight

bits of the write-only SCI transmit data register (TDR). SCODRL:SCODRH form the 9-bit data word for

the SCI. If the SCI is being used with a 7: or 8-bit data word, only SCODRL needs to be accessed. If a

9-bit format is used, the upper register should be written first to ensure that it is transferred to the

trans-mitter shift register’with the lower register.

13.3 Serial Peripheral Interface (SPI) *,\

*’::,:,,

The serial peripheral interface allows the MC68HC912B32 to communicate synchronously with perjp~~~

eral devices and other microprocessors. The SPI system in theMC68HC912B32 can operate as,? ‘~:$~ ~

ter or as a slave. The SPI is also capable of interprocessor communications in a multiple mast~;~~~rn.

,i”., >.:

When the SPI is enabled, all pins thatare defined by the’configuration as inputs’will be inp~i;.~ardless

.

of the state of the DDRS bits for those pins. All pins that are defined as SPI outputs wk~~+,outputs, $,.tQ3\;.:+$p only

if the DDRS bits for those pins are set. Any. SPI output whose corresponding DDR~. bI~# cleared can

be used as a. general-purpose input. _~*%,i:~~+1<:+}~x.,‘f**_..t,

so.~$!,:,~:, s .;,._{*, .\’i}

A bidirectional

serial pin is possible using the

DDRS as the direction contr&$~~j$*$

$y]y),:*.::.;\y\\_{,,:t~. ..} .’,.*+

13,3.1SPI Baud Rate Generation _{+::,~+:;+it,$~}..,,is$]‘>’3. ‘~.” *,,.+‘.’tl:,:\

‘“ The P clock is input to a divider series and the resulting SPl cloc~rd~ may be selected to be P divided

by 2,4,8, 16,32,64, 128 or 256. Three bits in the SPOBR reg@~$#wdfitrol the SPI clock rate. This baud

rate generator is activated only when SPI is in the master mod~~nd serial transfer is taking place.

Oth-e~ise this divider is disabled to save power. ,,+,,.!$+:..~.,e._‘?:~j..

,+y’~’+,*;.>.~. x,$ .,;\~i’(! ,<<

13.3.2SPI Operation ‘. _{:.:*;.;,.,....l<!\>l\fi..i..}‘(*J,‘~++,:.f.’

In the SPI system the 8-bit data register in the ma$~k and the 8-bit data register in the slave are linked

to form a distributed 16-bit register. When ~dat~’transfer operation is performed, this 16-bit register is

serially shifted eight bit positions by the SV~~ock from the master so. the data is effectively exchanged

between the master and the slave. Data+&*&n to the SPODR register of the master becomes the output

data for the slave and data read fro@,J~&8PODR register of the master after a transfer operation is the

MCU P CLOCK (SAME AS E RATE) ‘j DIVIDER +2 +4 +8 +16 +32 +64 +128 +256 14111111 SELECT I tttl !

I

! + -j 8-BIT SHl~ REGISTER ~

F

+, ~

SPOBR SPI BAUD RATE REGISTER

A

+1

*

SPI CONTROL + + L d & E o 0 m 3 z

v

v v

v

-MOTOROLA _MC68HC912B32

13.3.3 s output

Available in master mode only, ~ output is enabled with the SSOE bit in the SPOCR1 register if the

corresponding DDRS bit is set. The ~ output pin will be connected to the ~ input pin of the external

slave device. The ~ output automatically goes low for each transmission to select the external device

and it goes high during each idling state to deselect external devices.

Table 30 ~ Output Selection .?,...._~~.~,.,. i:.r.,..,.,....*, .\,,.,.,.(,...,{.., DDS7 SSOE Master Mode Slave Mode ;:,, ~:$?.\~,,~.?+:t+’~4.),..<,,>,,,,

~ Input with MODF Feature

“:.>

0

0

W

Input _{.,s” ~}.~,,,,}“r,:~~::?>~~..\ ““3,, ,..$

o 1 Reserved SS Input , “,.,~~~$t\i{y, .,#

..ii:”,d, syw~

1 0 General-Purpose Output = Input .(..,.*,.:>.~lt:+.J,.,/,\:,i:$::t\.

<‘

1 1

:\tk

Ss

output B Input, “qk<;:f$y

~... .,

?$::Q}~.j:\yJ:\, 13.3.4 Bidirectional Mode (MOMI or S1S0) ~T,$.‘~,l‘~~‘<a.,+.~,.<‘.,,\Ty}~~i

,::8,*{.i

In bidirectional mode, the SPI uses only one serial data pin for external d~~efitetiace. The MSTR bit

decides which pin to be used. The MOSI pin becomes serial data 1/0 (*W) pin for the master mode,

and the MISO pin becomes serial data 1/0 (S1S0) pin for the slay~’’~od~: Th& direction of each serial

1/0 pin depends on the corresponding DDRS bit.

.. \\,e~:+.~)y_,,+,,,, ,,,,,.,,,:,,_,.,:,.?:* .:,,, ., ,,,>-*T.> ,,+~. $., ,$.+ ,.+~’”

,*:t::. figure 24 Normal Mode and Bidirectional Mode

.*a ‘“::. “’F).‘ .,. ~‘..:i::t?~:. -f~~*+ , ‘is;,,_{s *?..}., 13.3:$:@’~kter Descriptions ‘%.:!

~}&~~trol and data registers for the Spi subsystem are described below. The memory address indicated

‘ ~for each register is the default address that is in use after reset. The entire512-b~e register block can

*\*<,$,l!*.,.$

.::.3,,.,‘“e_{~it,,i,p,*\\ be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. For more information}

.,{;::

:. refer to 5 Operating Modes and Resource Mapping.

SPOCRI — SPI Control Register 1 $OODO

Bit 7 6 5 4 3 2 1 Bit O

SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF

-RESET: o 0 0 0 0 1

0

0

-MC68HC912B32 MOTOROLA

Read or write anytime.

SPIE — SPI Interrupt Enable

.,

1 = Hardware interrupt sequence is requested each time the SPIF or MODF:status flag is set

O = SPI

interrupts are inhibited

SPE — SPI System Enable

O= SPI internal hardware is initialized and SPI system is in.a low-power disabled state.

1 = PS[4:7]are dedicated to the SPI function

,*!.

‘*{,3,

When MODF is set, SPE always reads zero. SPOCR1 must be written as pati of a mode fault recoy~~t~+’

,s:<.\.\..:

2,,

sequence.

_..?~,..,,

:/” !**.:J.

_,

.:)$:*

.*.*,$’

SWOM — Port S Wired-OR Mode

~\.\.> ,,~t,

.+!,,,+,\..,.

-i,...~..;,i

.-,<$~

Controls not only SPI output pins but also the general-purpose output pins (PS[4:7]) whic~$”@,$$otused

by SPI.

,,~$’.lit~.

_J:>..i’>

‘g>:;;

:’~?:$/17.:

O = SPI and/or PS[4:7] output buffers operate normally

~,+ \,.\:,.

,.:1+,,

<>*...;

1 = SPI and/or PS[4:7] output buffers behave as open-drain outputs

.**,{~..<..~Q

.,.!..]?,’

*“

‘$:\,

i?,“+’~,.;.$$.,

>,$:1

~.*,\ ~..!.

MSTR — SPI Master/Slave Mode Select

1{+..

,.,$,$,~b’

>.$}

,!.~

,r?

O= Slave mode

.bi,x.:

v~

.’!~~t?.$

,,.~~+o

*$/,i

1 = Master mode

.l~

~,’.

,\,T\ ,,

y:

‘~.

.:\::,.+$\%.$t?..

$,,.

$fva$>,

$:~\

CPOL, CPHA — SPI Clock Polarity, Clock Phase

,,$ ,/1

.,,.

~+”t..

-These two bits are used to specify the clock format to be used i~~~~ltiperations. When the clock polarity

~~~..<,

,,*,,

,.*!.,

bit is cleared and data is not being transferred, the SCK pi~bf th

master device is low. When CPOL is

set, SCK idles high. See

Figure 22

and

Figure 23. _{~:,,;::.~.!,$.:}.‘s“t%+>_,

$,}~, ‘k.

SSOE — Slave Select Output Enable

~$,

;!tt::,?J>\+T:t:\

‘*:f&\!,;$:::$:}i\L.

The SS output feature is enabled only in the maste~+~ode by asserting the SSOE and DDS7.

,,:3$

tiSBF — SPI’ LSB First Enable

\,.*.>,

_{\ ~~b?>.,}

.,~>:~ .

O= Data is’transferred most signifiqa~.bi~lirst

1 = Data is transferred least sig~~fi~~~$it first

Normally data is transferred most

~~~f~ant

bit first. This bit does not affect the position of the MSB and

LSB in the data register. Reads.?~~,w~ltes of the data register will always have MSB in bit 7.

_y\>$?.;

_,.,>>,

?:.;3>

SPOCR2 — SPI Control Regist,~R~,~~

$OOD1

,:+,: ‘~~\..*.

Bit 7

\@,,>**,,y 5

4

3

‘2

1

Bit O

0

l,,,{,+;%,$ I

o

0

0

0

SSWAI SPCO

,

RESET: o ,+,! “,,{:<,,.,~.>,;a&k o 0 0 0 0 0

,.:,, .*$_{,,.,,.,-’ .}

Read ori~{~~~~w~time.

,.,>wli:~i,

. i~,>~~

>.

SSWAI ~$~Stop

in Wait Mode

ySSl clock operate normally

;f?~ +*, ‘

+~~+il~> Halt SSI clock generation when in wait mode

,Tf?,:’!

_.,,:&.>.

_t?.~i{

_:,..

+~~b

— Serial Pin Control

O

‘~

This bit decides serial pin configurations with MSTR control bit.

-w ,.

MOTOROLA

MC68HC912B32

F

E

_NOTES:

SPCO’ MSTR MIS02 MOS13 SCK4 Ss!

o Slave Out Slave In

o SCK In SS In

1 Master In Master Out SCK Out Ss 1/0

o

Slave 1/0

1 GP1/O SCK In SS In

1 GP1/O Master 1/0 SCK Out Ss 1/0

.+:~,

SPOBR — SPI Baud Rate Register

Bit 7 6“ 5 4 3

$OOD3

,..,.,

.>*,:l{.~?p,,,,,,..,,

t+,,!1:8,,‘“*“%’:’Read anytime. Write has no meaning or effect.

‘:A$

SPIF — SPI Interrupt Request

SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SPOSR register (with SPIF set) followed by an access (read or write) to the SPI data register.

WCOL — Write Collision Status Flag

- The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated

because the error status flag can be read upon completion of the transfer that was in progress at the

w _{time of the error. Automatically cleared by a read of the SPOSR (with WCOL set) followed by an access}

MC68HC912B32 MOTOROLA

,,

.,

(read or,write) to the SPODR register. O = No write collision

1 = Indicates that a serial transfer was in progress when the MCU tried to write new data into the

SPODR data register.. :,

MODF - SPI Mode Error Interrupt Status Flag

This bit’is set automatically by SPI hardware if the MSTR control bit is set and the slave select input pin

becomes zero. This condition is not permitted in normal operation. In the case where DDRS bit 7 is set, ~

the PS7 pin is a general-purpose output pin or SS output pin rather than being dedicated as the SS inp~,>j,,

for the SPI system. In this special case the mode fault function is inhibited and MODF remains cle+~~j.~”

This flag is automatically cleared by a read of the SPOSR (with MODF set) followed by a wfit@~f$~#

SPOCR1 register. \ ‘&%*2?t?.:*+~~.:..,:. ~.+$

,.li.~

SPODR — SPI Data Register ,.:*~5:$<;~;OD~

,\&,l~t\$c:i,,~,~.,p.”

Bit 7- 6 5 4’3 2 1 _,~t?,B~%Q\,;;

Bit 7 6 5 4 3 2 1 ,~j;~t 0:’

RESET: O 0 0 0 0 0 ~{:$’+~f o

..,.$:>..-~,~~.p~,,>,:!:+

Read anytime (normally only after SPIF flag set). Write anytime (see W~%~R;te collision flag).

Reset does not affect this address. ..<$*t.,,,,i.$i.J’~+\:l1.$.,,,

This 8-bit register is both the input and output register for SPI d~&&~@ads of this register are double

buffered but writes cause data to be written directly into the ~ri~+#ifter. in the SPI system the 8-bit

data register in the master and the 8-bit data register in the ~~ve are linked by the MOSI and MISO

wires to form a distributed 16-bit register. When a data tr4~fer ‘operation is performed, this 16-bit

reg-ister is serially shifted eight bit positions by the SCK cl+*R~rdti the master so the data is effectively

ex-changed between the master and the slave. Note+t~~;@,fie slave devices are very simple and either

accept data from-the master without returning data:~~&e master or pass data to the master without

re-quiring data from the master,. _,iJ?.~$.’<

.,~s

-;T.~, #. i?,,

13.4 Pens _~:..!...,~,. ‘~$.$4,$),., ,..\\*\\ ~~j:{~..,.~,.):\,

In all modes, port S-bits PS[7:O] c~;~~&ed for either general-purpose I/O, or with the SCI and

SPI

subsystems. During reset, poti S ~~~w~e configured as high-impedance inputs (DDRS is cleared).

_.,.,~*,,

_*,*‘“+>

PORTS — Port S Data Register,,~,,~J~~~J” $OOD6

..,. .- ‘\\:i,,r..:i:l” Bit 7 6,,, $;; > ‘-’ 5 4 3 2 1 Bit O PS7 P*6+$ “ ‘ PS5 PS4 PS3 PS2 Psl Pso ... ,1,..I .,..~~:,, -.~’>i~,h. ~ ~,

Pin m ,..~a:%l+~K, MOSI MISO

Function CS*3? , ~ MOMI Slso 1/0 1/0 TXDO RXDO

~~’:~:t.,$i..~f

PORTS c~,~,pk:~’ad anytime. When configured as an input, a read will return the pin level. When

con-figured~,;&&put, a read will return the latched output data. Writes do not change pin state-when pin

confiQ~w*or

SPI

or SCI output.

A~fsr ~~el all bits are configured as general-purpose inputs.

,af~~+$ shares function with the on-chip serial systems (SPIO and SCIO).

“%*’.>

.~~#F- Data Direction Register for Pofl S $OOD7

,. t.,..,, -Tit:

,,, _{Bit 7 6 5 4 3 2 1 Bit O}

DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDSO

RESET: o .0 ‘ 0“ o 0 0 0 0

Read or write anytime.

After reset, all general-purpose l/O are configuredfor input only.

O = Configure the corresponding l/O pin for input only

-1 = Configure the corresponding 1/0 pin for output w

MOTOROLA MC68HC912B32

DDSO — Data Direction for Port S Bit 2 and Bit O

If the SCI receiver is configured for two-wire SCI operation, corresponding poti S pins will be input

re-gardless of the state of these bits. DDSI — Data Direction for Port S Bit 1

If the SCI transmitter is configured for two-wire SCI operation, corresponding port S pins will be output

regardless of the state of these bits.

,*!.

DDS2, DDRS3 — Data Direction for Port S Bit 2 and Bit 3 ,s:<.\.\..:.>..:,)-xv/,...‘*{,3,2,,

These bits are for general-purpose 1/0 only. ~i,:.+,:ls!,$_,,,,t _~“~$tx. ‘S’*

~t~.$t;::.:.*\$.\?,$ DDS[6:4] — Data Direction for Pod S Bits 6 through 4

><,*.>s:,,,,> ~_\,,.,,,.,,,Q~.~:,:,,. , If,4....

If the SPI is enabled and expects the corresponding port S pin to be an input, it,will be

~’l~~~Yregard-Iess of the state of the DDRS bit. If the SPI is enabled and expects the bit to bean ~&~R will bean

output only if the DDRS bit is set. _.’+,.\.<.?*.?~,?:!2

~{:,},,ti,:;+$t,

DDS7 — Data Direction for Pofl S Bit 7 ‘‘-?, ;fk~.\\\$,,,;~>?,~\+.,,\

In SPI slave mode, DDS7 has no meaning or effect; the PS7 pin is dedi$,~@,iasthe = input. In SPI

master mode, DDS7 determines whether PS7 is an error detect input t~.thwl or a general-purpose

or slave select output line. _\:?l:,*‘‘,:$..:~~~.!~~t~.:*.*

.i i$y..<,$..,$>;,,.

PURDS - Pull-Up and Reduced Drive for Pod S ,<\,>*l*:i<.i.*,,:.:*:y%.it.:i $OODB ,$. ,X.!,/$

Bit 7 6 5 4 3 _.>{~,~,,.-: .\,.:_,&e:.~:+: 1 Bit O

o

RDPS2 RDPS1 RDPSO oy~: ‘“PUPS2 PUPS1 PUPSO

RESET: o 0 0 0 ,i~~i,s -’+ , 1 1

.+. ‘:1: .;*N’c?_,$:,.*J$...,2

Read or write anytime. .’R!~>.,,~{!:,,~~,,~,>i~?.$

..,*._.,*\

RDPS2 — Reduce Drive of PS[7:4] $. ,*F,.

0 = Port S output drivers for bits 7 ~~o~~h 4 operate normally.

1 = Port S output pins for bits 7,.~~&~h 4 have reduced drive capability for lower power and less

noise. l,J,.,<?!~,,,i>~,,} “$J

,.:,J;!:.;,,,,I !.!+~$

RDPSI — Reduce Drive of PS[~~~&~*$J”

o = pofl S output drivqf~”~%~ts 3 and 2 operate normally..

1 = Pod S output pi~~f~ti~ts 3 and 2 have reduced drive capability for lower power and less noise.

RDPSO — Reduce Dtiv$~o~$#[l :0]

O = Port S @b~b&~vers for bits 1 and O operate normally.

1 = Port+$ o’*I pins for bits 1 and O have reduced drive capability for lower power and less noise.

,:,i;tt”~,Jy

PUPS2 — ~,u$&~oti S Enable PS[7:4]

gfij~~~nternal pull-ups on pod S bits 7 through 4.

,~$,~#%I~bfl S input pins for bits 7 through 4 have an active pull-up device. If a pin is programmed as

,.. “>/ output, the pull-up device becomes inactive.

!,.$:,,, $,~<1 ..w~:i.,../.?,:*.is

q%~l — Pull-Up Port S Enable PS[3:2]

f,:$!:+<. ‘.,> . &>,*

-?..~_,]: O = No internal pull-ups on pofl S bits 3 and 2.

$., _{1 = Port S input pins for bits 3 and 2 have an active pu1l-up device. If a pin is programmed as output,}

the pull-up device becomes inactive,

PUPSO — Pull-Up Port S Enable PSII :0]

O = No internal pull-ups on pod S bits 1 and O.

1 = Port S input pins for bits 1 and O have an active pull-up device. If a pin is programmed as output,

- the pull-up device becomes inactive.

MC68HC912B32 MOTOROLA