VHDL-Testbench as Executable Specification

(1)

Aargau , CH-5210 Windisch .

VHDL-Testbench as

Executable Specification

Michael Pichler

Zentrum für Mikroelektronik Aargau

Fachhochschule Aargau, Steinackerstrasse 5, CH-5210 Windisch

Web: www.zma.ch - E-mail: m.pichler@zma.ch

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Overview

–

Project Information

–

Project Description

–

Project Organization

– Verification Concept

– General Aspects

– Project Specific

(3)

Aargau

, CH-5210

Windisch

.

Abbreviations

ASIC

Application Specific IC

BFM

Bus Function Model

DUT

Design under Test

FPGA

Field Programmable Gate Array

SDF

Standard Delay Format

VHDL

VHSIC Hardware Description Language

VHSIC

Very High Speed Integrated Circuit

VITAL

VHDL Initiative towards ASIC Libraries

zma

Ascom

Used Colors:

Design

Verification

or

(4)

Project Context

uP

swidec

H8M

H2M

Port A

Port B

serial

Interface

Ts0 Ts31 Ts0 Ts2 Ts1 Ts127 Ts0 Ts3 Ts124 Ts125 Ts126 Ts127 Ts0 Ts31

Frame

H8M

H2M

(5)

Project Implementation

FPGA

Fast

Prototyping

ASIC

Bus Interface DU/DD Registers DD Path DU Path Generate Clocks Ports and Serial Interface Collision Checker & 0 0 0 & 0 0 0

swidec_top

swidec

nand_tree

io_block

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Layout

Project Team

System Know-how

Specification

Verification

Project Management

Design

Trainer

(7)

Overview

– Project Information

– Project Description

– Project Organization

–

Verification Concept

–

General Aspects

–

(8)

Aargau

, CH-5210

Windisch

.

Growing Design Verification

Investment

Design Complexity

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Aargau

, CH-5210

Windisch

.

Costs of design errors

Time to fix a bug

Block

Module

System

(10)

Aargau

, CH-5210

Windisch

.

Three different Testbench

Architectures

DUT

Classical

Testbench

Stimuli Generator

Output Checker

BFM

1..N

DUT

Monitor

1..N

Testbench

Control

Reference models

DUT

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Verification Environment

Design

System Design

Renoir

Testbench

Renoir / BestBench

VHDL Simulator (ModelSim)

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Aargau

, CH-5210

Windisch

.

General Verification Aspects

Design Complexity

Time to Market

Time to fix a bug

Block

Module

System

Design integration stage

DUT

Classical

Testbench

BFM

1..N

DUT

Monitor

1..N

Testbench

Control

Reference models

Design

System Design

Renoir

Testbench

Renoir / BestBench

VHDL Simulator (ModelSim)

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Design Flow (1)

Specification

FPGA Place&Route

FPGA Synthesis

Structured Design

Structured Analysis

Testbench Design

RTL

Prelayout

Postlayout

DESIGN

VERIFICATION

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Design Flow (2)

ASIC Place&Route

ASIC Synthesis

Re-Design

Testbench Re-Design

RTL

Prelayout

Postlayout

DESIGN

VERIFICATION

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Testbench

DUT

Classical

Testbench

Stimuli Generator

Output Checker

• Clock 8.192 MHz

• H8M

• H2M

• µ

C-Interface

• Serial Interface

• Two 16-bit Ports

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Statistics

Total [h]

0

100

200

300

400

500

600

700

SpecificationTe stben ch Structured Analysis Test Concept Struc tured Des ign Test Design Desig n To p Sh eet Synthesis ATPG

ClockTree SynthesisPrelayout Verification Layout

Postlayout Verification_{Vendor Netlist Transfer}

Testprogram Docu men tation Consulting Training Projectmanagement Travel

Design Kit Education nicht verrechenbar

Design

Testbench Design

RTL Verification

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J

Conclusions

– “First Time Right”

– One Testbench for all

simulations

– More verified features

implemented than needed in

the first hardware version

– Project Termination on time

and on budget

– Successful co-operation

… Ascom is satisfied.

(18)

Aargau

, CH-5210

Windisch