Design and Simulation of Low-Power Reconfigurable RCA and CLA by Using DMFA and HBFA

Design and Simulation of Low-Power

Reconfigurable RCA and CLA by Using DMFA and HBFA

M.Manikandan

and Shiju C Chacko

ME VLSI DESIGN/KCG college of technology/annauniversity/Chennai,india [email protected]

Assistant professor/KCG college of technology/Chennai,india [email protected]

ABSTRACT

Low power consumption is one of the important feature of every portable consumer electronics products in the market today (like smartphone, smart watches, tablets, cameras etc.). These devices employ various digital signal processing techniques for multimedia, image processing, wireless communication applications. In many of these applications, human beings can extract useful information even with a slightly erroneous output. These algorithm does not need very extract numerical outputs. So, several approximate and hybrid adders are used in these algorithms. This project proposes adder designs which can be used to achieve very high throughput with significantly low power consumption over the conventional adder designs. The proposed adder designs are dual mode full adder(DMFA) to implement accurate and approximation mode and a normal hybrid full adder(HBFA) to implement RCA and CLA these adders are designed using 130 nm technology node with Cadence Virtuoso simulation tool.

Keywords: low-power, approximation adders, hybrid adders, dual mode full adder, power reduction.

1. INTROUDUCTION

Now a day’s low power consumption, minimum delay and area are very important for the IC design. There are three types of power consumption in VLSI circuits they are short circuit power, static power and dynamic power. Short circuit power dissipation is produced during switching of NMOS and PMOS transistors. The static power dissipation varies with technology. The dynamic power dissipation is produced during the charging and discharging of capacitance. In real time applications, electronic devices such as mobile phones, laptop etc. require power efficient VLSI circuits. In this paper we propose approximation and GDI technology for application specific integrated circuit like image and video compression.

This approximation adders are used for floating point number system. This paper discusses reconfigurable RCA and CLA by using both approximation and GDI technology. The proposed architecture has very less transistors used. The DMFA is designed by using approximation adder and HBFA is designed

by using GDI technology. Replacing the full adder cell by the DMFA and HBFA designed reconfigurable RCA and CLA.

The both RCA and CLA are have very less transistors so it have less power consumption.

The approximation method is introducing large amount of power consumption and introducing less error in output. This approximation method replacing the adders with approximate output. We used gate diffusion (GDI) technology for implementing hybrid adder. It is used for high speed and low power electronics design. In this method only 2 transistors are used for designing AND and OR gates and 4 transistors are used for designing EX-OR gate. By using these technologies we designed a low power reconfigurable RCA and CLA.

2. APPROXIMATION ADDERS

2.1. Approximation 1:

To get an approximation adder with less transistor, low power application we started to reduce transistors from the digital

circuit one by one. The approximation 1 is having 16 transistors and it introduces one error in Cout and two errors in sum.

Fig-1: Approximation 1 2.2. Approximation 2:

The approximation 2 schematic is designed from approximation 1 and the transistors are reduced from 16 to 14.

In this approximation 2 schematic Cout has no error but 2 errors in sum output.

Fig-2: Approximation 2 2.3. Approximation 3:

The approximation 3 schematic is designed from both approximation 1 and approximation 2and it has 11 transistors.

The approximation 3 introduces one error in Cout and three errors in sum output.

2.4. Approximation 4:

In approximation 4 the Cout=A and sum=B for six out of eight cases. The approximation 4 have 11 transistors and it have two errors in Cout and three error in sum..

Fig-4: approximation 4

3. DMFA and HBFA

Fig-5: Dual Mode Full Adder (DMFA)

The block replaces the full adder cell by DMFA and it is operate either approximation or accurate mode by using APP signal. The power gating technology is used for switching the DMFA as either approximation or accurate mode. If the APP signal is active high the DMFA is working as approximation mode and the APP signal is active low the DMFA is working as accurate mode. By using the approximation technology the DMFA introduce less power consumption compared to original full adder.

The gate diffusion input (GDI) logic is used for create a HBFA and it is more efficient than normal fulladder.Basic

transistors for EX-OR gate. By replacing all the basic gates in original full adder HBFA is obtained. HBFA operates either approximation or accurate mode by using APP signal... If the APP signal is active high the HBFA is working as approximation mode and the APP signal is active low the HBFA is working as accurate mode. By using the approximation technology the HBFA introduces less power consumption compared to DMFA and original full adder.

Fig-6: Two transistor AND Gate and two transistor OR gate

Fig-7: Four transistor EX-OR gate

4.8-BIT RECONFIGURABLE RCA and CLA

Fig-8: 8-bit reconfigurable RCA block.

Fig-9: 8-bit reconfigurable cla block

5. RESULT AND OUTPUT

Both Approximation Dual mode full adder (DMFA) and hybrid full adders are implemented and the same have been used for Ripple carry adder (RCA) and Carry look ahead adder (CLA) implementation. It has been seen that the power consumption is reduced in RCA and CLA respectively by approximation DMFA and HBFA. Required waveforms and tabular forms are shown below.

Fig-10: output wave form for RCA using DMFA

Fig-11: output wave form for RCA using DMFA

Fig-12: output waveform for RCA using HBFA

Fig-13: output waveform for CLA using HBFA

ORIGINAL FULL ADDER

BFA

153.0 e^-9 185.4 e^-6 73.06e^-9 Table-1: power consumption of full adders

OF RCA USING DMFA

OF RCA USING HBFA

2.233 e^-9 1.937 e^-6 15.58e^-9 Table-2: power consumption of RCA

ORIGINAL CLA

POWER

CONSUMPTION OF CLA USING DMFA

POWER

CONSUMPTION OF CLA USING HBFA

9.344 e^-9 8.577 e^-6 5.84e^-9 Table-3: power consumption of CLA

6. CONCLUTION

This paper proposes reconfigurable RCA and CLA with less transistors. These adders are used for video encoding. The approximate adders and GDI technology architecture are used in MPEG encoder that optimize power consumption while maintaining the output quality of different input videos. These architectures have low power consumption, less delay and minimum area requirement.

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