Model-based system-on-chip design on Altera and Xilinx platforms

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CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT

Model-based system-on-chip design

on Altera and Xilinx platforms

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Agenda

3T Company profile

Technology

Design process

Tooling

Gatso radar tracking SoC solution

Conclusions

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Company profile

Electronics & Embedded software 50 employees

Offices in Enschede (HQ) and Eindhoven

Co-development, Manufacturing, Innovation & Support Customer specific solutions, from idea to phase-out

Analog/digital electronics, FPGA/SoC, Software 3T: leading for more than 30 years

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Partners for FPGA/SoC design

Altera Design Service Network Partner Xilinx Alliance Program Partner

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Agenda

3T Company profile

Technology

Design process

Tooling

Gatso radar tracking SoC solution

Conclusions

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Technology

Field Programmable Gate Array

Enormous capacity and performance Real-time / deterministic

Parallel processing power (DSP, computing algorithms) Single chip

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Technology

1985: Xilinx XC2000

1998: Xilinx Spartan / Virtex 2002: Xilinx Virtex-II Pro (PPC) 2010: Xilinx 7-series

2011: Xilinx SoC

2014: Xilinx UltraScale 4M LC FPGA history

1984: Altera EP300 (EPLD) 1992: Altera Flex 8000

2000: Altera ARM-based Excalibur 2002: Altera Cyclone / Stratix

2007: Altera Arria series 2013: Altera SoC

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Technology

Easier programming Easier data handling

(Real-time) Operating Systems Software protocol stacks

Libraries, components, references CPU benefits

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Technology

Processor IP (HDL) Altera NIOS II Xilinx MicroBlaze Performance ~300 DMIPS Hardware accelerators FPGA soft-core solution

Your design here

TCM D-MEM TCM I-MEM CUSTOM INSTR IF I$ D$ INT CNTRL JTAG DEBUG HW BP I & D TRCE TRCE PORT Debug EXP CNTRL MMU MPU

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Technology

Less CPU performance than e.g. Cortex-A industry standard Increased FPGA resource utilization

Decreased FPGA performance Soft-core drawbacks

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Technology

Altera and Xilinx adopt ARM Cortex-A industry standard Dual core ARM Cortex-A9 processing system

64-bit Quad core ARM Cortex-A53 next generation Microsemi (Actel) FPGA/Cortex-M3 SoC

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Technology

FPGA and CPU combined Increased reliability

Higher flexibility

Improved system performance Lower system cost

Faster time-to-market SoC benefits

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Technology

Dual ARM Cortex-A9 1 GHz operation

2500 DMIPS / core Software SDK

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Technology

Dual ARM Cortex-A9 1 GHz operation

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Technology

Processor IP (HDL) Altera NIOS

Xilinx MicroBlaze Xilinx vs Altera SoC

Item Xilinx Zynq Altera SoC

On-Chip RAM 256 kB 64 kB

Boot Sequence

Processor first Processor first or FPGA first or simultaneous

Analog Mixed Signal (ADC) Yes No

Interconnect FPGA to ARM 4x 64 bit high performance

2x 32 bit general purpose 1x 128 bit high performance

Interconnect ARM to FPGA

2x 32 bit general purpose 1x 128 bit high performance 1x 32 bit low latency

Interconnect FPGA to SDRAM

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Agenda

3T Company profile

Technology

Design process

Tooling

Gatso radar tracking SoC solution

Conclusions

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Design process

Traditional model

Criticized by Agile/Scrum fans Feedback in late stadium

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Design process

Model is specification Multidisciplinary Continuous verification Code generation Co-simulation

Tuning (quick iterations) Model-based design

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Agenda

3T Company profile

Technology

Design process

Tooling

Gatso radar tracking SoC solution

Conclusions

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Tooling

Model-based design Matlab / Simulink

Embedded coder / HDL coder

Altera & Xilinx FPGA and SoC target Vision, DSP and control systems

Focus on code generation (C/C++, HDL) 1million users

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Tooling

HDL Coder

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Tooling

Not as simple as just pressing the button HDL Coder Workflow Advisor

Synthesis, MAP, timing analysis Pipelining, delay balancing

Resource sharing Black boxing

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Tooling

Xilinx Vivado

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Tooling

Altera Quartus II

SoC fully integrated in Quartus II Configure and connect HPS in Qsys

AXI and Avalon busses can connect together Eclipse based SoC EDS

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Agenda

3T Company profile

Technology

Design process

Tooling

Gatso radar tracking SoC solution

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Radar tracking module

High performance analog front-end for signal conditioning radar signals System on Module with Xilinx Zynq Z-7020

C/C++ code for radar tracking algorithms generated via Model-Based Design using MatLab and Simulink

Digital Signal Processing in Zynq FPGA fabric eCos RTOS and bare-metal on Zynq ARM cores Co-development / Manufacturing

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Radar tracking module

System design

- Golden Matlab model provided by customer Software design

- Cortex-A9 in Asymmetric Multi Processing (AMP) - eCos RTOS and bare metal radar algorithms

- Generated C code (Matlab) for radar algorithms Hardware design

- Xilinx IP Integration (FFT) with Vivado - Custom IP Integration with Vivado - Gbit Ethernet UDP in hardware Design overview

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Radar tracking module

Vivado IP Integrator

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Radar tracking module

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Radar tracking module

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Radar tracking module

Generate FPGA image

(pre-loader / bootloader configures FPGA) Export hardware platform for SDK

Generate BSP from hardware platform Hardware / software interface

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Radar tracking module

RTOS for real-time requirements

eCos available for System On Module (SOM) RTOS usage avoids rewriting Matlab algorithms

Second CPU reserved exclusively for data processing Software design

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Altera Cyclone V SoC demo

Visit the EBV-Altera booth #60

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Conclusions

SoC benefits ■ higher performance ■ Flexibility ■ lower costs ■ faster time-to-market Multidisciplinary

Model-based design highly suitable for SoC design High-level SoC design tooling under development Stay with your FPGA vendor

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