S 18
ELECTRONIC INTERLOCKING
Issued in November 2009
INDIAN RAILWAYS INSTITUTE OF
SIGNAL ENGINEERING & TELECOMMUNICATIONS
SECUNDERABAD - 500 017S-18
ELECTRONIC INTERLOCKING
CONTENTS
Drafted By P. Raju, IMS-2 , S.V.K. Hanuman, IES-5 Checked By Jyotirmoy Ray, Asst Prof /Sig
Approved By Ch. Mohan, Sr. Prof / Sig DTP and Drawings P.V. Surya Narayana, JE I (D) No. of pages 145
Date of Issue November 2009
Version No A4
© IRISET
http://www.iriset.ac.in
S. No Chapter Page No
1 Introduction to Electronic Interlocking 1
2 MICROLOK-II EI system 14
Annexure-I Electronic Interlocking Spec. No: RDSO /
SPN / 192 / 2005 49
Annexure-II Items of Microlok-II EI system (Centralised
version) for a typical 4- Road Station 65
Annexure-III Items of “ All Indoor Works for provision of Microlok-II EI system (Distributed version with OFC) at Stations of Indian Railways”
70
Annexure-IV Technical Specifications of E.I. 72
Annexure-V Failure summery of Electronic Interlocking
system at Stations of Indian Railways 81
Annexure-VI Factory Acceptance Test and
Site Acceptance Test of Microlok II 85
Annexure-VII SIMIS S EI system 101
Annexure-VIII ESA11- IR Electronic Interlocking System
Manufactured by AZD Praha 122
Annexure-IX GE system of Electronic Interlocking 131
Annexure-X Pre-commissioning Checklist 136
Annexure-XI Review Questions 144
“ This is the Intellectual property for exclusive use of Indian Railways. No part of this publication may be stored in a retrieval system, transmitted or reproduced in any way, including but not limited to photo copy, photograph, magnetic, optical or other record without the prior agreement and written permission of IRISET, Secunderabad, India”
INTRODUCTION OF ELECTRONIC INTERLOCKING
CHAPTER 1 : INTRODUCTION
1.1 Introduction of Electronic Interlocking :
The era of interlocking started with mechanical lever frames. As the size of yards & train movements increased, size of lever frames also increased. These lever frames not only increased in size occupying more space but also required intensive maintenance. With the advent of Electro-mechanical relays, these lever frames gave way to relay interlocking based installations. This development resulted in relatively faster operation, fail safety in operation and reduced size of buildings required for housing of interlocking installations. With further increase in traffic and expansion of railway network, large number of Route Relay Interlocking and Panel Interlocking installations were commissioned.
Route Relay interlocking (RRI) and Panel Interlocking (PI) installations use Electro- mechanical relays requiring complex wiring and Inter-connections. The wiring diagrams for such installations run into hundreds of sheets. Individual relays, wiring and interconnections along with thousands of soldered joints are required to be physically examined and certified. This exercise requires traffic blocks of long durations and large manpower to manage the traffic during blocks. Even for small yard re-modeling like addition of a loop line, all the above activities are required to be redone. Therefore, the advantages of relay based interlocking installations are being nullified.
With development of modern fault tolerant and fail safety techniques, electronics and particularly microprocessors have found acceptance in the area of railway Signalling world over. Railways in advanced countries of Europe, North America & Australia have gone for large scale introduction of microprocessor based Electronic Interlocking system (EI). This system occupies considerably less space, consumes less power, is more reliable and is easy to install and maintain. Also, initial commissioning & changes due to yard re-modeling can be carried out in negligible time requiring skeleton manpower for traffic management during the blocks.
EI is a computer based electronic interlocking system, used for controlling points, signals, level crossing gates etc, through a centralized control panel or through VDU, like existing relay based/ mechanical interlocking systems. (Microprocessor or Micro controllers are used in EI’s.) .
Based on a proposal for development of Electronic Interlocking System, submitted by IIT Delhi to DOE, a project was started at IIT Delhi in July 1983. Two Officers from Railways were posted on this project to IlT, Delhi. Two industries (M/s DCM & CGL) were also associated in development and fabrication of the prototype. A design of the system was evolved in March 1985. The design was evaluated through software simulation at IIT Delhi and a prototype based on this design was fabricated in 1987. RDSO and DOE funded the project for design, development and prototype fabrication jointly. The prototype was installed at Brar Square Station of Northern Railway for field evaluation. Based on field trial results, it was decided by Railway Board to manufacture four engineering models incorporating necessary improvements. Railways and DOE funded these jointly on 50:50 basis. Thereafter, design and fabrication of SSI Mark-II system was taken up by RDSO in association with lIT, Delhi.
Brief history of EI s in Indian Railways is follows.
(a) First EI (Microlok I ) is installed at Srirangam (SR) in 1987.
(b) First indigenous EI – Installed at Brar Square (NR) – (Parallel operation)-1987-88 (c) First indigenous EI – Installed at Dushkheda (CR) – Stand alone – October, 1995 -
DCM.
(d) Second indigenous EI – Installed at Bhadli (CR) – Stand alone – March, 1997 - CGL.
(e) Third indigenous EI – Installed at Uppugunduru (SCR) – Stand alone – Warm standby - April, 1998 - RPIL.
More than 350 EI have been installed in Indian Railways so far of various makes and 75 more in various stages as on 2009-10.
1.2 Advantages of Electronic Interlocking System:
(a) System can be tested at factory level using simulation panels.
(b) Non-Interlocking period is less (Typically few hours instead of few days.) both for initial installation and also for yard alterations (which can be done using application software compiler which is user friendly.)
(c) Modular in design and easy for maintenance, thus requiring less staff . Expertise of hardware and software is not much needed for maintaining the equipment at initial stage.
(d) Requires less number of relays - vital EI replaces interlocking circuits Thus less space required for signal equipment room (Relay rooms).
(e) Less power supply as compared with existing PI/ RRI’s. Less failures, less wiring, less soldering, less complexity in the circuit.
(f) Enables usage of OFC (with Object Controller) which reduces requirement of Copper cables , their cost & maintenance.
(g) Remote operation of signals, points, and level crossings controls is feasible. Thus Compatible with centralized traffic Control.
(h) All EI’s are designed and manufactured as per the international safety committees – such as CENELEC STANDARDS (European countries).
(i) Standard of safety and reliability is higher as compared with existing relay interlocking systems (PI/RRI).
(j) Datalogger / Event logger is an integral part of EI.
(k) Self-diagnostic in feature: i.e. error code/ alarm code messages will be displayed on display cards or on the front panel of printed circuit boards. Hence easy for rectification of failures and reduces the failure duration.
Policy on type of Interlocking to be adopted :
Board has decided the following policy to be adopted on IR vide Board’s letter Nos. 2003/Sig/G/5 dt. 10-09-2003 and 2003/Sig/G/5/Pt. Dated 30th January, 2006
Up to 50 routes Relay based interlocking of Metal to Carbon or Metal to Metal type according to the expertise available on the railway.
(In special cases, EI may also be adopted in installations below 50 routes on a case to case basis. Such proposals for EI at signalling installations below 50 routes have to be justified on a case to case basis based on life cycle cost including capital cost, annual
maintenance cost, depreciation provision, saving due to avoidance of repeated relay wiring due to anticipated yard remodeling etc. and concurrence of the associate finance obtained.)
50 to 200 routes Electronic interlocking.
Above 200 routes
RRI with relay based interlocking of Metal to Carbon or Metal to Metal type according to the expertise available on the railway.
( Note : Bd has directed RDSO to finalise new Specification for EI for above 200 routes also vide Lr No .2008/SIG/SGF/4 /EI /GEN dt 29/07/09)
VARIOUS TERMS USED IN E I
1.3 Various Terms used for EI’s:-
(a) CPU – Central Processing Unit ( Micro processor or Micro controller)
(b) RAM – Random Access Memory (used for vital data processing and event / error logs)
(c) EPROM –Erasable Programmable Read Only Memory. (used for storing Executive and Application software)
(d) EEPROM – Electrically Erasable Programmable Read Only Memory. (used for storing Executive and Application software)
(e) OBJECT CONTROLLERS (OC):
(i) Object controller is the equipment which drives the field function through conventional Relay or directly through its own electronic circuitry. It also takes inputs from the field.
(ii) Object Controllers drive the field gears (Points, Signal etc.,) through relays and take feedback (input) from various field gears (Track, Point Indication, Aspects etc) through concerned relay contacts.
(iii) Object Controllers are used as slave unit of Main system .
(iv) Object controller and Main system can be connected by copper cable or Optical Fiber Cable (OFC) or wireless.
(v) By using Object Controllers Main signalling cables between Equipment Room (Relay Room) and Location Box of field functions can be eliminated.
Different types of Electronic Interlocking Systems currently used in Indian Railways. Manufacturer MODEL RDSO/SPN/ 192/2005 clause No Hardware Redundancy Software Diversity Standby arrangement
Some of the installations
Hot-standby
Warm -standby
US & S MICROLOK-II 7.1 (a) NO YES NO YES
ECoRly, Walter division of Kottavalsa - Vizianagaram Palasa section, Pundi,
Naupada, Kotabomalli, Tilaru, etc.,
SIEMENS
SIMIS S (See Annexure-VII)
- NO YES YES YES
SCRly, Mahaboob Nagar (HYB division);
WRly, Rajkot Division of Sabli Road, Leelapur Road, Lakhtar, Bala Road, Vani Road, etc., WESTING
HOUSE WESTRACE 7.1 (a) NO YES YES YES
SERly, CKP division, Mahalimarup station. AZD-PRAHA ESA 11- IR (See Annexure-VIII) - 2 out of 2 YES At control level Processor At command level and I/O cards level processor cold stand by
SC division, BZA-BBQ Section SCRly,-12 Nos
GE
VHLC (See Annexure-IX)
7.1(b) YES YES NO YES CRly, PA division, KOP-KRD
section, SNE, Shirwade, etc.,
ALSTOM ASCV
-SMARTLOK - NO YES YES YES DMRC
KYOSAN KB-5 2 out of 2 NO
On BRC Division, Western Railway, 7 Kyosan Systems of have been installed in 2005-2008
CLASSIFICATION OF EI’S
1.4 Classification of EI’s:
Depends on redundancy EI’s are classified as :
(a) Software Redundant. (b) Hardware Redundant.
1.4.1 Single Hardware with software redundancy.
Ex: (i) MICROLOK -II US&S.
(ii) WESTRACE – WESTING HOUSE
(iii) VPI – Vital Processing Interlocking – ALSTOM. (iv) ASCV (SMARTLOK) – ALSTOM.
(v) SIMIS S - SIEMENS EI
With this configuration hot standby or warm standby with auto changeover arrangement is required.
1.4.2 Dual Hardware with Hardware redundancy – 2 out of 2 system.
Ex: (i) VHLC – GE Transportation (ii) SICAS S5 – SIEMENS EI (iv) ESA 11 – AZD Praha
(vi) ESA 12 – AZD Praha
(vii) EBI LOCK 850 – Bombardier Transportation.
With this configuration hot standby or warm standby with auto changeover arrangement is required. Software used in both hardware may be identical or diverse.
1.4.3 Triple Modular redundancy - Hardware redundant - 2 out of 3 system
Ex: (i) ALSTOM – SSI
(ii) SIMIS –W - SIEMENS (iii) SICAS – SIEMENS (iv) ESTWL90 – ALCATEL
In this TWO out of THREE hardware (identical) system Software used in hardware may be identical or diverse.
1.5 TYPICAL HARDWARE USED IN EI
1.5.1 Any computer-aided systems require the study of both hardware and software of the system. Study of hardware involves the study of components; printed circuit boards (PCB’s) provided in the computer aided Signalling system. Software (Program) is a set of instructions given to a microprocessor (computer).
A brief description of common hardware features for different Electronic Interlocking Systems are discussed as follows.
1.5.2 Common Features of Hardware:
(a) Electronic Interlocking System is a microprocessor based electronic device with fail-safe information processing used in place of conventional relay interlocking systems.
Fig.No.1.1
(a) Input Cards :
All the field conditions (i.e. Field relay contacts) are connected to these input cards of EI system.
The maximum inputs capacity of each RI card will depend on design of the RI cards by different manufacturers. The total number of inputs will depend on the yard layout.
Total inputs means: (i) Field inputs : ECRs, TPRs, NWKR etc. (ii) Panel inputs : GNs , UNs, NWNs, RWNs, etc. (iii) Read back inputs : HR, DR, WNR, WRR etc
Opto couplers are provided to isolate field optically from the system in Input cards. These cards will read the conditions of inputs and passes the information to EI system.
COMMON FEATURES OF HARDWARE (b) Processor card:
This card is also called as central processing unit card of the System. This is provided with microprocessor, RAM, ROM, EPROM, EEPROM Memory IC’s.
These EEPROMS or EPROM’s (ROM’s) are programmed with software required for executing the system commands.
System software consists of the following:
--
-- Executive software programmed in system EPROM’s
--
-- Application software programmed in DATA EPROM’s.
Executive Software Application Software.
This software is common to all EI’s for the same company manufacturing.
This software is specific to each station. Different for different stations.
Factory installed software This is as per table of control of specific station
Performs all operations Can be installed at site by signal engineers.
Cuts off vital supply voltage to output relays, in case of unsafe failures.
Logic installed through Boolean expressions or user-friendly equations.
In all EI installations, DATA EPROM’s are to be replaced with new DATA EPROM’s at the time of yard alteration works. i.e. yard data as per new table of control software is to be programmed in the EPROM’s
For doing yard alterations as per the new table of control (interlocking) EI compiler software is used. Some manufacturers are providing EEPROMs, in which program can be erased electrically and reprogrammed with new software as per new changes using a debug port.
Function of CPU Card :
This card will execute the commands given by the user (station master/panel operator). Whenever the panel operator operates the push buttons, the relevant push buttons will be operated. Processor card will sense the operation of the panel operation of the panel operator (through inputs cards) and process according to the program available in EPROMS and finally gives output if the conditions are favorable (i.e., field condition relays are favorable as per principle of interlocking).
The output voltage generated by the CPU card will be connected to Relay output cards. Before sending the output-to-output relays safety checks will be done internally.
Output card (Relay Drive Card):
This card receives the output of CPU card as input and picks up relevant output relay as per the panel operators’ request.
The output of this card is terminated on phoenix terminals from there the output relays are connected.
1.5.3 Basic Principle of Hardware design :
The Basic principle of design is shown in Fig.No.1.2. Input/output cards, and CPU card with RAM and ROM are inter connected.
Fig No: 1.2
System Bus for information (data) exchange. Input cards gives information of all inputs to system Bus. CPU card will read the status of inputs and output cards are connected to output relays for operating the circuits (i.e., signal lamp circuit, point operation circuit, CH slot circuit etc). CPU will execute the panel commands as per the program stored in the memory chips. During execution of commands it reads the status of all inputs and writes on the RAM. After processing the interlocking logic the output is written in RAM and then according to a fixed program, these are written to the output registers of the output cards through which output relays are actuated.
1.5.4 Safety and Reliability of Hardware :
Prime objective of EI design for Railway Signalling shall be, to obtain fail safe features similar to that obtainable in relay interlocking systems which are already existing.
Microprocessor based equipment cannot be designed to work on fail safe principle at all times. Therefore, reliability has a much more importance role to play which is achieved by redundancy.
Fail-safe EI system can be obtained only when it is made possible to detect any fault in the system instantly on occurrence to apply remedial measures. The output of the system should be cut off whenever the system detects any unsafe condition. So, all the EI’s should have self-diagnostic features so as to achieve fail to safety condition.
To ensure safety and reliability there are three approaches to the hardware (redundancy) design of EI’s globally.
(a) Single processor system – with extensive safety checks. (b) System with redundancy (two out of two) – failsafe
TESTING AND VALIDATION
1.6 TESTING AND VALIDATION
Testing and validation of a microprocessor based safety system is carried out in four stages as described below:
Stage-1 Theoretical design of the hardware and program structure of the software are
examined for reliability and fail-safety at the initial design level.
Stage-2 Each card or the circuit module of the hardware is tested under normal as well
as fault conditions. In the case of software, each routine is tested with diverse test data.
Stage-3 Overall system, after integration of hardware and software is tested under
different input data conditions. Testing at this stage can be carried out by simulation for accelerated testing using computers.
Stage-4 Exhaustive field trials of the equipment is conducted under the field conditions.
1.7 REQUIREMENTS FOR ORDERING OF ELECTRONIC INTERLOCKING SYSTEM
While ordering EI, purchaser is required to furnish the following documents to the supplier:
(a) Approved Interlocking Plan
(b) Approved Panel / Front Plate Diagram (c) Selection table.
After installation at the station, functional testing shall be done by the purchaser as per the Selection table.
1.8 CRITERIA FOR THE SELECTION OF EI SYSTEM
The main criterion for the selection of EI System is its reliability, availability, maintainability & safety apart from meeting full functional requirements.
The main features are:
(a) System should meet functional requirements and have future expandability.
(b) Meet the requirements of environmental conditions, electromagnetic interference, etc.
(c) System should be user friendly and economical (example – object controller for yards).
(d) System architecture should be such as to give very high overall availability while ensuring high degree of safety.
(e) System validation to international standards to meet safety integrity level 4 (defined in CENELEC Standards).
To meet above main requirements, various architectures have been suggested in Para 7.1 of the specification No. RDSO/SPN/192-2005.
1.8.1 Block diagrams of various available systems is given below:
(a) Single Hardware with software redundancy:
Fig : Single Processor without any Standby
SINGLE PROCESSOR WITH STANDBY (TWO EI’S CONNECTED IN PARALLEL) Fig No :1.3
(b) Dual Hardware with Hardware redundancy – 2 out of 2 system:
DUAL HARDWARE WITHOUT STANDBY Fig No : 1.4
BLOCK DIAGRAM OF VARIOUS AVAILABLE SYSTEMS
DUAL HARDWARE WITH WARM STANDBY Fig No : 1.5
DUAL HARDWARE WITH HOT STANDBY Fig No : 1.6
DUAL HARDWARE WITH OBJECT CONTROLLERS Fig No : 1.7
c) Triple Modular Redundancy (TMR) - Hardware redundant - 2 out of 3 system:
TMR WITH RELAY INTERFACE Fig No : 1.8
TMR WITH OBJECT CONTROLLERS Fig No : 1.9
VARIOUS DESIGN ASPECTS OF SYSTEM
1.8.2 Various Design aspects of the System to achieve viability & safety:
Design of electronic Railway Signalling Equipment based on processor and/or software has to ensure that safety integrity of whole system/sub-system is maintained through out the life of the equipment.
Safety integrity is specified as one of 4 discrete levels by IEC/CENELEC Standards. Level-4 has highest level of safety integrity. For Safety Integrity Level - 4, dangerous failure rate per hour for continuous mode of operation should be less than 10-10. Safety integrity of any system covers mainly two components:
(a) Systematic failure integrity. (b) Random failure integrity.
It is necessary to specify both the Systematic & Random failure integrity requirements of the system if adequate safety is required to be achieved.
1.9 European Committee for Electro technical Standardization (CENELEC) has come up with several Standards, out of which, the following are to be considered for any Electronic component – based Railway Signalling equipment.
EN 50121 --- Electromagnetic Compatibility (EMC).
EN 50126 --- Railway applications - The Specification & Demonstration of Reliability, Availability, Maintainability and Safety (RAMS).
EN 50128 --- Railway applications - Software for Railway Control and Protection Systems.
EN 50129 --- Railway applications - Safety Related Electronic Systems for Signalling.
Besides these Standards if Communication Line is used in Railway Signalling as in the case of Block Signalling or Axle Counter, another Standard.
EN 50159 --- Signalling and Communications — Safety-related Communication -- is also to be considered.
EN50126 for RAMS fail-safe systems like EI, ATP, AFTC are verified and validated to SIL- 4 standard of EN50129 and EN50128.
CHAPTER 2: MICROLOK - II - EI SYSTEM
2.1 Introduction:
Microlok is a trade name of US&S currently known as Ansaldo STS India Pvt Ltd. Initially Microlok I was introduced in early 1990 s . The current version is Microlok II , which is a multipurpose monitoring and control system for line side interlocking equipment.
With this system we can have Direct control of wayside signals, Control and monitoring of Point Machine, Control and monitoring of track circuits Vital communication to other compatible interlocking systems and Cab signalling.
The hardware used in Microlok II (MLKII), various aspects of design, installation, testing, commissioning and maintenance of MLKII with the update post commissioning changes in yard is detailed as under :-
2.2 Hardware used in this system: Microlok II equipment consists of : (a) Card file.
(b) CPU PCB.
(c) Power Supply PCB. (d) Vital Output PCB. (e) Vital Input PCB.
(f) Non-Vital-Input / Output PCB. (g) VCOR- Vital Cut Off Relay. (h) Wiring hardware
2.3 Software used in this system:
2.3.1 Executive Software:
Executive software used in this system does the following functions. (a) Monitoring all Vital and Non-vital cards.
(b) Processing inputs, decision making and issuing commands. (c) Continuous internal and external diagnostics.
(d) Management of serial data ports. (e) Execution of application software.
All Microlok II CPU boards are shipped with executive software loaded in memory. Upgrade is possible using Maintenance Tool.
2.3.2 Application Software:
HARDWARE USED IN THIS SYSTEM
FRONT VIEW OF MICROLOK-II SYSTEM Fig No : 2.1
REAR VIEW OF MICROLOK-II SYSTEM Fig No : 2.2
2.4 Hardware: 2.4.1 Card File:
CSI card 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Vital Input, Vital Output, Nonvital I/O cards.
Power Supply card CPU card Microlok-II Card file layout
Fig No: 2.3
Each card file is like a shelf having 20 Slots to accommodate various PCBs that are used in a system. Slot nos.1 to 15 and 20 are used to accommodate Non-vital Input-output or Vital Input or Vital Output PCBs. Slot no.16&17 are used to accommodate Power supply PCB. Slot no.18&19 are used to accommodate CPU PCB. In this cardfile a mother board is available in the rear side connecting all the 20 Slots. This cardfile is suitable to mount on a 19” rack.
2.4.2 CPU PCB
Each card file to have one CPU PCB and always placed in slot no.18&19. In this card Micro Controller used is Motorola 68332 and its speed is 21 MHz.
In this card, 4 nos. of flash EPROMs of 8 MB are used to store executive and application software, Two nos. of fast Static RAM (each 64KB) are used to process the vital data and Four nos. of Static RAM (each 64KB) are used to store events and errors.
It has Five serial ports to communicate with peripheral devices. Ports 1 & 2 are RS 485 types to interface with vital control system such as MLKII. Port 3 is RS 432 type for other Non-vital control systems such as operators PC. Port 4 is RS 232 type for other Non-Non-vital control systems such as indication panel / Genesys. Port 5 is used to interface with Maintenance PC provided with maintenance tool software, exclusively for diagnostic purpose.
The main functions of CPU is described as under:
It monitors continuously status of Vital Boards. It also monitors system internal operation for faults and responds to detected faults. It processes application logic based on inputs received and deliver outputs to drive external gears. It records system faults and routine events in user-accessible memory. It monitors and controls the serial communication ports. It controls power to vital outputs through external VCOR relay.
CPU PCB
CPU Board Front Panel Layout Fig No : 2.4
Various indications/buttons available on front side of the CPU card is tabled below. CPU Printed Circuit Board ( Refer Fig : 2.4 )
Fig No:2.2
LABEL DEVICE PURPOSE
1,2 (None) 4 – Character alpha numeric displays
On site Configuration programming menus and options
3 A,B,C,D,E Yellow LED s Reserved for serial link status
4 1,2,3,4,5,6,7,8 Red LED s User- defined in application software
5 ON LINE Green LED s When lit , indicates normal system operation (successful diagnostics)
6 VPP ON Yellow LED When Lit , indicates FLASH + 5 V or +12 V programming voltage enabled (via board jumper)
7 RESET Red LED When Lit , Indicates that the
system is in RESET mode.
8 RESET Momentary Push Button When Pressed , RESETs the CPU. Also used to replace the CPU in the RESET mode.
9 MENU
L - R
3 – Position (Return to Centre) toggle switch
Used to search main program menu items shown on
displays.
10 MENU
UP- DOWN
3 – Position (Return to centre ) toggle switch .
Used to select main program menu items shown on
displays.
11 ADJUST
UP-DOWN
3 – Position (Return to Centre) toggle switch
Used to cycle through configuration values to be selected with ACTION switch.
12 ACTION
ACCEPT-REJECT
3 – Position (Return to Centre) toggle switch
Executes or Cancels
configuration value selected with ADJUST switch.
POWER SUPPLY PCB
2.4.3 Power Supply PCB:
Each card file to have one Power Supply PCB and always placed in slot no.16&17. Power supply PCB is basically a DC-DC converter that converts 12V DC input supply is +12V, -12V and +5V required for various board functioning. Based on diagnostic check by CPU, Power Supply Card receives 250Hz signal from CPU and extends supply to VCOR relay. This card provides isolated supply to internal circuit.
System Operating Power
The table below is a list of the worst-case current draws for Microlok-II system boards:
BOARD CONDITION + 5V + 12 V - 12 V
IN16 N17061001 16 LEDs 170 ma - 276ma
OUT16 N17060501 16 LEDs 155 ma 6 ma -
IN8.OUT8 N17061601 16 LEDs 150 ma 4 ma 147ma
CPU N17061301 No serial links ON 840 ma 4 ma 12 ma
CPU N17061301 Serial link ON 1000 ma 4 ma 12 ma NV.IN32.OUT.32
N17000601 64 LEDs ON 576 ma - -
Power Input to System Cardfile
Voltage Range Nominal Voltage Min. Sys. Start-Up Maximum Ripple Current Draw 9.5 to 16.5 VDC 12V dc 11.5V dc 0.5V P-P Determined by Installation (No. of signal lamps, cab carrier frequency, etc.)
Cardfile Power Supply Printed Circuit Board Outputs*
For System Cardfile PCB 5V Internal Circuits
For System Cardfile PCB 12V Internal Circuits
To VCOR Relay
+5V @ 3A +12V @1A, -12V @ 1A +12V into 400 Ω Coil
POWER SUPPLY CARD OUTPUT CARD Fig No : 2.5 Fig No : 2.6
VITAL OUTPUT PCB
2.4.4 Vital Output PCB:
Each Vital Output PCB has 16 Outputs. It is available in 12V and 24V DC applications. Each Vital Output can drive an output device such as any Q-series relay. This output relay in turn controls signals, points, crank handle, siding control, level crossing etc.
Since Vital Output drives the relay, which controls important outdoor gears, all the Vital Output boards are continuously diagnosed by a CPU. Any abnormality in any of the outputs will shut down the system to ensure safety.
The status of vital output is known from LEDs available in front of the PCB.
Vital Output PCB
VCOR Standard Vital Output
Relay card (24V) Output “X” Controlled Poly switch External Protected
Relay Output “Contact”
N24
Analog Ground
Standard Vital Output Fig No : 2.7
CPU Control
2.4.5 Vital Input PCB:
Each Vital Input PCB has 16 Inputs. It is available in 12V and 24V DC applications. Each Vital Input is assigned to read the status of outdoor gears such as Track circuits, Point detectors, Crank handles, Siding controls, level crossing etc.
Since the Vital Inputs read the status of outdoor gears, they are normally configured with double cutting arrangement using relay contacts.
The status of Vital Input is known from LED indications available in front of the PCB.
INPUT CARD Non-Vital Input-Output Card Fig No : 2.8 Fig No : 2.9
NON-VITAL INPUT/OUTPUT PCB
2.4.6 Non-Vital Input/output PCB:
Each Non-vital I/O has 32 inputs and 32 outputs in one PCB. It is available in 12V and 24V DC applications. Non-vital inputs are Panel push buttons and keys. Non-vital outputs are Panel indication LEDs, counters and buzzers.
The status of Non-vital Input/output is known from LED indications available in front of the card.
2.4.7 Vital Cut off Relay- VCOR:
Each card file will have one VCOR to ensure the healthiness of the system. VCOR has 6 F/B dependent contacts each rated for 3 Amps. When system is healthy the coil receives voltage from PS PCB, which in turn controlled by CPU. Power to Vital output board is controlled by VCOR, thus ensuring safety.
Vital Cut-Off Relay (VCOR) Fig No : 2.10
2.4.8 Lightning & Surge protection arrangements in MicrolokII
• The interfacing of CCIP with I/O gatherer cardfile is on PIJF cable. GD tubes have been provided at T1 rack for protection of Non-vital Input /output boards against surge, transient / lightning. GD tubes (EPCOS EC90) have been connected at non-vital input from panel and non-vital output to panel and grounded with system equipotential earth.
• Microlok Non Vital Output Filter is a surge protective device which protects the non vital output board from electrical surges caused by lightning or power faults in Microlok system.
• An augmented surge protection arrangement (external protection box) introduces surge suppression for the Non Vital Board output lines safeguard the system against lightning surges & other switching surges:
• Every Non Vital Board output line is provided with 30V Tranzorb (1.5KE30A) and MOV (V36ZA80). The Tranzorb is connected to the +24V DC signal line & MOV is connected to the 24V DC Common line.
• Every Non Vital Board output line is provided with GD Tube (CG2 145L) and MOV (V36ZA80). GD Tube is grounded to the earth & MOV connected to the 24V DC Common line. The RS-5 Resistor is provided in each of the output lines which is capable of withstanding 5 joules energy.
• The external protection box also provides protection to the 24V common line for every Non Vital board. Every 24V common line is provided with 30V Tranzorb (1.5KE30A) and MOV (V36ZA80). The Tranzorb connected to the +24V DC signal line & MOV connected to the 24V DC Common line. The RS-5 Resistor is provided in each of the output lines which is capable of withstanding 5 joules energy.
(* Extract of RDSO Guidelines vide L.No.STG/IH/ML dt.10.07.09)
Consequent to damage of Microlock-II EI due to lightning at a few stations on ECoR,
implementation of an earthing improvement scheme comprising of following three stages was decided. Zonal Railways and the firm were accordingly advised vide this office letter of even no. dated 14.03.2008.
Stage 01
- Shielded cable between Termination Rack and Control Panel is to be properly grounded at the Termination side.
- Microlock-II Racks which are having epoxy coating will be provided with copper foil. - Separate DC 24V supply to be used for Microlock-II cooling fan.
- Ensuring proper copper connection of Room Earth Bar and Earth points Ensuring earth resistance value <1 ohm.
Stage 02
- the serial port of one Microlock-II to another Microlock-II will be isolated (using opto-isolators) if the stations is located in high hazard lightning area (having more than 50 Average thunder Storm days per year)
Stage 03
- Provision of augmented surge protection arrangement for the non-vital output board lines in case the operating panel room (SM’s room) and the equipment room (EI room) are located in two different buildings.)
WIRING HARDWARE
2.5 Wiring Hardware:
48 Pin Address select PCB and Connector assembly is provided for Vital Input and Vital Output cards. 96 Pin Address select PCB and Connector assembly is provided for Non-Vital I/O cards. 48 Pin Connector Assembly is provided for PS and CPU PCB.
EEPROM PCB which is provided on rear side of the CPU connector to configure various serial communication ports. Keying plugs are provided in the cardfile to ensure coding to each type of cards.
PCB Wiring Connector Mounting and Address Select PCB Fig No : 2.11
2.6 Address Select PCB
It is used to address particular slot of the card file. Each address select PCB consists of 6 nos. of Jumpers. These jumper settings are unique and shall match with the definition of cards in application program. 48 Pin address select PCB is used for Vital Input and Output boards. 96 Pin address select PCB is used for Non-vital I/O boards.
PCB Jumper selection Table is given below :
2.7 Connector Assembly
Each connector assembly consists of connector receptacle (i.e. cover), guide pair to fix the connector on the cardfile & crimp contacts. Connector Assemblies are used to connect MLKII cards with Relays, relay contacts and panel with help of pre-wired cables. The 48 Pin Connector assembly is used for Vital Input and Output boards. The 96 Pin connector assembly is used for Non-vital I/O boards.
Board Order Non – Lamp Board Jumpers
1 2 3 4 5 6 1 0 0 0 0 0 1 2 0 1 0 0 0 1 3 0 0 1 0 0 1 4 0 1 1 0 0 1 5 0 0 0 1 0 1 6 0 1 0 1 0 1 7 0 0 1 1 0 1 8 0 1 1 1 0 1 9 0 0 0 0 1 1 10 0 1 0 0 1 1 11 0 0 1 0 1 1 12 0 1 1 0 1 1 13 0 0 0 1 1 1 14 0 1 0 1 1 1 15 0 0 1 1 1 1 16 0 1 1 1 1 1
KEYING PLUG
2.8 EEPROM PCB
The EEPROM PCB is placed on the 48 Pin connector assembly of the CPU PCB. The purpose of EEPROM PCB is to store Site-specific configuration data.
2.9 Keying Plug
The purpose of the keying plug is to avoid insertion of wrong type of board in card file slot. Each slot requires of 6 Nos. of keying plug and to be inserted according to type of the board. In principal keying Plug is similar to the index pin of the relays.
CARDFILE SLOT KEYING PLUG INSTALLATION
Fig No : 2.12
Card File Mother Board Keying Plug Locations :
Printed Circuit board
Keying Plug Location
1 2 3 4 5 6 7 8 9 10 11 12
CPU √ √ √ √ √ √
Power Supply (with out Panel )
√ √ √ √ √ √
Standard Vital O/P (24 v) √ √ √ √ √ √ Vital I/P (24v ) √ √ √ √ √ √ Code System interface √ √ √ √ √ √
Non- Vital I/O ( N17000601 )
√ √ √ √ √ √
Non-Vital I/O (N17061501)
2.10 Design :
Microlok II Design consists of : (a) Interface Design:
Wiring diagram of relays, panels, CT racks, Power supply, Microlok II card file etc. (Mainly external to MLKII).
(b) Application Program Design:
Complete Interlocking program, further converted in conventional circuit, which is easy to understand.
2.11 Inputs for Design
To start design of MLK II based Interlocking system, Inputs required are: (a) Approved Signal Interlocking Plan.
(b) Approved Front Plate Drawing. (c) Power supply scheme.
(d) Relay room building layouts. (e) CT rack termination details.
(f) Details of any additional interlocking equipment to be interfaced with MLKII. 2.12 Process of Interface Design
(a) Vital and Non-vital I/O bit calculation. (b) Vital and Non-vital board calculation.
(c) System configuration and serial communication. (d) Power calculation.
(e) Interconnection of various racks and interlocking equipment. (f) Manuscript of complete wiring diagram.
2.12.1 Calculation of I/O Bits
Gather following information from Interlocking plan: (a) Type of signals, direct/indirect feed.
(b) Points/Cross over and type of control/operation. (c) Motor points/Hand operated points.
(d) Level crossings, siding control and crank handles. (e) Track circuits.
(f) Axle counters.
(g) Type of block working with adjacent stations. Gather following information from Front Plate Drawing:
(a) Number of push button controls and key controls. (b) Number of indications, counters, buzzers, bells etc.
The Information gathered from “Signal Interlocking Plan” and “Front plate Drawing “ is used to calculate Vital I/O and Non-Vital I/O respectively.
DESIGN Example of I/O Bits
Outdoor Gear Vital Output Vital Input Non-vital Input Non-Vital Output Relays 3A Signal (HOME) DR HR Co HR UHR DECR HECR RECR Co HECR UECR GN DGKE HGKE RGKE UGKE AJKE COKE ECR- 5 QN1-4 3A Signal DR HR DECR HECR RECR GN DGKE HGKE RGKE AJKE ECR- 3 QN1-2 2A Signal HR HECR RECR GN HGKE RGKE AJKE ECR- 2 QN1- 1 Points WNR WRR NWKR RWKR WN NWKE RWKE WLKE ACKE ACKRE ANKE ANKRE BCKE BCKRE BNKE BNKRE QN1-2 QNA1-2 Track Circuit - TPR - TKE TKRE QNA1-1 Crank Handle CHYR CHLR CHN CHR CHKE CHKRE QN1-2 Siding Control KLR KLCR KLN KLR KLKE KLKRE QN1-2 Level Crossing LXYR LXCR LXN LXR LXKE LXKRE QN1-1 QNA1-1 Block Inst. - LCPR TOLR
2.12.2 Calculation of Board & Relays
After finding out final quantity of Vital and Non-vital I/O bits, quantity of various boards is
derived as below:
(a) 16 Vital Inputs per one Vital Input Card. (b) 16 Vital Outputs per one Vital Output Card.
(d) 8 Vital Inputs and 8 Vital Outputs per one Mixed Vital I/O Card.
(e) Calculate various relays on the basis of above table and decide ,the size and design of relay rack.
(f) Per Card file, allocate 16 cards either Vital or Non-Vital.
2.12.3 Estimation of MLK II Hardware
(a) 48 pin Connector Assembly: Sum of Vital I/O Boards, CPU and Power Supply PCB. (b) 48 Pin Address select PCB: Sum of Vital I/O Boards.
(c) 96 Pin Connector Assembly: Sum of Non-vital Boards. (d) 96 Pin Address select PCB: Sum of Non-vital Boards.
(e) Each cardfile will have one CPU, one PS PCB and one VCOR. (f) Each CPU will have one EEPROM PCB.
2.13 Configuration of MLK II
Place maximum of 16 nos. of either vital or Non-vital cards per Cardfile. Arrive at final quantity of card files.
On the basis of requirement of installation/site, MLK II is connected with the peripheral equipments such as VDUs and another MLKII units.
All the peripherals are connected with MLK II with serial communication cable. Inputs and Outputs from / to control panel are connected through multi core cables.
Fig. No: 2.13
Configuration of MLK II
CONTROL PANEL CONTROL PANEL MLK II - A MLK IIUNIT --BDOUBLE DECK TERMINALS (PHOENIX TERMINALS) DOUBLE DECK TERMINALS (PHOENIX TERMINALS)
RELAY RACK RELAY RACK OP. OP. VDU VDU MAINT. MAINT. VDU VDU To Adjacent Station To Adjacent Station P1 P1 P1P1 P4 P4 P4P4 P3 P3 P3 P3 P5 P5 P5P5 Diagnostic Link Maint . VDU Link NV
OP VDU Link NV
OP VDU Link NV
CABLE TERMINATION RACK CABLE TERMINATION RACK
MLK-II UNIT-B MLK-II
CONFIGURING MLK II
2.14 Configuring MLK II :
(a) Operator VDU and Maintenance VDU are connected to MLK II- CPU through “Non-Twisted pair-communication” cable.
(b) Communication between A and B MLK II are wired with Twisted Pair-communication cable.
(c) Control panel Inputs and Outputs are connected to MLK II with help of “Single strand Multi core” cable.
(d) Relay rack and CT racks are connected to MLK II with “Single Strand Multi core “ cable.
(e) Vital Input and Vital Outputs are wired with help of “Twisted Pair” wires. (f) Relay wiring is done with the help of “Multi strand, Single core” wire. 2.15 Design of Relay Room Floor Plan
Once calculation of boards, relays and MLK II configuration is finalized Design of Relay Room Floor Plan is taken up with following criterion:
MLK II Rack: Size: 2100mm X 800mm X 600 mm Capacity: 2 Card files
Relay Rack: Size: 2100mm X 1120mm X 300 mm Capacity: 96 Relays
Termination Rack: Size: 2100mm X 700mm X 300 mm Capacity: 12 Non-vital boards
2.16 Interface Design
All the required details now available to design interface drawings.
Interface Drawings consists of:
(a) Index.
(b) Signalling Layout Plan-Replica of Signal Interlocking Plan. (c) Panel Front Plate drawing.
(d) Route control chart. (e) Relay Room Floor Plan. (f) Configuration drawing. (g) Serial Ports wiring details.
(h) Address select PCB, Jumper settings and keying plug details. (i) CPU&PS PCB wiring detail.
(j) I/O Bit Charts.
(k) Non-Vital & Vital board wiring. (l) All field gear driving circuit.
(m) Power supply distribution drawing. (n) Fuse chart.
(o) Rack assembly drawings. (p) Interconnection details. (q) Contact analysis.
2.17 Application Program Design
Application Program is nothing but another form of Interlocking Circuit. The design is based on Signal Interlocking Plan, Route Control Chart & Front Plate Drawing. Application Program is written in form of equations called Boolean equations. All the relays used in conventional circuits are called as BIT when referred to Application Program.
Program is divided in various parts : (a) Local I/O bit definition section. (b) Boolean bit definition section. (c) Serial bit definition section. (d) Timer Section.
(e) Log bit definition section. (f) Logic section.
2.18 Conventional PI Logic
Pressed UP Down UP Down UP
UP UP Down Down Up
UP
Down Down
UP UP
Fig No : 2.14
GN,UN GNR, UNR GNCR, UNCR NRR NNR WNR, WRR
WKRs UCR ALSR WLR HR
TPRs
RECR RGKE
CONCEPT OF MLK II APPLICATION LOGIC
2.19 Concept of MLKII Application Logic:
2.20 Non-vital Section:
It consists button relay logics and indication logics. The relays such as GNR, UNR and indications such as RGKE, HGKE, WLKE etc. are defined in Non-vital I/O board definition section. Rest of the relays GNCR, UNCR are defined in NV Boolean bit definition section. These logics are written as “NV ASSIGN “ statement.
2.21 Vital Section
It consists complete interlocking logic except button relay and indication logics. The names of Vital relays such as HR, DR, RECR, HECR, TPR etc. are defined in Vital I/O board definition section and rest of the relays such as ASR, UCR, TLSR etc. are defined in Vital Boolean bit definition section. These logics are written as “ASSIGN” statement.
2.22 Timer Section
“Slow to Pick “or “Slow to Release” time delay for any function are defined in this section. The definition works as Condenser-Resistor combination generally used in conventional installation. “Slow to Pick” is defined as “SET=1 SEC”. “Slow to Release” is as
“CLEAR=1 SEC”.
2.23 Serial Section
This section is required to communicate the STATUS of any bit to other compatible system like VDU, MLKII etc. Output BIT from one system becomes Input BIT to other system and vice a versa. Output BIT and Input Bit definition sections are different. The order of BIT definition shall be same in both systems.
2.24 Symbols Used in Application Program
* - SERIES
+ - PARALLEL
( - START OF PARALLEL PATH
) - END OF PARALLEL PATH
~ - BACK CONTACT
, - BIT SEPARATION
; - END OF STATEMENT/ SECTION
// - SINGLE LINE COMMENTS
% MULTI LINE COMMENTS - - - TYPE 1 \
/* MULTI LINE COMMENTS - - - TYPE 1 */
2.25 Conversion of Circuit to Equation
A B C D XYZ ASSIGN A * B * ( ~ C * D + E ) To XYZ ; E .
CONVERSION OF CIRCUITS TO EQUATIONS
Examples:-
Typical examples are given below :
Fig No : 2.16
2.26 Compilation of Application Program
Program shall be stored as “PROGRAM.ML2” file name. Compilation is carried out with help of Microlok II Compiler. Result of compilation will be two files viz. ‘PROGRAM.MLL” & “PROGRAM.MLP”. “MLL” file is a listing file, which gives any errors, warnings, no. of BITs used, no. of time one bit used and so many other important information. This also gives unique identification numbers called as “CHECKSUM” & “CRC”. “MLP” file is a data file, which is loaded in memory of CPU of MLK II using MLK II Maintenance tool.
2.27 Concept of Hot Standby
Any Signal Interlocking System needs to be uninterrupted as it deals with safety. Train detentions shall be minimal. MLK II being an Electronic System, it is mandatory to duplicate entire system. All the Vital and Non-vital boards, CPU, Power Supply PCB, VCOR are in duplicate. Duplicated MLKII systems are identified as “SYSTEM-A” and “SYSTEM-B”. When one system fails due to any reason, it is ensured the other system is available to take care of Station Interlocking.
2.28 Evolvement of Hot Standby Logic
Both systems shall work all the time. Inputs are read by both the systems independently and compared continuously. Processing application logic simultaneously and comparison at various stages. Parallel delivery of Output by both the systems after comparison. Any mismatch in the STATUS of bits between the system will KILL the system ensuring other unaffected.
2.28.1 Design Concept:
a) Vital Output:
Vital output will be delivered only when status of the BIT is same in the both the systems. Both the systems’ outputs are connected in parallel to one interface relay through a DIODE to avoid back feeding. Once output is delivered, any change is STATUS of other system will not affect status of delivered bit. In case of MISMATCH no outputs will be delivered by either system. MISMATCH indication will appear on Control panel and VDU.
b) Vital Input:
System-A read Input as HIGH and that in B as LOW. Input LOW is most restrictive state, it is considered to be valid. MISMATCH is generated in the system which has Input in HIGH state and System-A will be KILLED.
c) Non-vital Output:
Outputs are not compared before delivery as it is difficult to compare status of Flashing Output. Output is delivered only by one system. When system which is delivering Non-vital Outputs is KILLED, the control will be shifted to other system. Interruption of visual indications on control panel for few seconds.
d) Non-vital Input:
The inputs are compared for its STATUS in both systems. Mismatch will be generated in as system that has not read Input and it will be KILLED.
Concept of Vital Output, Vital Input and vital Output is same as above. Non-vital Input is ANDed with its corresponding bit from other system. Further process is negated in the system, which has not read the Input, MISMATCH is generated and system will be KILLED. When one system is KILLED, it needs human intervention to restore back ONLINE. System need to be RESET manually. When RESET, it will not update itself from already ONLINE system.
CONCEPT OF HOT STANDBY
2.28.2 Disadvantages:
Momentary button inputs cause Disabling/Shutting down of one system or some time both the systems.
Remedy:
Intermediate bits are compared to generate MISMATCH. This intermediate bit is nothing but next level steady bit(which has its own holding path). Incase of MISMATCH indication will appear on control panel and VDU and further process in the both the systems will be negated. Killing incidences are then reduced and system is made STABLE.
In stations both the systems are working on actual Hot Standby logic is most satisfactorily and stable.
2.29 Warm Standby Logic:
Hot Standby Logic working in some stations, though having stable design, due to climatic instability / lightening caused failure of cards and both the systems were shut down which has interrupted train movements. In these stations warm standby logic is introduced i.e. external change over circuit is developed to switch on second system, when first has failed due to some reasons.
Both the systems’ cards are kept inserted in slots and in ready condition to switch ON when intended. MLKII power supply is controlled by “External Changes Over” circuits, which proves back contact of VCOR relays. Only one system is ONLINE and other is power OFF. This is a Worm Standby Logic and working satisfactorily in stations.
The main advantage of this warm standby logic is to maintain only one Application Program and its testing is easy and time saving.
The disadvantage is the system which is Powered OFF, integrity of the cards and whole system cannot be ascertained unless Powered ON next time. Traffic interruption for 3 to 5 Minutes.
2.30 Maintenance:
MLK II based Interlocking System is provided with Windows based Maintenance Tool package. Maintenance tool is loaded in Maintenance VDU
Using the tools provided in this Maintenance tool program, maintenance personnel and application engineers can perform a wide variety of Microlok II system maintenance, configuration, and diagnostics functions.
The program provides these tools as selections on the Microlok II Maintenance Tools main menu, as shown in Figure below.
This main menu displays the selection buttons that activate the primary functions of the program. These selection buttons are grouped into four main categories.
(a) Run-time Monitor (b) Historical Data
(c) System Adjustment/Setup (d) Other Tools
MAINTENANCE
2.30.1 RUN-TIME MONITOR
These buttons lead to display data about an operating MICROLOK II and its application. This group of tools enables you to view the current status of equipment and related systems.
(a) System Information:
It views system events and appears as shown below.
This display shows the current version number of the executive software and an abbreviated "snap-shot" of the most recent system events. Where appropriate, the display defines the action taken in response to an event.
The system information display lists the time and date when the following types of events last occurred:
(i) System resets (ii) System errors (iii) Unit configuration
(iv) Clearing of the system log clear (v) Clearing of the user data log clear (vi) Time changes
(vii) Clearing of conditional power supply (CPS) trips
Since some of these events occur infrequently, the displayed date also includes the year in which the associated event occurred.
(b) Board Information:
It displays the status information about Input – Output interface cards (Printed Circuited Boards) of a Microlok II or Serial link. It displays the current status of each enabled PCB in the Microlok II cardfile. Each board type is dynamically updated.
(c) Free-run Variable Display and Dynamic Bit/Variable Display:
These two tools enable you to view the real-time status of Microlok II system variables. These tools list the current values for selected variables and bits as well as a real-time list of changes. These two displays provide the same information in different ways. The free-run display presents the status information in a text mode, while the dynamic bit/variable display represents the indications graphically in strip-chart view of bit and variable changes.
2.30.2 HISTORICAL DATA:
These buttons lead to views which display data which an operating Microlok II has collected and stored. The Microlok II system logs and reports information of critical errors, warnings, and operational events. This section contains four tools that enable you to review the logged system information in several ways.
(a) User Data Log:
The user data log records only those events that the user specifies. It displays changes of selected bit and numeric variables as requested by the application or configuration. This log is capable of recording up to 90,000 of the most recent specified Boolean changes, or at least 64,000 Boolean and/or numeric changes.
(b) System Event Log:
The system event log records up to 5000 of the most recent critical errors, warnings, and events. Any system critical error or warning will be logged in the system log. Events are used to relay miscellaneous system information and may be limited by use of the configuration.
(c) System Error Log:
The system error log is limited to critical errors. Since the older events may be lost in system event logger, the system error log contains a list of the last 50 time stamped critical system errors.
(d) Merged Events Log:
The merged events log enables you view errors, warnings, and events as in the User Data, System Event, System Error log and Dynamic variable changes merged onto the same time axis. This log also provides graphic displays of parameters and events as specified in the user data log.
2.30.3 SYSTEM ADJUSTMENT / SETUP
These buttons lead to views which modify parameters of the Microlok II.
(a) Set Time of Day Clock:
This function displays the date and time settings for both the Microlok II system CPU and the laptop computer and sets the Microlok II on-board clock.
(b) Software Upload:
This tool is used for uploading a custom-designed application software program from the laptop PC to the Microlok II CPU. This tool interacts with Windows-based files; therefore, you should be familiar with application software and Windows file navigation to use this feature.
(c) Reset Microlok II:
This tool enables you to reset the Microlok II CPU from the laptop computer. The reset function is used mainly to clear system faults and return the system to normal operation.
OTHER TOOLS (d) System Configuration:
The configuration tool provides a wide variety of options for checking and modifying the configuration of the Microlok II system hardware and software.
Three types of options are provided within this tool:
(i) System configuration options enable you to modify the general system parameters and the user parameters, and to assign specific parameters to the user data log.
(ii) Board configuration options enable you to enable/disable and configure the individual Microlok II system PCBs (Printed Circuit Boards).
(iii) Link configuration options enable you to configure the Microlok II system communication links.
2.30.4 OTHER TOOLS:
These buttons lead to views which allow special diagnostic functions to be performed.
(a) System Memory Dump:
Allows Ansaldo STS personnel to provide specialized debugging assistance. The system memory dump tool enables Ansaldo STS system developers and maintainers to perform debugging operations when a customer encounters a software problem.
(b) Program Settings:
The Program Settings dialog is used to modify the way in which the system stores and displays data. These options can also change the general appearance of the screens.
(c) Serial Message Monitor:
This tool enables you to monitor serial message traffic on a selected active serial link.
(d) Save Comma Delimited download:
This tool lets the user download the user data log in a comma-delimited format. This file can be viewed in Microsoft Excel. The file can be saved via the diagnostic port link, or directly from the PCMCIA card in the card reader on the individual PC.
(e) Application Download :
This tool lets the user download the application image from the EEPROM on the Microlok II unit. As a default, the file is stored with a filename.mlp extension so it can be easily uploaded to the system, if necessary. It is for to download present working application program.
2.31 Microlok II as a Distributed Interlocking System :
(Working in Kottavalsa - Vizianagaram Palasa section of ECo Rly )
(a) Object Controllers (OCs) are used as slave unit of Central Interlocking Unit (CIU) through duplicated serial communication.
(b) As on date, Object Controllers drive the field gears (Points, Signal etc.,) through relays and take feedback (input) from various field gears (Track, Point Indication, Aspects etc) through concerned relay contacts.
(c) The medium of communication between CIU and OC shall be Optical Fiber Cable (OFC) provided on a ring basis.
(d) Any error in any OC or hardware fault leading to unsafe condition shall immediately withdraw all output commands.
(e) In place of Control cum Indication Panel, two number of VDU panel with LCD monitor of 22’ (One working & one standby) are provided. VDU panel have the auto change over facility as well as manual change over facility.
(f) OC and CIU have been interfaced by OFC with ring by providing Optical modem (OSD-1250).
(g) Although system has inbuilt Data logger system, the system has been provided with external data logger for networking purpose with other station.
(h) All vital outputs are drive to field through relay only. (i) Here OC and CIU are represented by each Microlok II. (j) Communication equipment used :
(i) 422 CFCR
-- Used as interface between Microlok and Redundant modem(OSD1250LC) (ii) OSD 1250LC
-- Redundant optical modem ( 2ch-OFC) Communication between Microlok-II to Microlok-II
(iii) 485 LDRC
-- RS232 to RS485/422 converter cum Isolator. Used between Microlok to Operator’s PC / Maintenance PC.
(iv) OSD 136L
-- Optical modem without ring protection. Used for communication between Microlok-II to Datalogger.
2.32 Advantages of Distributed Interlocking System : (a) As Main Signalling Cable is totally eliminated,
-- Main Cable Maintenance and testing is Reduced.
-- Main Cable failures are prevented.
-- Damage of equipment due to short circuit of main cables is prevented.
-- Damage of main equipments under short circuit condition of traction supply (OHE catenary wire broken and fallen on the rails) is minimised.
-- Expenditure has been reduced considerably. (b) Designing and modification has become more easier. (c) Simulation can be more simplified.
2.33 General Maintenance of MLK II:
System must be protected from the dust. Wires should be properly inserted of wires in terminals. All the terminals should have tightness. Battery shall be maintained properly. User data log shall be downloaded regularly.
DO’S & DON’T’S
2.34 DOs & DON’Ts of MICROLOK II System: √ DOs
--
-- Keep the Microlok II room free from dust.
--
-- Finger Tighten the boards after insertion.
--
-- Ensure all terminations are fully tightened.
--
-- Place the removed boards with a tag into a conductive shielding bag.
--
-- Maintain Minimum 13.5 V to 16.5 V DC at the power supply board terminals.
--
-- Maintain 24V to 28V DC at the Microlok II Input /Output power Modules.
--
-- Check Microlok II system fuses at regular intervals.
--
-- Take back up of User Data Log / Event Log / Error Log data files weekly.
--
-- Ensure synchronization of Microlok II clock time with Maintenance PC after the System
changes over.
--
-- After completion of diagnostics, Reset that system and enable CPS in up mode
(Ref: ”CPS CLEAR FUNCTION” details).
--
-- During Maintenance changeover of one system to other system, SGE block Instrument
must be kept in TOL Condition.
--
-- Use Vacuum for the externally accumulated dust and dirt.
X DO NOT
-- Don’t attempt Troubleshooting if you do not have proper Microlok II training.
-- Don’t switch ON Radio Equipment within the vicinity of Microlok II.
-- Don’t use non-conductive materials such as Styrofoam cups, Plastic ashtrays and Cell phone wrappers in the vicinity of Microlok II.
-- Don’t reset the system using Maintenance Tool/CPU front panel Reset push button when working.
-- Don’t remove boards, VCOR relays, fuses / Links and 48/96 pin
-- Connectors when the system is ON.
-- Don’t force boards into the Slots during insertion.
-- Don’t change jumper settings in CPU board & Address select PCBs.
-- Don’t touch the board components.
-- Don’t repair boards on your own.
-- Don’t alter Microlok II system, Maintenance PC & Operator PC settings without authorization.
-- Don’t delete/Modify Application logic programs without authorization.
-- Don’t apply blower for cleaning dust.
-- Don’t use any kind of Solvents, Detergents or Abrasive cleaners on the Card file or internal components.
-- Don’t use vacuum cleaner inside the Card file. * * *
