An Ultra-low low energy asynchronous processor for Wireless Sensor Networks

(1)

An Ultra

-

low energy

asynchronous processor for

Wireless Sensor Networks

L.Necchi

,

L.Lavagno

,

D.Pandini

,

L.Vanzago

Politecnico

(2)

Wireless Sensor Networks

Application areas: Application areas: Monitoring Monitoring Building automation Building automation

Health care, Medical

Health care, Medical Emergency response

-- AdAd--hoc wireless networkshoc wireless networks -- SensingSensing -- ComputationComputation -- ActuationActuation

(3)

Key WSN Requirements

Flexibility (general purpose design)

High energy efficiency (battery powered)

Extremely wide voltage supply range

Exhausted battery or energy scavenging Exhausted battery or energy scavenging

Fast and inexpensive wake

-

up

event driven power management (not predictable)event driven power management (not predictable)

Sporadic high computational load

Encryption (security)Encryption (security)

(4)

TI

MSP430

Main components of a WSN node:

Microcontroller

Memory

Radio

Sensors / Actuators

Power supply

Battery (energy storage)

Power scavenging

Sensor node architecture

Atmel

(5)

Circuit

-

_-

level Power Management

_{level Power Management}

X

Active Active Idle Idle

Long

Deadlines

Idle Time

Scenario Scenario

Adaptive Body Biasing

Dynamic Voltage Scaling

X

Power Gating Power Gating

X

Clock Gating Clock Gating

Save energy while

Management

DVS can be obtained by:

OffOff--line preline pre--computed voltage/frequency tablescomputed voltage/frequency tables High delay margins

High delay margins

Evaluated onEvaluated on--line:line:

PowerWise

(6)

Closed

-

_-

loop DVS technique

_{loop DVS technique}

PowerWise

PowerWise::

Samples, with a high frequency clock, the output of a digital deSamples, with a high frequency clock, the output of a digital delay lay

line, and arrange voltage supply to deliver required performance

Razor:

Detects timing errors comparing values stored in duplicated slavDetects timing errors comparing values stored in duplicated slave e

latches, in which the second is clocked half clock cycle later,

restarts the pipeline and arranges voltage supply accordingly

Asynchronous with Dual

Asynchronous with Dual--Rail encoding:Rail encoding:

(Quasi) delay insensitive implementation, that guarantees (Quasi) delay insensitive implementation, that guarantees

correctness for (almost) every voltage supply and process

variation

Asynchronous with Bundled Data encoding:

(7)

De

-

_-

synchronization

_{synchronization}

Synchronous CLK Asynchronous Desynchronize CLK

(8)

Design Flow

Obtain asynchronous Obtain asynchronous implementation from implementation from synchronous specification: synchronous specification: Think synchronously Think synchronously Design synchronously Design synchronously De De--synchronize synchronize (automatically) (automatically) Test synchronously Test synchronously Run asynchronously Run asynchronously HDL RTL Synthesis & Optimization Netlist De-synchronization Netlist Physical Design Layout Library

(9)

MS flip-flop

Synchronous circuit

CLK L L L L L _L 0 0 0 0 1 1

(10)

De

-

_-

synchronization

_{synchronization}

L L L L L _L 0 0 0 0 1 1 C C C C C _C

(11)

De

-

_-

synchronization

_{synchronization}

C C C C

C _C

Distributed micropipeline-style controllers

substitute the clock network

(12)

Flow equivalence

[Guernic, Talpin, Lann, 2003]

A

B

(13)

CLK A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 Synchronous behavior De-synchronized behavior

Flow equivalence

(14)

Flow equivalence

[Guernic, Talpin, Lann, 2003]

Theorem:

CLK A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 Synchronous behavior De-synchronized behavior

(15)

Flow equivalence

(16)

De

-

_-

synchronization Benefits

_{synchronization Benefits}

For the end user:

Reduced electromagnetic emissionReduced electromagnetic emission

Process Variation toleranceProcess Variation tolerance

Enables Enables partialpartial average case design, average case design,

wrt

wrt process & environment variation (not process & environment variation (not wrtwrt datadata--dependent dependent delay)

delay)

The resulting circuit will be:The resulting circuit will be:

Ready for frequency and voltage scaling

Inherently more robust to delay variations

Virtually no performance or area overhead

Virtually no performance or area overhead wrtwrt synchronoussynchronous

For the designer

Conventional EDA Tools and design flowConventional EDA Tools and design flow

Limited design time and effort, fully automated

(17)

Asynchronous advantages

not

_not

offered by de

-

_-

synchronization

_{synchronization}

Fine

-

grained power management

The desynchronized circuit inherits the synchronous The desynchronized circuit inherits the synchronous

clock gating

Fine

-

grained pipelining

The pipeline structure is not changedThe pipeline structure is not changed

Data

-

dependent delays

Could be exploited by using a Could be exploited by using a datapathdatapath with with

completion detection (work in progress)

Robustness with respect to uncorrelated local

variability

(18)

Synchronous Logic Interfacing

C L 0 L 1 C L 0 L 1 C L 0 L 1 _FAST LOGIC

Data path (not modified) Handshaking line

(19)

Synchronous Logic Interfacing

C L 0 L 1 C L 0 L 1 C L 0 L 1

•Synchronized with an external slower clock -Just low EMI

CL CL CL

SLOW LOGIC

(20)

Synchronous Logic Interfacing

C L 0 L 1 C L 0 L 1 C L 0 L 1 CL CL CL SELF TIMED LOGIC

(21)

Main components of a WSN node:

Microcontroller

Memory

Radio

Sensors / Actuators

Power supply

Battery (energy storage)

Power scavenging

Sensor node architecture

Atmel

(22)

Our Case Study

Application independent 8 Bit CPU architecture:

Atmel

AVR Instruction Set (like MICA2

-

-MICAZ) from

MICAZ) from

OpenCores.org

, implemented

with a 130nm technology

Toolchain

and lots of software are ready to use

nesC

nesC, , TinyOSTinyOS, , TinyDBTinyDB, Surge, , Surge, TossimTossim

Aggressive Energy management enabled by

de

-

synchronization, using:

Dynamic Voltage Scaling

zero wake

(23)

Typical AVR architecture

L 0 L 1 Instruction FETCH INSTR. Memory Instruction DECODE ALU MEM Access DATA Memory Execution External CLK

Data Path (8 bit) Address bus Clk distribution

(24)

Design Choices

Main target is energy efficiency (

vs

speed)

Large delay margins (100%) to increase

robustness at low voltage supply

AVR core is really small (~4500 gates),

hence we used a

Single

controller

Reduced area overhead

(25)

De

-

_-

synchronized AVR

_{synchronized AVR}

L 0 L 1 Instruction FETCH INSTR. Memory Instruction DECODE ALU MEM Access DATA Memory Execution Data Path Address bus

Handshake signal distribution Delay chain

(26)

Logic and Delay Line Matching

(27)

Logic Delay

Leakage per

instruction

Energy Efficiency

Voltage Supply [V]

Power

Consumption

Energy per

Instruction

(28)

Energy Efficiency

(29)

Some Past Work Comparison

Philips 80c51 (H. van

Gageldonk

., 1998)

Asynchronous bundledAsynchronous bundled--data implementation of the data implementation of the

8051 ISA, general purpose.

Lutonium

(A. Martin et al., 2003)

Asynchronous QDI implementation of the 8051 ISA.Asynchronous QDI implementation of the 8051 ISA.

Snap/le (V.

Ekanayake

et al., 2004)

Asynchronous QDI processor specifically designed for Asynchronous QDI processor specifically designed for

WSN.

Razor (D. Ernst et al., 2004)

Synchronous processor that estimated the best Synchronous processor that estimated the best VddVdd by by

dynamically monitoring the delay of the logic using a

redundant latching schema.

(30)

CONCLUSIONS

Aggressive Energy management using DVS

14 14 pJ/InstrpJ/Instr @ 1.2 V (170 MIPS) @ 1.2 V (170 MIPS)

2.7 2.7 pJ/InstrpJ/Instr @ 0.51 V ( 48 MIPS)@ 0.51 V ( 48 MIPS)

Minimal overhead

wrt

synchronous counterpart

+6% area (due to FF+6% area (due to FF-->latch conversion)>latch conversion)

--20% speed (could be improved by reducing margins)20% speed (could be improved by reducing margins)

Future work:

Analysis with other “SPICEAnalysis with other “SPICE--like” simulators (like” simulators (HsimHsim))

Statistical simulations to check robustness Statistical simulations to check robustness wrtwrt

process variability (Monte Carlo)