CMOS Differential Amplifier

(1)

CMOS Differential Amplifier

1. Current Equations of Differential Amplifier

VDD

VSS VC VSS VSS

ISS

VG1 VG2

VGS2 VGS1

ID1 ID2

(a)

+

+ +

+

E+=VID/2

E-=-VID/2 (1)

(10)

(2) VG1

VG2 VIC

VID (7)

(b)

Figure 1. General MOS Differential Amplifier: (a) Schematic Diagram, (b) Input Gate Voltages Implementation.

Figure 1(a) shows the schematic diagram of a typical differential amplifier. The differential input is given by:

)

V

(

)

V

(

V

_ID

=

_G1

−

_G2

=

_GS1

+

_C

−

_GS2

+

_C --(1)

2 D2 1

D1 TN

GS2 TN

GS1 GS2

GS1 ID

I

2 I

2 )

V

(

)

V

(

V

β

−

=

−

=

−

=

--(2)

The common-mode input signal is given by:

2 V

V

G1 G2

IC

+

=

--(3)

The input voltages in term of VID and VIC are given by

2 /

V

_G1

=

_IC

+

_ID --(4)

2 /

V

(2)

Figure 1(b) shows the implementation of the 2 gate voltages in terms of the differential and common mode voltages. Its PSpice implementation using voltage controlled voltage source is given below:

VID 7 0 DC 0V E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5 VIC 10 0 DC 0V

Two special cases of input gate signals are of interests : pure differential and pure common mode input signals. Pure differential input signals mean VIC=0, from equation (4) and (5);

2 /

V

2 /

V

ID G2

ID G1

−

=

This case is of interest when studying the differential gain of differential amplifier, see Figure 2(a). Pure common-mode input signals mean VID=0, from equation (4) and (5);

IC G2

IC G1

V

=

This case is of interest when studying the common-mode gain of differential amplifier, see Figure 5(a). Assume both transistor drivers are matched, that is:

β

₁

=

₂

=

β

D1 D2

ID

I

2 I

2 V

=

−

--(6)

D2 D1

ID

I

V

2 /

=

−

β

--(7)

The transistor currents satisfy the following equations: D2

D1

SS

I

=

+

--(8)

D2 D1

OD

I

=

−

--(9)

2 /

)

I

(

I

_D1

=

_SS

+

_OD --(10)

2 /

)

I

(

I

_D2

=

_SS

−

_OD --(11)

Substituting Eq(10) and Eq(11) to Eq(7)

2 /

)

I

(

2 /

)

I

(

V

2 /

_ID

=

_SS

+

_OD

−

_SS

−

_OD

(3)

Normalizing by ISS

)

I

1 I

I

1 (

V

I

_SS

OD SS

OD ID

SS

−

+

=

β

--(13) To simplify the equation, let

SS OD ID

SS

I

=

y

and

,

V

I

=

x

β

--(14)

The equation reduces to:

y

-1

y

+

1 =

x

−

Solve for y,

2 2

₍

₁

_y)

_-

₂

₍

₁

_y)

₍

₁

_y)

₍

₁

_y)

₌

₂

_-

₂

₁

_-

_y

x

=

+

−

+

−

2 x

1 y

1

2 2

₌

₋

−

4 x

x

1 y

1 ₋

2

₌

₋

2

₊

4

)

4 x

1 (

x

y

2 2

2

₌

₋

The result is:

1 |

2 x

|

provided

,

4 x

-1

x

=

y

2

≤

--(15)

Substituting for x and y, one obtains

4 I

V

1 V

I

SS 2 ID ID

SS SS

OD

₌

β

₋

β

_--(16)

2 SS

4 ID SS

2 ID SS OD

4I

V

I

V

I

=

β

−

β

--(17)

2 SS

4 ID SS

2 ID SS SS

D1

4I

V

I

V

I

2

1 I

2

1

(4)

2 SS

4 ID SS

2 ID SS SS

D2

4I

V

I

V

I

2

1 I

2

1 I

=

−

β

−

β

, provided

β

SS

ID

I

2 |

V

≤

|

--(19)

2. Low Frequency Small Signal Equivalent Circuit With Pure Differential Input

Signal

VG1

VGS1

VSS VG2

VGS2 VDD

VSS VC VSS

ISS

S3

D3

D1

S1

S4

D4

D2

S2 gm3

gds1 gds2

gm4vgs4

gm2(-vid/2) gm1(vid/2)

gds3 gds4

VC

+ VO

-ID2

ID4 IO

ID3 ID1 M1

w=9.6u l=5.4u

M2 w=9.6u l=5.4u M3

w=25.8u l=5.4u

M4 w=25.8u l=5.4u

(6) (3)

(4)

(1) (2)

(5)

(b) (a) +

VID/2

+ VID/2 +2∆I

+∆I +∆I

+∆I −∆I

(5)

Figure 2. Differential Amplifier Implementation: (a) Differential Amplifier with PMOS current mirror load, (b) Small Signal Equivalent Circuit for Purely Differential Input Signal.

An active load acts as a current source. Thus it must be biased such that their currents add up exactly to ISS. In practice this is quite difficult. Thus a feedback circuit is required to ensure this equality.

This is achieved by using a current mirror circuit as load, as in Figure 2. The current mirror consists of transistor M3 and M4. One transistor (M3) is always connected as diode and drives the other transistor (M4). Since VGS3=VGS4, if both transistors have the same β, then the current ID3 is mirrored to ID4, i.e.,

ID3=ID4.

The advantage of this configuration is that the differential output signal is converted to a single ended output signal with no extra components required. In this circuit, the output voltage or current is taken from the drains of M2 and M4. The operation of this circuit is as follows. If a differential voltage, VID=VG1-VG2, is applied between the gates, then half is applied to the gate-source of M1 and half to the

gate-source of M2. The result is to increase ID1 and decrease ID2 by equal increment, ∆I. The ∆I increase ID1

is mirrored through M3-M4 as an increase in ID4 of ∆I. As a consequence of the ∆I increase in ID4 and the

∆I decrease in ID2 , the output must sink a current of 2∆I. The sum of the changes in ID1 and ID2 at the

common node VC is zero. That is, the node VC is at an ac ground, see Figure 2(b). From Eq(4) and Eq(5)

for pure differential input signal means the common-mode signal VIC is zero. That is, the input signals are

VG1=VID/2 and VG2=-VID/2. This is shown in Figure 2(a). The transconductance of the differential amplifier

is given by:

m1 gs1 ID

ID ID

O

mD

g

V

I

2 /

V

I

V

I

2 V

I

g

=

∆

=

∆

=

∆

=

∆

=

That is, the differential amplifier has the same transconductance as a single stage common source amplifier.

(6)

gm2(vid/2) _gds2 gm4vgs4 _gds4 G1 D1

S1 S3

D2

S2

D4

S4 D3=G3=G4

vgs3= vgs4

+

-+

-V2=vo V1=vid/2

2gm1(vid/2) g_{ds2 gds4} G1

V1=vid/2 +

-S1

D2

S2

D4

S4

+

-V2=vo

gm1vid _{gds2 gds4} D2

S2

D4

S4

+

-G1

+

-S1

V2=vo V1=vid

(b)

(c)

gds3

(a)

gm1 (vid

/2)

gds1 gm3

Figure 3. Differential Amplifier Operating in Purely Differential Input Signal: (a) Original Equivalent Circuit, (b) Reduction to Two-port Network, and (c) Changing Input Port Variable to V1=Vid .

The derivation of the small signal equivalent circuit is shown in Figure 2. The simplification is based on the symmetry of the circuit. In Figure 2(b), each transistor equivalent circuit is drawn. Figure 3(a) redraws the equivalent circuit in Figure 2(b) in a form suitable for two-port analysis. The further reduction is obtained after the two-port parameters are obtained.

From Figure 3(a), the following two-port variables and load are obtained.

O 2

ID 1 L

V

and

/2

V

0 Y

=

The port current equations are derived to obtain the Y parameters:

0 I

₁

=

--(20)

2 ds4 ds2 gs4

m4 1 m2

2

-g

V

g

V

(g

g

)V

(7)

V

g

-V

₁

m3 ds3 ds1

m1

gs4

=

₊

--(22)

Substitute eq(22) to eq(21)

2 ds4 ds2 1

m1

2 ds4 ds2 1 m3 ds3 ds1

m4 m1 m2

2 ds4 ds2 1 m3 ds3 ds1

m4 m1 1

m2 2

)V

g

(g

V

-2g

)V

g

(g

V

)

g

(g

-

)V

g

(g

V

g

-V

-g

I

+

=

+

=

+

=

--(23)

ds3 ds1 m3

m4 m3 m2

m1

g

assuming

=

>>

+

The resulting Y-parameter matrix is:













+

=

ds4 ds2

m1

g

2g

-0

0 Y

The dc voltage gain is,

ds4 ds2

m1 L

22 21 id

O 1

2 VD02

g

2 Y

y

2 /

V

A

+

=

+

−

=

Instead of half differential input, dc gain with respect to full differential input is desired. That is,

ds4 ds2

m2 ds4

ds2 m1 id

O 1 2 VDO

g

V

A

+

=

+

=

(8)

VG1

VGS1

VSS _VG2

VGS2 VDD

VSS VC

VSS Vo

+

-M6 w=21.6u l=1.2u

M1 w=9.6u l=5.4u

M2 w=9.6u l=5.4u M4 w=25.8u l=5.4u M3

w=25.8u l=5.4u

M5 w=21.6u l=1.2u

ISS=220uA ID2

ID4 IO

ID1 ID3

(1) (2)

(8)

(9)

(4) (3)

(6) (5)

IB=220uA

Figure 4. The Complete Differential Amplifier Schematic Diagram

Figure 3(c) is the resulting two-port equivalent circuit. Except for the polarity this gain equation is identical to that of the single NMOS inverter with PMOS current load. Figure 4 shows the complete differential amplifier implemented using a pair of inverter amplifier with PMOS current load, and 200uA current souce. The PSpice netlist is given below:

* Filename="diffvid.cir"

* MOS Diff Amp with Current Mirror Load *DC Transfer Characteristics vs VID VID 7 0 DC 0V AC 1V

E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5 VIC 10 0 DC 0.65V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT

M1 5 1 8 8 NMOS1 W=9.6U L=5.4U M2 6 2 8 8 NMOS1 W=9.6U L=5.4U M3 5 5 3 3 PMOS1 W=25.8U L=5.4U M4 6 5 3 3 PMOS1 W=25.8U L=5.4U M5 8 9 4 4 NMOS1 W=21.6U L=1.2U M6 9 9 4 4 NMOS1 W=21.6U L=1.2U IB 3 9 220UA

.MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10

+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL PMOS1 PMOS VTO=-1 KP=15U

(9)

+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10

+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .DC VID -2.5 2.5 0.05V

.TF V(6) VID .PROBE .END

The operating point current is determined by the source current ISS, which is split between the two PMOS

current loaded inverters. IDSQ1=IDSQ2=ISS/2, and similarly IDSQ3=IDSQ4=ISS/2. For the given differential

amplifier ISS=220uA. The voltage gain is computed as follows:

87.95uA/V

=

0.5u))

*

2 -5.4u

6)(25.8u/(

-E

15 (

)

L

/

W

(

K

87.3uA/V

=

0.5u))

*

2 -.4u

6)(9.6u/(5

-E

40 (

)

L

/

W

(

K

2 P3 P3 P3 P4 P3 2 N1 N1 N1 N2 N1

=

β

umho

1 .

139 6)

-6)(110E

-E

95 .

87 (

2 I

2 g

g

umho

59 .

138 6)

-6)(110E

-E

3 .

87 (

2 I

2 g

g

DSQ3 P3 m4 m3 DSQ1 N1 m2 m1

=

β

umho

4.4 =

6)

-E

220 (

02 .

I

g

umho

2.2 =

6)

-E

110 (

02 .

I

g

umho

2.2 =

6)

-E

110 (

02 .

I

g

DSQ5 P DSQ DS5 ds5 DSQ1 P DSQ4 DS4 ds4 DSQ1 N DSQ2 DS2 ds2

=

λ

5 .

31

6 -2.2E

+

6 -2.2E

6 -E

59 .

138 g

g

A

ds4 ds2 m1

(10)

The low frequency input resistance Rin = ∞. The output resistance Rout = 1/(gds2+gds4)= 1/(2.2E-6+2.2E-6)

=.2272M, see Figure 3(d), and the computation above. These calculations agree well with Pspice simulation results of:

**** SMALL-SIGNAL CHARACTERISTICS V(6)/VID = 3.347E+01

INPUT RESISTANCE AT VID = 1.000E+20 OUTPUT RESISTANCE AT V(6) = 2.423E+05

(11)

VG1

VGS1

VSS VG2

VGS2 VDD

VSS VC VSS

ISS

M3 _M4

M1 M2

S3

D3 D1

S1

S4

D4 D2

S2 gds1

gds2

gm4vgs4

gm2vgs2 gm1vgs1

M5 VGG +

VIC

+ VIC

gds5

Vo +

-Vo +

-gm3 gds3 gds4

VC

VDS5 VDG1

VSD3 VSD4

Vgs3 Vgs4

Figure 5. Differential Amplifier with Purely Common-mode Input Signal: (a) Schematic Diagram, and (b) Small Signal Equivalent Circuit.

The input common-mode range is the range of common-mode voltage Vic=VG1=VG2 in which all

the transistors are operating in saturation region. To determine this a purely common-mode input is applied at both inputs, see Figure 5.

3.1 Maximum VG1 or VG2 Determination

As VG1 approaches VDD transistor M1 and M2 go into the triode region. VG1(max) is the value

of the input when it occurs. This can be determined from Figure 5 by writing the KVL equation from VDD

(12)

G

=

D

since

,

V

=

V

DG1 SG3

DD

DG1 SD3

DD G1

−

=

|

V

|

I

|

2 |

V

|

|)

V

|

V

(|

V

_TP3

P3 DS3 TP3

TP3 GS3

SG3

=

−

+

=

_β

+

DG1 TP3

P3 DS3 DD

G1

|

V

|

V

|

I

|

2 V

V

=

−

β

From Figure 5(a), VDG1 can be determined in term of the commonly known transistor voltages of M1.

DG1 GS1

DS1

GS1 DS1 DG1

V

or

V

-V

V

+

=

Transistor M1 is on saturation when the following condition holds. DG1

GS1 DS1

TN1

GS1

V

−

≤

=

+

That is,

DG1 TN1

V

≤

−

The minimum value of VDG1 is achieved when transistor M1 is on the threshold of saturation. That is,

DG1 TN1

V

=

−

The maximum input voltage is obtained when

−

V

_TN1

=

V

_DG1. That is,

P3 SS DD

P3 DS3 DD

TN1 TP3

P3 DS3 DD

G1

I

V

|

I

|

2 V

V

|

V

|

I

|

2 V

(max)

V

β

−

=

−

=

+

−

=

--(25)

Assuming |VTP3| ≈VTN1.

(13)

As VG1 approaches VSS, M1 becomes cutoff. The minimum input voltage VG1 is determined when

M5 is no longer in saturation. This is obtained by writing the KVL equation from VSS to VG1.

GS1 DS5

SS

G1

V

=

+

Transistor M5 is on saturation when, DS5

TN5

GS5

V

−

≤

M5 is at verge of saturation when,

V

_GS5

−

V

_TN5

=

V

_DS5

=

V

_DS5(SAT)

That is, the minimum input voltage occurs when,

V

_GS5

−

V

_TN5

=

V

_DS5(SAT).

GS1 DS5(SAT)

SS

G1

(min)

V

=

+

--(26)

GS1 TN5

GS5 SS

G1

(min)

V

(V

V

)

V

=

+

−

+

N1 SS GG

N1 DS1 GG

TN1 N1

DS1 TN5

GG

TN1 TN1

GS1 TN5

SS GG SS

G1

I

V

2I

V

2I

V

)

V

-V

(

)

V

(

V

(min)

V

β

+

=

+

=

+

−

=

+

−

+

=

--(27)

Ignoring the bulk bias effect.

Using the SPICE parameters for the differential amplifier implemented in Figure 4. From Eq(25),

P3 SS DD

G1

I

V

(max)

V

β

−

=

2 3

3 P

P3

=

K

(

W

/

L

)

=

(

15 E

-

6)(25.8u/(

5.4u

-

2 *

0.5u))

=

87.95 uA/V

β

V

92 .

0

58 .

1

5 .

2

6 -87.95E

6 -E

220

5 .

2 (max)

V

_G1

=

−

=

−

=

and from Eq(27),

V

38 .

0

2 .

1

58 .

1

2 .

1

87.3

6 -E

220 V

I

(min)

V

_GG

N1 SS

G1

=

_β

+

=

−

=

−

=

To guarantee that the differential amplifier stays on the linear region of operation, set common-mode signal at half way the common-mode range. That is, VIC=[VG1(max)+VG1(min)]/2=[0.92+.38]/2=0.65.

4. Low Frequency Small Signal Equivalent Circuit With Pure Common-Mode Input

Signal

(14)

2gm1vgs1 D1

S1

D3

S3 +

-G1

+

-V2=vo V1=Vic

gds5

gds

1

+g

ds2

gds

3

+g

ds4

+g

m3

+gm4

Vgs1

D5

S5 VC

YL

(c)

gm1vgs1 gm2vgs2 _gds2 gds4

G1 D1

S1

S3

D2

S2

D4

S4 D3=G3=G4

+

-vo +

-vgs1

+

-gds5 +

-Vic

Vc vgs3

gds

1

D5

gm4 v gs

4

S5

+

-vgs4

gds

3

+g

m3

gds

4

+g

m4

gm1vgs1 gm2vgs2 gds2

G1 D1

S1

S3

D2

S2

D4

S4 D3=G3=G4

+

-vo +

-vgs1

+

-gds5 +

-Vic

Vc vgs3

gds

1

gds

3

+g

m3

D5

S5

(b) (a)

I2

Figure 6. Small Signal Equivalent Circuit: (a) Original Small Signal Equivalent Circuit, (b) Accounting for Source Values and Polarities, and (c) Two-port Conversions.

Figure 5(a) shows the schematic when a purely common-mode input is applied at both inputs that is, VG1=VG2 =VIC . If VIC increases both ID1 and ID2 increases. Their sum at the common node VC also

increases. Figure 5(b) shows that VC is not at ac ground, unlike the pure differential input signal case

shown in Figure 2(b). Due to signal symmetry when both inputs are the same, VDS3=VDS4. Since both G

and S of M3 and M4 are connected to each other, means VGS3=VGS4. M3 is diode connected with G and D

(15)

across D and S of M4 can be labelled as VGS4, see Figure 6(a). The current source of M4 is therefore

reduced to conductance gm4, see Figure 6(b). Since VDS3=VDS4, the D3 and D4 can be connected together.

Figure 6(c) shows the final equivalent circuit after combining all components that are in parallel. From Figure 6(c), the following two-port variables and load are obtained.

O 2 IC 1 m3 ds4 ds3 m3 ds3 m4 m3 ds4 ds3 L

V

and

V

g

assuming

g

2 g

g

Y

=

+

=

+

=

m4

The two-port current equations are derived to obtain the Y parameters.

2 m1 ds5 ds2 ds1 ds5 ds2 ds1 1 m1 ds5 ds2 ds1 ds5 m1 2 2 ds5 m1 ds2 ds1 2 ds2 ds1 1 m1 2 2 ds5 C C m1 ds2 ds1 2 ds2 ds1 1 m1 C 1 m1 C 2 ds2 ds1 2 1

V

2g

g

)g

g

(

V

2g

g

2 I

I

g

1 )

2g

g

(g

-)V

g

(g

V

2g

I

g

1 V

)V

2g

g

(g

-)V

g

(g

V

2g

)

V

-(V

2g

)

V

-)(V

g

(g

I

0 I

+

=

+

=

+

=

+

=

The Y-parameter matrix is:

m4 m3 ds2 ds1 m1 ds5 ds1 ds5 ds1 m1 ds5 ds1 ds5 m1 m1 ds5 ds2 ds1 ds5 ds2 ds1 m1 ds5 ds2 ds1 ds5 m1

g

assuming

2g

g

2g

g

2 2g

g

2g

g

2

0

0 2g

g

)g

g

(

2g

g

2

0

0 Y

=













+

=













+

=

(16)

.

g

assuming

r

g

2

1 r

g

2 g

g

r

g

2

1 g

g

2g

1 g

g

)

2g

g

2g

)(

g

(

2 g

g

2 g

g

2 )

g

(

2 2g

g

2g

g

2 2g

g

2g

g

2 Y

y

A

ds3 m3

ds5 m3 ds5

m1 m3 m1

ds5 m1

m3 m1

ds5 m1 ds1

m3 ds1

m3 m1

m1 ds5

ds1 m3 ds3 ds5

ds1

ds5 m1

m3 ds3 m1

ds5 ds1

m1 ds5

ds1

ds5 m1

L 22

21 VC0

>>

−

≈

−

≈

+

−

≈

+

−

=

+

−

=

+

−

=

+

−

=

* Filename="diffvic.cir"

* MOS Diff Amp with Current Mirror Load *DC Transfer Characteristics vs VIC VID 7 0 DC 0V

E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5 VIC 10 0 DC 0V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT

M1 5 1 8 8 NMOS1 W=9.6U L=5.4U M2 6 2 8 8 NMOS1 W=9.6U L=5.4U M3 5 5 3 3 PMOS1 W=25.8U L=5.4U M4 6 5 3 3 PMOS1 W=25.8U L=5.4U M5 8 9 4 4 NMOS1 W=21.6U L=1.2U M6 9 9 4 4 NMOS1 W=100.8U L=3.6U M7 9 9 3 3 PMOS1 W=3.6U L=3.6U .MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6

+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6

+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .OP

.DC VIC -2.5 2.5 0.05V .TF V(6) VIC

.PROBE .END

(17)

01582

.

0 )

6)(.2272E6

-E

1 .

139 (

2

1 r

g

2

1 A

ds5 m3

VCO

=

−

=

−

=

−

This is very closed to the PSpice simulation result. **** SMALL-SIGNAL CHARACTERISTICS

(18)

V(6)/VIC = -1.459E-02

INPUT RESISTANCE AT VIC = 1.000E+20 OUTPUT RESISTANCE AT V(6) = 2.386E+05

The goal of differential amplifier is to amplify the difference signal and to reject common-mode signal. A figure of merit called common-mode rejection ration (CMRR) is defined as:

15 .

1991

0.01582

-5

.

31 A

A

CMRR

VC

VD

₌

=

(19)

VG1 +

VGS1

VSS

VG2 + VGS2 VDD

VSS VC VSS

ISS

M3 M4

M1 M2

CL Cgd2

Cdb4 Cdb2

Cgs4 Cgs3

Cgd4 Cdb3

Cgd1

(a) Cdb1

VGS1

VSS

VGS2

VSS VC VSS

ISS

M3 M4

M1 M2

C2 C3

C1

(b) VDD

VG2 + VG1

+

C1=Cgd1+Cdb1+Cdb3+Cgs3+Cgs4 C2=Cgd2+Cdb2+Cdb4+CL C3=Cgd4

(1) (2)

(5) (6)

(8)

Figure 7. Parasitic Capacitances of Differential Amplifier Operating in Purely Differential Input Signal: (a) Parasitic Capacitances of each Transistor, (b) Lumped Parasitic Capacitances.

Figure 7(a) shows all the parasitic capacitances of the differential amplifier with purely

differential input signals. Since both inputs are voltage sources, they are at ac ground when considering the effects of gate capacitances. Figure 7(b) shows that there are basically three capacitances. These are:

gd4 3

L db4 db2 gd2 2

gs4 gs3 db3 db1 gd1 1

C

=

+

=

+

=

(20)

gm1(vid/2)

gds

1

+gds3

+g

m3

C1 C3

gm2(vid/2) gm4vgs4 gds

2

+g

ds

4

C2 G1 D1

S1

D3=G3=G4

S3

D2 D4

S2 S4

+ vo

-+

vid/2

-gm1(vid/2) gm1(vid/2) gm4vgs4 G1 D1

S1

D3=G3=G4

S3

D2 D4

S2 S4

+

-+

-I3 + -Vgs4

C1=Cgd1+Cdb1+Cdb3+Cgs3+Cgs4 C2=Cgd2+Cdb2+Cdb4+CL

C3=Cgd4 (a)

(b) Y3

Y1 Y2

V1=Vid/2 _V2=VO

=

gm1=gm2

Figure 8. High Frequency Small Signal Equivalent Circuit: (a) Small Signal Equivalent Circuit Showing Lumped Capacitances, (b) Small Signal Equivalent Circuit Combining Capacitance and Resistance to Admittance.

NOTE C3 is not a miller capacitance, it is connected between the outputs of the two inverter amplifiers,

and not between an output and an input terminals of an amplifier. C3 in this case is normally small and can

be ignored. Figure 8(b) shows that the three admittances are given by:

gd4 3

3

2 ds4 ds2 2

1 m3 ds3 ds1 1

C

Y

C

g

Y

C

g

Y

s

=

+

=

+

=

The two-port Y parameters are to be determined. Figure 8(b) shows that the two-port variables are:

O 2

id 1 L

V

and

2 /

V

0 Y

=

(21)

2 3 1 3 m1 3 2 3 1 2 1 1 3 1 m4 m1 1 m1 2 3 1 3 1 3 1 m1 m4 3 2 3 2 1 m1 2 2 3 1 3 1 3 1 m1 gs4 gs4 gs4 2 3 1 m1 gs4 1 gs4 1 3 gs4 2 3 1 m1 3 gs4 m4 3 2 3 2 1 m1 2 2 gs4 m4 1 m1 gs4 2 3 2 1

V

Y

g

Y

V

Y

g

-Y

g

)

V

Y

V

Y

g

)(

g

Y

(

)V

Y

(

V

-g

I

V

Y

V

Y

g

V

for

Solve

0 )

V

-(V

Y

-V

g

V

Y

V

Y

I

0 )

V

-(V

Y

-V

g

I

D3

node

At

)V

g

Y

(

)V

Y

(

V

-g

V

Y

V

g

V

g

-)

V

-(V

Y

I

0 I

+

=

+

−

+

−

+

=

+

−

=

+

=

+

−

+

=

+

=

The Y-parameter matrix is:













+

=

3 1 3 m1 3 2 3 1 2 1 3 1 m4 m1 1 m1

Y

g

Y

g

-Y

g

-

0

0 Y

For differential amplifier the assumption that Y3 or C3 is approximately 0 is valid. That is,













−

=

2 1 m4 m1 m1

Y

g

-g

0

0 Y

(22)













+













+













+













+

=













+













+













+













+

=

+

=

+

=

+

=

+

=

+

−

=

ds4 ds2 2 m3 ds3 ds1 1 m4 m3 ds3 ds1 1 ds4 ds2 m1 ds4 ds2 2 m3 ds3 ds1 1 m3 ds3 ds1 m4 m3 ds3 ds1 1 m4 m3 ds3 ds1 ds4 ds2 m1 2 ds4 ds2 1 m3 ds3 ds1 1 m4 m3 ds3 ds1 m1 2 ds4 ds2 1 m3 ds3 ds1 m4 m1 2 1 m4 m1 2 1 m4 m1 m1 L 22 21 1 2 VD2

g

C

1 g

g

C

1 g

g

C

1 g

g

2 g

g

C

1 g

g

C

1 )

g

(

g

C

1 )

g

(

g

)

C

g

)(g

C

g

(g

)

C

g

(g

g

)

C

g

(g

)

C

g

(1

g

Y

)

Y

g

(1

g

Y

g

Y

y

V

A

s

The differential gain when the input voltage V1 is changed to VID is:

1 m3 1 m4 m3 ds3 ds1 1 m3 1 m3 ds3 ds1 2 2 ds4 ds2 1 1 2 VDO ds4 ds2 2 m3 ds3 ds1 1 m4 m3 ds3 ds1 1 ds4 ds2 m1 id O VD

C

2g

C

g

z

C

g

C

g

p

C

g

p

:

where

)

p

1 )(

p

1 (

)

z

1 (

A

g

C

1 g

g

C

1 g

g

C

1 g

g

V

A

−

≈

+

−

=

−

≈

+

−

=

+

−

=

−

=













+













+













+













+

=

s

p1 << p2 << z

NOTE the differential voltage gain has pole-zero doublets. That is, the zero z is double that of the non-dominant pole p2. The dominant (lowest frequency) pole p1 occurs at the output node. The above transfer

(23)

Each node is at a finite impedance with respect to ground. That is, each node there is a resistance Rn (or

conductance) and capacitance Cn to ground. To determine which poles are dominant (or more significant),

the impedance levels must be monitored. The parasitic capacitances Cn are of approximately the same

magnitude, but Rn usually vary considerably. When the resistance (conductance) is high (low), a dominant

pole is generated. The impedance levels are summarized in the follwing table:

Node(From Netlist) Resistance Capacitance Pole

1 0 (ac ground) X

2 0 (ac ground) X

5 R5=1/(gds1+gds3+gm3) C1 p2=1/(R5C1)*

6 R6=1/(gds2+gds4) C2 p1=1/(R6C2)

8 0 (ac ground) X

The derivation shows that the pole p2 create a zero doublet.

* Filename="diffreq.cir"

* MOS Diff Amp with Current Mirror Load *DC Transfer Characteristics vs VID VID 7 0 DC 0V AC 1V

E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5 VIC 10 0 DC 0.65V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT

M1 5 1 8 8 NMOS1 W=9.6U L=5.4U M2 6 2 8 8 NMOS1 W=9.6U L=5.4U M3 5 5 3 3 PMOS1 W=25.8U L=5.4U M4 6 5 3 3 PMOS1 W=25.8U L=5.4U M5 8 9 4 4 NMOS1 W=21.6U L=1.2U M6 9 9 4 4 NMOS1 W=100.8U L=3.6U M7 9 9 3 3 PMOS1 W=3.6U L=3.6U .MODEL NMOS1 NMOS VTO=1 KP=40U

+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .AC DEC 100 1HZ 100000GHZ

.PROBE .END

(24)

(25)

VG1

VGS1

VSS VG2

VGS2 VDD

VSS VC VSS

M3 _M4

M1 M2

M5 VGG

+ VIC

Vo +

-Cdb5 Csb2 Csb1 Cgd5

VG1

VGS1

VSS VG2

VGS2 VDD

VSS

VC VSS

M3 _M4

M1 M2

M5 VGG

+ VIC

Vo +

-CS

CS=Csb1+Csb2+Cdb5+Cgd5

Figure 9. Differential Amplifier Operating in Pure Common-Mode Input Signal: (a) All Parasitic Capacitances at Common Node Vc, (b) Total Capacitances Across the Drain and Source of M5.

From the expression of the dc common-mode gain, it is primarily a function of gm3 and rds5. The

first order frequency response analysis can be simplified by ignoring all parasitic capacitances except the capacitance CS across rds5, see Figure 9. That is rds5 is replaced by zds5 in the the common-mode gain

(26)

gd5 db5 sb2 sb1 S

ds5 m3

S ds5

S ds5 ds5 m3

ds5 m3 VC

S ds5 ds5 S

ds5 ds5

C

:

where

r

g

2 )

C

r

1 (

C

r

1 r

g

2

1 z

g

2

1 A

C

r

1 r

)

//C

r

(

z

+

=

+

−

=

+

−

=

−

=

+

=

s

* Filename="diffreqc.cir"

E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5

VIC 10 0 DC 0.65V AC 1V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT

M1 5 1 8 8 NMOS1 W=9.6U L=5.4U M2 6 2 8 8 NMOS1 W=9.6U L=5.4U M3 5 5 3 3 PMOS1 W=25.8U L=5.4U M4 6 5 3 3 PMOS1 W=25.8U L=5.4U M5 8 9 4 4 NMOS1 W=21.6U L=1.2U M6 9 9 4 4 NMOS1 W=100.8U L=3.6U M7 9 9 3 3 PMOS1 W=3.6U L=3.6U .MODEL NMOS1 NMOS VTO=1 KP=40U

+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .AC DEC 100 1HZ 100000GHZ

.PROBE .END

(27)

The differential-mode voltage gain decreases with increasing frequency but common-mode voltage increases. Therefore, CMRR decreases with increasing frequency.

7. Designing Differential Amplifier With Specified CMR

Given a common-mode range of –0.75 <= VIC <=0.75 , VGG=-1, ISS=IDS5=100uA, Lmin=5.4u,

. Determine the size of each transistor in the differential amplifier circuit, see Figure 4.

5 .

0 V

V

=

_GS

−

_TN

=

∆

1. Determine the (W/L)5 to sink 100uA.













=

























=

u

4 .

5 u

108

20 1]

-(-2.5)

-6)[-1

-(40E

6)

-E

100 (

2 )

V

-V

(

K

I

2 )

V

-V

(

K

I

2 L

W

)

V

-V

(

L

W

2 K

)

V

-V

(

2 I

2

2 TN5 SS GG N

DS5 2

TN5 GS5 N

DS5 5

2 TN5 GS5 5 N 2 TN5 GS5 N5 DS5

β

2. Determine (W/L)1 =(W/L)2 from VIC(min)=VG1(min) specification

(28)













=













=













=

−

=

−

≥

−

≥

+

=

u

4 .

5 u

216

40 1)

-6)(1.25

-E

40 (

6)

-E

50 (

2 )

V

-(V

K

I

2 L

W

L

W

25 .

1

5 .

0 )

5 .

2 (

75 .

0 V

V

75 .

0 V

75 .

0 V

V

min)

(

V

2 2 TN GS1 N DS1 2 1 DS5(SAT) SS GS1 GS1 DS5(SAT) SS G1 IC

3. Determine (W/L)3=(W/L)4 from VIC(max)=VG1(max) specification

From Eq(25),













=

























=

−

=

u

4 .

5 u

75 .

11

177 .

2 0.75)

-6)(2.5

-E

15 (

6)

-E

50 (

2 (max))

V

-(V

K

|

I

|

2 L

W

(max))

V

-V

(

L

W

2 K

(max))

V

-V

(

2 |

I

|

I

|

2 V

(max)

V

(max)

V

2 2 G1 DD P DS3 3 2 G1 DD 3 P 2 G1 DD P3 DS3 P3 DS3 DD G1 IC

β

The above is simulated using PSpice. The results agree well with the calculations.

* Filename="diffcmr.cir"

E+ 1 10 7 0 0.5 E- 2 10 7 0 -0.5 VIC 10 0 DC 0V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT

M1 5 1 8 8 NMOS1 W=216U L=5.4U M2 6 2 8 8 NMOS1 W=216U L=5.4U M3 5 5 3 3 PMOS1 W=11.75U L=5.4U M4 6 5 3 3 PMOS1 W=11.75U L=5.4U M5 8 9 4 4 NMOS1 W=108U L=5.4U VGG 9 0 DC -1V

.MODEL NMOS1 NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6

+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .DC VIC -2.5 2.5 0.05V

.TF V(6) VIC .PROBE

(29)