256K (32K x 8) Static RAM

256K (32K x 8) Static RAM

Features

• High speed: 55 ns and 70 ns

• Voltage range: 4.5V–5.5V operation

• Low active power (70 ns, LL version)

— 275 mW (max.)

• Low standby power (70 ns, LL version)

— 28 µW (max.)

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages

Functional Description

The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected.

An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O₀ through I/O₇) is written into the memory location addressed by the address present on the address pins (A₀ through A₁₄). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.

A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂

COLUMN DECODER

ROW DECODER SENSE AMPS

INPUTBUFFER

POWER WE DOWN

OE

I/O₀

CE

I/O₁ I/O₂ I/O₃ 512 x 512

ARRAY

I/O₇ I/O₆ I/O₅ I/O₄ A₁₀

A13 A11

A12 A

A14 A1 0

Logic Block Diagram

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

CY62256

Pin Configurations

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature ...–65°C to +150°C Ambient Temperature with

Power Applied... 0°C to +70°C Supply Voltage to Ground Potential

(Pin 28 to Pin 14) ... –0.5V to +7.0V DC Voltage Applied to Outputs

in High-Z State^[2]...–0.5V to V_CC + 0.5V

DC Input Voltage^[2]... –0.5V to V_CC + 0.5V Output Current into Outputs (LOW)... 20 mA Static Discharge Voltage... > 2001V (per MIL-STD-883, Method 3015)

Latch-up Current... > 200 mA 1

2 3 4 5 6 7 8 9 10 11

14 15

16 20 19 18 17 21 24 23 22 Top View Narrow SOIC

12 13

25 28 27 26

GND A6 A7 A8 A9 A10 A11 A12 A13

WE VCC

A4 A3 A2 A1

I/O7I/O6 I/O5 I/O4 A14

A5

I/O0 I/O1 I/O2

CE OE A0

I/O3

22 23 24 25 26 27 28 1 2

5 10

11

15 14 13 12

16

19 18 17 3

4

20 21 7

6

8 9

OE A1 A2 A₃ A₄ WE V_CC A₅ A₆ A7

A₈ A9

A0 CE I/O₇ I/O₆ I/O₅ GND I/O2 I/O1

I/O₄ I/O₀ A₁₄ A₁₀

A₁₁

A₁₃ A12

I/O₃

TSOP I Top View (not to scale) Reverse Pinout

22 23 24 25 26 27 28 1 2

5 10

11 15 14 13 12 16 19 18 17

3 4

20 21

7 6

8 9

OE A₁ A₂ A3 A₄ WE V_CC A5 A6 A7

A₈ A9

A₀ CE I/O7 I/O₆ I/O₅

GND I/O2 I/O₁ I/O₄

I/O₀ A₁₄ A₁₀

A11

A₁₃ A₁₂ I/O₃

TSOP I Top View (not to scale) 1

2 3 4 5 6 7 8 9 10 11

14 15

16 20 19 18 17 21 24 23 22 Top View

DIP

12 13

25 28 27 26

GND A6 A7 A8 A9 A10 A11 A12 A13

WE VCC

A4 A3 A2 A1

I/O7I/O6 I/O5 I/O4 A14

A5

I/O0 I/O1 I/O2

CE OE A0

I/O3

Operating Range

Range Ambient Temperature V_CC Commercial 0°^{C to +70}°^{C 5V} ± 10%

Industrial –40°^{C to +85}°^{C 5V} ± 10%

Electrical Characteristics

CY62256−55 CY62256−70

Unit Min. Typ.^[3] Max. Min. Typ.^[3] Max.

V_OH Output HIGH Voltage V_CC = Min., I_OH = −1.0 mA 2.4 2.4 V

V_OL Output LOW Voltage V_CC = Min., I_OL = 2.1 mA 0.4 0.4 V

V_IH Input HIGH Voltage 2.2 V_CC

+0.5V

2.2 V_CC

+0.5V V

V_IL Input LOW Voltage –0.5 0.8 –0.5 0.8 V

I_IX Input Leakage Current GND < V_I < V_CC –0.5 +0.5 –0.5 +0.5 µA

I_OZ Output Leakage Current GND < V_O < V_CC, Output Disabled –0.5 +0.5 –0.5 +0.5 µA I_CC V_CC Operating Supply

Current

V_CC = Max., I_OUT = 0 mA, f = f_MAX = 1/t_RC

28 55 28 55 mA

L 25 50 25 50 mA

LL 25 50 25 50 mA

I_SB1 Automatic CE

Power-down Current—

TTL Inputs

Max. V_CC, CE > V_IH, V_IN > V_IH or V_IN < V_IL, f = f_MAX

0.5 2 0.5 2 mA

L 0.4 0.6 0.4 0.6 mA

LL 0.3 0.5 0.3 0.5 mA

Notes:

2. V_IL (min.)= −2.0V for pulse durations of less than 20 ns.

3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (T_A = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.

I_SB2 Automatic CE

Power-down Current—

CMOS Inputs

Max. V_CC, CE > V_CC− 0.3V V_IN > V_CC− 0.3V, or V_IN <

0.3V, f = 0

1 5 1 5 mA

L 2 50 2 50 µA

LL 0.1 5 0.1 5 µA

Indust’l Temp Range LL 0.1 10 0.1 10 µA

Capacitance

Parameter Description Test Conditions Max. Unit

C_IN Input Capacitance T_A = 25°C, f = 1 MHz, V_CC = 5.0V

6 pF

C_OUT Output Capacitance 8 pF

Electrical Characteristics

CY62256−55 CY62256−70

Unit Min. Typ.^[3] Max. Min. Typ.^[3] Max.

AC Test Loads and Waveforms

Data Retention Characteristics

Parameter Description Conditions^[5] Min. Typ.^[3] Max. Unit

V_DR V_CC for Data Retention 2.0 V

I_CCDR Data Retention Current L V_CC = 3.0V, CE > V_CC− 0.3V, V_IN > V_CC− 0.3V, or V_IN < 0.3V

2 50 µA

LL 0.1 5 µA

LL Ind’l 0.1 10 µA

t_CDR^[4] Chip Deselect to Data Retention Time 0 ns

t_R^[4] Operation Recovery Time t_RC ns

Data Retention Waveform

Notes:

4. Tested initially and after any design or process changes that may affect these parameters.

5. No input may exceed V_CC + 0.5V.

3.0V 5V

OUTPUT

R1 1800Ω

R2990Ω 100 pF

INCLUDING JIG AND SCOPE

GND 10% 90%

90%

10%

< 5 ns < 5 ns

5V OUTPUT

R1 1800Ω

R2990Ω 5 pF

INCLUDING JIG AND SCOPE

(a) (b)

OUTPUT 1.77V

Equivalent to: THÉ VENIN EQUIVALENT

ALL INPUT PULSES

639Ω

3.0V 3.0V

t_CDR

V_DR> 2V DATA RETENTION MODE

t_R CE

V_CC

CY62256

Switching Characteristics

Parameter Description

CY62256−55 CY62256−70

Unit

Min. Max. Min. Max.

Read Cycle

t_RC Read Cycle Time 55 70 ns

t_AA Address to Data Valid 55 70 ns

t_OHA Data Hold from Address Change 5 5 ns

t_ACE CE LOW to Data Valid 55 70 ns

t_DOE OE LOW to Data Valid 25 35 ns

t_LZOE OE LOW to Low-Z^[7] 5 5 ns

t_HZOE OE HIGH to High-Z^{[7, 8]} 20 25 ns

t_LZCE CE LOW to Low-Z^[7] 5 5 ns

t_HZCE CE HIGH to High-Z^{[7, 8]} 20 25 ns

t_PU CE LOW to Power-up 0 0 ns

t_PD CE HIGH to Power-down 55 70 ns

Write Cycle^{[9, 10]}

t_WC Write Cycle Time 55 70 ns

t_SCE CE LOW to Write End 45 60 ns

t_AW Address Set-up to Write End 45 60 ns

t_HA Address Hold from Write End 0 0 ns

t_SA Address Set-up to Write Start 0 0 ns

t_PWE WE Pulse Width 40 50 ns

t_SD Data Set-up to Write End 25 30 ns

t_HD Data Hold from Write End 0 0 ns

t_HZWE WE LOW to High-Z^{[7, 8]} 20 25 ns

t_LZWE WE HIGH to Low-Z^[7] 5 5 ns

Switching Waveforms

Notes:

6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I_OL/I_OH and 100-pF load capacitance.

7. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.

8. t_HZOE, t_HZCE, and t_HZWE are specified with C_L = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

9. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.

10. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD 11. Device is continuously selected. OE, CE = V_IL.

12. WE is HIGH for Read cycle.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

t_RC

t_AA t_OHA Read Cycle No. 1 ^{[11, 12]}

Notes:

13. Address valid prior to or coincident with CE transition LOW.

14. Data I/O is high impedance if OE = V_IH.

15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Switching Waveforms

50% 50%

DATA VALID t_RC

t_ACE

t_DOE t_LZOE

t_LZCE t_PU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC ISB t_HZOE

t_HZCE

t_PD OE

CE

HIGH

V_CC SUPPLY CURRENT

Read Cycle No. 2 ^{[12, 13]}

t_HD t_SD

t_PWE t_SA

t_HA t_AW

t_WC

DATA I/O ADDRESS

CE

WE

OE

t_HZOE

DATA_INVALID NOTE

Write Cycle No. 1 (WE Controlled)[9, 14, 15]

16

t_WC

t_AW t_SA

t_HA

t_HD t_SD

t_SCE

WE

DATA I/O ADDRESS CE

DATA_INVALID Write Cycle No. 2 (CE Controlled) [9, 14, 15]

CY62256

Note:

16. During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms

DATA I/O ADDRESS

t_HD t_SD

t_LZWE t_SA

t_HA t_AW

t_WC

CE

WE

t_HZWE

DATA_INVALID Write Cycle No. 3 (WE Controlled, OE LOW) ^{[10, 15]}

NOTE 16

Typical DC and AC Characteristics

1.2 1.4

1.0

0.6 0.4 0.2

4.0 4.5 5.0 5.5 6.0

1.6

1.4

1.2

1.0

0.8

−55 25 125

−^{55 25 125}

1.2 1.0 0.8

NORMALIZED tAA

120 100 80 60 40 20

0.0 1.0 2.0 3.0 4.0

OUTPUT SOURCE CURRENT (mA)

SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 0.0

0.8

1.4

1.1 1.0 0.9

4.0 4.5 5.0 5.5 6.0

NORMALIZED t

SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE

120 140

100

60 40 20

0.0 1.0 2.0 3.0 4.0

OUTPUT SINK CURRENT (mA)

0 80

OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 0.6

0.4 0.2 0.0 NORMALIZED I CC

NORMALIZED I , ICCSB I_CC

ICC

V_CC=5.0V

V_CC=5.0V T_A=25°C

V_CC=5.0V T_A=25°C I_SB

T_A=25°C

0.8 0.6

0

AA

1.3 1.2

V_IN=5.0V T_A=25°C

1.4

VCC=5.0V V_IN=5.0V

−^{55 25 105}

2.5 2.0 1.5

CURRENT vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C) 1.0

0.5 0.0 -0.5

I_SB 3.0

STANDBY

V_CC=5.0V V_IN=5.0V ISB2µA

CY62256

Typical DC and AC Characteristics

3.0 2.5 2.0 1.5

1.0 0.5

0.0 1.0 2.0 3.0 4.0 NORMALIZED IPO

SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE

30.0 25.0 20.0 15.0

10.0 5.0

0 200 400 600 800 DELTA t (ns)AA

CAPACITANCE (pF) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING

1.25

1.00

0.75

10 20 30 40

NORMALIZED ICC

CYCLE FREQUENCY (MHz) NORMALIZED I_CCvs.CYCLE TIME

0.0

5.0 0.0

1000 0.50 V_CC=4.5V

T_A=25°C

V_CC=5.0V T_A=25°C V_IN=0.5V

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High-Z Deselect/Power-down Standby (I_SB)

L H L Data Out Read Active (I_CC)

L L X Data In Write Active (I_CC)

L H H High-Z Deselect, Output Disabled Active (I_CC)

Ordering Information

Speed

(ns) Ordering Code

Package

Name Package Type

Operating Range 55 CY62256LL−55SNI SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Industrial

CY62256LL−55ZI Z28 28-lead Thin Small Outline Package

70 CY62256−70SNC SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial CY62256L−70SNC

CY62256LL−70SNC

CY62256L–70SNI Industrial

CY62256LL−70SNI

CY62256LL−70ZC Z28 28-lead Thin Small Outline Package Commercial

CY62256LL−70ZI Z28 Industrial

CY62256−70PC P15 28-lead (600-Mil) Molded DIP Commercial

CY62256L−70PC P15

CY62256LL−70PC P15

CY62256LL−70ZRI ZR28 28-lead Reverse Thin Small Outline Package Industrial

Package Diagrams

51-85017-A

28-lead (600-mil) Molded DIP P15

51-85092-*B

28-lead (300-mil) SNC (Narrow Body) SN28

Document #: 38-05248 Rev. *B Page 10 of 11

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams

28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28

51-85071-*G

51-85074-*F

28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28

Document Title: CY62256 256K (32K x 8) Static RAM Document Number: 38-05248

REV. ECN NO.

Issue Date

Orig. of

Change Description of Change

** 113454 03/06/02 MGN Change from Spec number: 38-00455 to 38-05248

Remove obsolete parts from ordering info, standardize format

*A 115227 05/23/02 GBI Changed SN Package Diagram

*B 116506 09/04/02 GBI Added footnote 1.

Corrected package description in Ordering Information table