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Accelerating the next technology revolution

Welcome & Introduction

Sitaram Arkalgud, PhD

Director – Interconnect

Temporary Bond Workshop – SEMICON West

July 11, 2011

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Outline

SEMATECH Overview

SEMATECH Assessment of key 3D detractors

Temporary Bond/Debond Background

SEMATECH’s supplier landscape evaluation in 2010

Assessment from SEMATECH Workshop at SEMICON

Taiwan (September 2010)

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Scope of technical TSV program

Materials:

Liner, barrier, seed

Plating chemistry

Bond materials

Temporary, tack

Permanent

Equipment Development

Unit Process Development

TSV Module

Bond Module

Thin and handle

Backside processing

Metrology

Infrared

Acoustic

x-ray techniques

Standard techniques

Integration

Passive TSV daisy chains

TSV DtW daisy chains

Device interactions

65nm and 30 nm planar/non-planar

Keep out area

Thermo-mechanical modeling/simulation

Electrical modeling/simulation

Early reliability

0.00 0.05 0.10 0.15 0.20 0.25 0 10 20 30 40 50 60 70 Force , m Strain, mm Cu-Cu : Voids Cu-Cu : Void Free

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SEMATECH 3D Program Organization

GF, HP, Hynix, IBM, Intel, Samsung, TSMC, UMC, CNSE

Unit Process

TSV Module

Thin

Bond

Metrology

Module Development

Baseline/Yield

Device Interaction

Reliability

Modeling/Simulation

Test Vehicles

Enablement Center

Standards

Metrology/Inspection

Microbumping/bonding

Enablement Center Relationship to SEMATECH’s overall 3D Program

3D Enablement Center members (non SEMATECH Members) leverage core

program reference flows, program tooling, test structures, etc.

No outflow of unit processes, equipment development, integration and early reliability

data to 3D Enablement Center

Atotech, Lasertec, NEXX, TEL

Chip – chip interoperability,

standards and specs for the

interface

Technology development

ADI, Altera, ASE, LSI, NIST, ON,

Qualcomm

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SEMATECH’s role

Members can, through SEMATECH, orchestrate major industry-wide

technology transitions and minimize risk

EUV, 450 mm, 3D (standards and infrastructure), disruptive materials/

devices

SEMATECH is the only consortium focused on manufacturable

technology solutions and critical infrastructure

EUV mask infrastructure, metrology, 3D, III-V

SEMATECH’s R&D can complement members’ core development

activities to quickly narrow technology options

Members can benefit from cost sharing and significant government

(50%) leverage

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(7)

Lack Of Industry-wide Readiness In

Critical 3D Areas

HVM is unrealistic unless the gaps are addressed now

Temporary bond/debond is a critical gap

As a neutral consortium, SEMATECH is in a position to play

a critical role in this transition

This workshop

Followup workshop at SEMICON Taiwan – September 9, Hsinchu

5x50 Via-mid Manufacturability

RIE liner barrier /seed (PVD) plate CMP handle wafer bond back grind TSV reveal handle wafer debond

Process performance (vs technical requirements) 1 1 2 1 1 1 1 1 2 1 ready

Repeatability, uniformity, process window 1 1 1 1 1 2 2 3 3 2 close but not quite

Tool availability / maturity 1 1 2 1 1 3 2 2 3 3 not ready

Throughput / cost of ownership 2 1 2 2 2 2 2 2 2

Manufacturability Readiness Key

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Temporary bonding/debonding

Several options identified from tool and materials evaluations

Thermal, solvent, laser debond ….

Materials Material Type Bond Mechanism Bonding Conditions Debond Mechanism Debond Temperature Carrier Equipment Supplier Material A not specified Thermal Reflow T = 160-190ºC F = 8kN t =1-3 min Thermal Slide Off T = 220ºC Standard Si or Glass Wafer A/B Material B Acrylic UV Cure T = 25ºC F = 8kN t not specified Laser Release T = 25ºC Larger Diameter Glass Wafer B/C Material C Silicone Thermal Cure T = 180ºC F = 8kN t not specified Mechanical Release (CVD Layer) T = 25ºC Standard Si or Glass Wafer B Material D not specified Thermal Reflow T = 175ºC F = 0.7 kN t = 50sec Solvent Release T = 25ºC Perforated Larger Diameter Glass Wafer D Material E Polyimide Thermal Cure T = 350ºC F = 5kN t =10 min All T = 250ºC (thermal slide-off) Debond Process Dependent A/B

(9)

Temporary bonding/debonding

Several options identified from tool and materials evaluations

Thermal, solvent, laser debond ….

No industry consensus observed on best options for temporary bond/debond (SEMATECH survey)

integration dependent

Closing temporary bonding gap would drive critical mass and accelerate 3D technology into HVM

Materials Material Type Bond Mechanism Bonding Conditions Debond Mechanism Debond Temperature Carrier Equipment Supplier Material A not specified Thermal Reflow T = 160-190ºC F = 8kN t =1-3 min Thermal Slide Off T = 220ºC Standard Si or Glass Wafer A/B Material B Acrylic UV Cure T = 25ºC F = 8kN t not specified Laser Release T = 25ºC Larger Diameter Glass Wafer B/C Material C Silicone Thermal Cure T = 180ºC F = 8kN t not specified Mechanical Release (CVD Layer) T = 25ºC Standard Si or Glass Wafer B Material D not specified Thermal Reflow T = 175ºC F = 0.7 kN t = 50sec Solvent Release T = 25ºC Perforated Larger Diameter Glass Wafer D Material E Polyimide Thermal Cure T = 350ºC F = 5kN t =10 min All T = 250ºC (thermal slide-off) Debond Process Dependent A/B 0 1 2 3 4 5 6 # r esp o n ses Num

Number of companies using each strategy for at least one integration product

L aser ab lat ab le T h er m o p last ic P eel ab le R T d e bo nd a bl e C h em ical ly re m o vab le S u pp or t r in g Ot h e r Un s u re , DK

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SEMATECH Survey on Gaps in the Via-Mid Ecosystem

Gaps in Standards and Specifications

Gaps in Standards and Specifications

EDA Exchange Formats

Partitioning and floorplanning; Logic verification;

Power/Signal integrity analysis; Thermal analysis

flow; Stress analysis flow; Physical verification;

Timing analysis

Reliability

Reliability test methods

Test

DFT test access architecture

Inspection/metrology

TSV voids, defect mapping, microbump

inspection and coplanarity

Chip Interface

Stackable memory pin assignment; Stackable

memory physical pinout

TSV

Keep out area, fill materials, dimensions

Thin wafer handling

Technology Development and Cost Reduction

Technology Development and Cost Reduction

Reliability

Criteria; Test methods; ESD

Temporary bond/debond cost reduction

Materials and release mechanisms cost reduction;

Equipment cost reduction

TSV

Keep out distance/area

Microbumping and bonding

Pad metallurgy and layer thickness; Bump

metallurgy

Inspection/metrology

Microbump inspection and coplanarity; TSV voids;

BWP voids

Test

Probing microbumps cost reduction

12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs

High density via-mid applications including interposers, heterogeneous stacking, logic on

logic, memory on memory; 2011-2014 timeframe

Addresses all aspects of via-mid: wafer processing, assembly, reliability,

inspection/metrology, design, test

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Expected Outcome

Survey review

14 companies participated (2 fabless, 4 foundries, 3

IDM-logic, 2 IDM-memory, 3 OSATs)

Landscape survey of key suppliers

References

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