Combinational Controllability Controllability Formulas (Cont.)

1/29/2008

Based on text by S. Mourad "Priciples of Electronic Systems"

Digital Testing:

Testability Measures

Fab. 2, 2001 Copyrights(c) 2001, Samiha Mourad 2

Outline

The case for DFT Testability Measures

Controllability and observability SCOAP measures

• Combinational circuits • Sequential circuits Adhoc techniques Easily testable structures C-testability

What is Design for Test ?

Also called design for testability That is design to facilitate testing No formal definition for testability

Possible definition, testability increases as the cost and time of testing decreases

The Case for DFT

High device density

Large number of gates per pin

• see next chart

High cost of ATPG particularly for sequential circuits

Need for a shorter design & test cycle

• shorter-time-to-market

Complexity: Gates per Pin

800

Testability Analysis

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Determines testability measures

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Involves Circuit Topological analysis, but no test vectors (static analysis) and no search algorithm.

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Linear computational complexity

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Otherwise, is pointless – might as well use automatic test-pattern generation and calculate:

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Exact fault coverage

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Exact test vectors

What are Testability Measures?

Approximate measures of:

Difficulty of setting internal circuit lines to 0 or 1 from primary inputs.

Difficulty of observing internal circuit lines at primary outputs.

Applications:

Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware. Guidance for algorithms computing test patterns – avoid using hard-to-control lines.

SCOAP Measures

ƒ SCOAP – Sandia Controllability and Observability Analysis Program

ƒ Combinational measures:

ƒCC0– Difficulty of setting circuit line to logic 0

ƒCC1– Difficulty of setting circuit line to logic 1

ƒCO – Difficulty of observing a circuit line

ƒ Sequential measures – analogous:

ƒSC0

ƒSC1

ƒSO

ƒ Ref.: L. H. Goldstein, “Controllability/Observability Analysis of Digital Circuits,” IEEE Trans. CAS, vol. CAS-26, no. 9. pp. 685 – 693, Sep. 1979.

Range of SCOAP Measures

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Controllabilities – 1 (easiest) to infinity (hardest)

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Observabilities – 0 (easiest) to infinity (hardest)

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Combinational measures:

Roughly proportional to number of circuit lines that must be set to control or observe given line.

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Sequential measures:

Roughly proportional to number of times flip-flops must be clocked to control or observe given line.

Combinational Controllability

Controllability Formulas (Cont.)

Controllability Formulas (Cont.)

Combinational Observability

Combinational Observability

To observe a gate input: Observe output and make other input values non-controlling.

Observability Formulas (Cont.)

Observability Formulas (Cont.)

Fanout stem: Observe through branch with best observability.

An Example

Z

Y

A

B

C

G1 G2 G3 G4 G5

F

H

G

An Example

Z Y A B C G1 G2 G3 G4 G5 F H G Controllabilities CC1(F)=CC1(A)+CC1(B)+CC1( C)+1=4 CC0(F)=min{CC0(A),CC0(B),CC0( C)}+1=2 CC1(H)=min{CC0(A),CC0(B)}+1=2 CC0(H)=CC1(A)+CC1(B)+1=3 CC1(G)=CC0( C)+1=2 CC0(G)=CC1( C)+1=2 CC1(Y)=min{CC1(F),CC1(H)}+1=3 CC0(Y)=CC0(F)+CC0(H)+1=6 CC1(Z)=min{CC0(H),CC0(G)}+1=3 CC0(Z)=CC1(H)+CC1(G)+1=5

Assume that controllability of all inputs and observability of all outputs is 1 Observabilities COY(F)=CO(Y)+CCO(H)+1=5 COZ(G)=CO(Z)+CC1(H)+1=4 COY(H)=CO(Y)+CCO(F)+1=4 e.t.c.

Comb. Controllability

Circled numbers give level number. (CC0, CC1)

Final Combinational Controllability

Combinational Observability for

Level 1

Number in square box is level from primary outputs (POs). (CC0, CC1) CO

Combinational Observability for

Level 2

Final Combinational Observability

Sequential Measures

ƒ Combinational

ƒIncrement CC0, CC1, COwhenever you pass through

D Flip-Flop Equations

ƒ Assume a synchronous RESET line.

ƒ CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET)

D Flip-Flop Clock and Reset

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CO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C)

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SO (RESET)is analogous

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Three ways to observe the clock line: 1. Set Qto 1 and clock in a 0 from D 2. Set the flip-flop and then reset it 3. Reset the flip-flop and clock in a 1 from D

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CO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C), CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C), CO (Q) + CC0 (Q) + CC0 (RESET) + CC1 (D) + CC1 (C) + CC0 (C)]

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SO (C)is analogous

Testability Computation

1. For all PIs, CC0 = CC1 = 1and SC0 = SC1 = 0 2. For all other nodes, CC0 = CC1 = SC0 = SC1 = ∞ 3. Go from PIs to POs, using CCand SCequations to get

controllabilities Iterate on loops until SC stabilizes --convergence is guaranteed.

4. Set CO = SO = 0 for POs, ∞ for all other lines. 5. Work from POs to PIs, Use CO, SO, and controllabilities

to get observabilities.

6. Fanout stem (CO, SO) = min branch (CO, SO)

7. If a CCor SC(COor SO) is ∞ , that node is uncontrollable (unobservable).

Sequential Example Initialization

After 1 Iteration

Stable Sequential Measures

Final Sequential Observabilities

Testability Measures are Not Exact

Exact computation of measures is NP-Complete and impractical

Blue(Italicized) measures show correct (exact) values – SCOAP measures are in orange--CC0,CC1 (CO)

1,1(6) 1,1(5,∞) 1,1(5) 1,1(4,6) 1,1(6) 1,1(5,∞) 6,2(0) 4,2(0) 2,3(4) 2,3(4,∞) (5) (4,6) (6) (6) 2,3(4) 2,3(4,∞)

Summary

Summary

Testability measures are approximate measures

of:

Difficulty of setting circuit lines to 0 or 1 Difficulty of observing internal circuit lines

Applications:

Analysis of difficulty of testing internal circuit parts • Redesign circuit hardware or add special test

hardware where measures show poor controllability or observability.

Guidance for algorithms computing test patterns – avoid using hard-to-control lines

Exercise

Compute (CC0, CC1) CO for all lines in the following circuit.

Test Points

OP

Observation Points

Z Y (b) A B C G1 G2 F H G3 G4 G5 OP G G1 faults are masked due

to circuit redundancy but they are testable if OP observation point is added

CAD Tools

All aspect of ASIC design and test depends on CAD tools

CAD programs perform different tasks:

Design entry, Simulation, Synthesis, layout, Test pattern generation, Fault grading, Floor planning, Technology mapping, Place and route, DRC, LVS, Parameter extraction

Most these problems are NP-complete There is a need for algorithms that utilize

some heuristic and a cost function to stop the computation.

Logic and Physical Design

Specs Behavioral HDL Simulation Static Timing Analysis Electrical Rule Checker Logic Simulation Synthesis Models Netlist ATPG Fault Grading P&R Models Back-annotation Mask _Models