COA Unit-1 Final

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Unit I

COMPUTER ARCHITECTURE

AND

ORGANIZATION

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Unit 1: Register Transfer And

Unit 1: Register Transfer And Micro Operations:

Micro Operations:



 Register Transfer Language,Register Transfer Language,



 Register transferRegister transfer



 Bus and Memory transfer,Bus and Memory transfer,



 Arithmetic Micro-operations,Arithmetic Micro-operations,



 Logic Logic Micro-operationsMicro-operations,,



 Shift Shift Micro-operationsMicro-operations,,



 Arithmetic Logic Shift Unit.Arithmetic Logic Shift Unit.



 Computer Organization:Computer Organization:

Computer Organization is concerned with the way the hardware

components operate and the way they are connected together to form

the computer system.



 Computer Architecture:Computer Architecture:

Computer architecture is concerned with the structure and

behavior of the computer as seen by the user.

behavior of the computer as seen by the user. It includes the information

It includes the information

format, instruction set, and technique for addressing memory. The

architecture design of a computer system is concern with the

specification of the various function modules, such as processors and

memories, and structuring them together into a

memories, and structuring them together into a computer system

computer system

..



 RegisterRegister 



A register is a group of flip-flop with each flip-flop capable of storing

one bit of

one bit of informatio

information.

n.



An n-bit register has a group of n flip-flops & is capable of storing any

binary information of n-bits.



In addition to the flip flops, a register may have combinational gates

that perform certain data processing tasks.



“Register consists of group of flip

“Register consists of group of flip-flops and gates that effect their

-flops and gates that effect their

transition.

The flip-flops hold the binary information and gates control

when and how new information is transferred into register.”



The individual flip-flops in an n-bit register are numbered in

sequence from 0 through n-1, starting from 0 in the rightmost

position & increasing the numbers towards the left.

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 Register Transfer LanguageRegister Transfer Language 



A digital system is an interconnection of digital hardware modules

that accomplish specific information-processing task.



Digital systems are built from modules that are built from

components such as registers, decoders, arithmetic elements and

control logic. Those modules are connected with control and data

paths.



Digital modules are best defined by registers they contain and

operations they perform on stored data.



Micro operations: the operations executed on data stored in

Micro operations: the operations executed on data stored in registers.

registers.

An elementary operation performed in information stored in

register(s). Examples of micro operations: shift, count, clear,

increment, and load



But also it is interesting to know that the internal hardware

organization of a digital computer is

organization of a digital computer is best defined by:

best defined by:



Registers it contains and their functions



Sequence of micro operations performed on data inside

registers



Control that ignites the sequence of micro

Control that ignites the sequence of micro operations

operations



It is time now to agree on a terminology to describe the sequence of

transfer between registers and arithmetic and logical operations

associated with those transfers.



 RTL (Register transfer language):RTL (Register transfer language): is symbolic notations used to is symbolic notations used to describe micro operation transfer among registers. RTL is a system for describe micro operation transfer among registers. RTL is a system for expressing in symbolic

expressing in symbolic form the micro operation sequences amongform the micro operation sequences among registers in a digital module.

registers in a digital module.



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4 4

Designation of Registers:



Registers are designated by capital letters; sometimes followed by

numbers to denote the function of a register. Examples will as:

o

MAR for Memory Address

MAR for Memory Address Register

Register

o

PC for Program Counter

o

IR for Instruction register

o

R1 for processor register



The individual flip flops in n-bit register is numbered from 0 in right

most to n-1 in left most



A register can be viewed as a single entity or may also be represented

showing the bits of data they contain. Registers can be designated by

a whole register, portion of a register, or a bit of a register. Registers

and their contents can be viewed and represented in various ways

such as shown in next figure:

Register transfer:

Register Transfer is defined as copying/transfer the content

of one register to another. For register transfers, the data transfer

from one register to another is designated in symbolic form by

replacement operator

R2



R1

Please note that:

o

In this case the contents of register R2 are copied (loaded) into

register R1

o

A simultaneous transfer of all bits from the source R1 to the

destination register R2, during one

destination register R2, during one clock pulse

clock pulse

o

Note that this is a non-destructive; i.e. the contents of R1 are not

altered by copying (loading) them to R2

That register transfer also implies that:

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g g e e 5 5 o

o

The data lines extend from the source register (R1) to the

destination register (R2) with lines equal the bit numbers of R1

and R2.

o

Parallel load occurs in

Parallel load occurs in the destination register (R2)

the destination register (R2)

o

Control lines are needed to

Control lines are needed to perform this action

perform this action

Control Function:

We need the transfer to happen under a certain condition by

means which looks if-then statement. In digital systems, this is

often done via a control signal, called a control function. If the

signal is “1” then a

signal is “1” then action will take place. See next example for

ction will take place. See next example for

control statement P. P also could be a combination of Boolean

variables which yields a single Boolean output.

P: R2



R1

Which means “if P = 1, then load the contents of register R1

into register R2”,

i.e., if (P =

i.e., if (P = 1) then (R2

1) then (R2



R1).

Hardware Implementation for control function:



Look at next diagram which shows R1 transfer to R2. You will

realize that the n outputs of register R1is connected to n input of

register R2. Register R2 has a load control activated by P control

function and the whole operation is synchronized with the central

clock. The rising edge of the CLK input triggers activates P at t time

and at t+1 time the transfer takes place.

Block Diagram Block Diagram

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6 6

Timing Diagram Timing Diagram

Also we assume that here the registers are comprised of DFF

that acts on rising edge clocks.

Simultaneous Operations:



If cases where two or more operations are

If cases where

two or more operations are to occur simultaneously,

to occur simultaneously,

they are separated with commas

they are separated with commas as shown next:

as shown next:

P: R3



R5, MAR



IR

Here, if the control function P = 1,

Here, if the control function P = 1, load the contents of R5 into

load the contents of R5 into

R3, and at the same time (clock), load the contents of register IR

into register MAR

The basic symbols for register transfer is shown in next table and that

summarizes the topic:

Symbol

Symbol Description Description ExampleExample Alphanumeric

Alphanumeric Register Names Register Names MAR, MAR, R2,AR2,A Subscript

Subscript Bit Bit positions positions in in registers registers AA33, B, B77

Parentheses(

Parentheses( ) ) Portion/Part Portion/Part of of Registers Registers MBR(8-15),MBR(8-15), R2(L)

R2(L) Left Arrow

Left Arrow  Transfer/Copying Transfer/Copying of of info. info. AA B B Colon

Colon : : Separates Separates controlcontrol

function from expression function from expression

P: A P: A B B Comma

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 Bus and Memory TransferBus and Memory Transfer



 There is a problem if we need to move data from and to multiple registers.There is a problem if we need to move data from and to multiple registers. The number of wires will be so large if separate lines are used to connect The number of wires will be so large if separate lines are used to connect all registers with each other.

all registers with each other.



 To completely connect n registers we need n(n-1) lines. So the cost is inTo completely connect n registers we need n(n-1) lines. So the cost is in order of O(n2). This is not a realistic approach to be used in a large digital order of O(n2). This is not a realistic approach to be used in a large digital system. The solution is to use a

system. The solution is to use a commoncommon “Bus”.“Bus”.



 Instead, take a different approach; have one centralized set of circuits forInstead, take a different approach; have one centralized set of circuits for data transfer the

data transfer the “bus“bus_{”. Also have control circuits to select which register is}_{”. Also have control circuits to select which register is}

the source, and which is the

the source, and which is the destination.destination.



 Definition of a bus: Bus is a path (of a group of wires) over whichDefinition of a bus: Bus is a path (of a group of wires) over which information is transferred, from any of several sources to any of several information is transferred, from any of several sources to any of several destinations.

destinations.



 One way of constructing a bus is by using multiplexers. The next diagramOne way of constructing a bus is by using multiplexers. The next diagram shows how this works. The next figure shows how to implement data shows how this works. The next figure shows how to implement data transfer from register to the bus.

transfer from register to the bus. BUS

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

 In general, the bus system will multiplex k registers of n bits each toIn general, the bus system will multiplex k registers of n bits each to produce an n-line common bus.

produce an n-line common bus.

o

o The number of multiplexers need is nThe number of multiplexers need is n o

o The size of each multiplexer is k X 1The size of each multiplexer is k X 1

S1

S1 S0 S0 Register Register SelectedSelected

0 0 A 0 0 A 0 1 B 0 1 B 1 0 C 1 0 C 1 1 D 1 1 D Functional Table Functional Table 

 Three state table buffersThree state table buffers

Another way of constructing a bus is by using buffers or 3-state gates. The Another way of constructing a bus is by using buffers or 3-state gates. The next two figures show the buffers in use for constructing a bus system.

next two figures show the buffers in use for constructing a bus system.



 The first one shows the graphical symbol for 3-state bufferThe first one shows the graphical symbol for 3-state buffer

While the next one shows bus system using 4 by one selectors of buffers. While the next one shows bus system using 4 by one selectors of buffers. 

 _{A bus system can be constructed with three state gates instead of}_{A bus system can be constructed with three state gates instead of} multiplexers.

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 _{A three states gate is digital circuit that exhibits three states.}_{A three states gate}_{is digital circuit that exhibits three states.} 

 _{Two of the states are signals equivalent to logic 1 and 0 as in a}_{Two of the states are signals equivalent to logic 1 and 0 as in a} conventional gate. The third state is a

conventional gate. The third state is a high-impedance state.high-impedance state. 

 _{The high-impedance state behaves like an open circuit, which means}_{The high-impedance state behaves like an open circuit, which means} that the output is disconnected and does not have a logic, such as AND that the output is disconnected and does not have a logic, such as AND or NAND. However the one most commonly used in the design of a bus or NAND. However the one most commonly used in the design of a bus system is the buffer gate.

system is the buffer gate.



 Bus Transfer in RTL:Bus Transfer in RTL:

The transfer of information from a bus into one of many destination The transfer of information from a bus into one of many destination registers can be accomplished by connecting bus lines to the inputs of all registers can be accomplished by connecting bus lines to the inputs of all registers and activating load control of selected destination. The symbolic registers and activating load control of selected destination. The symbolic statement for a bus transfer may mention the bus or may be implied in the statement for a bus transfer may mention the bus or may be implied in the statement. statement. R2 R2  R1R1 OR OR BUS

BUS  R1, R2R1, R2  BUSBUS



 Memory Transfer:Memory Transfer:

Memory (RAM) can be thought as a sequential circuits containing Memory (RAM) can be thought as a sequential circuits containing some number of registers. These registers hold the words of memory. Each some number of registers. These registers hold the words of memory. Each of the r registers is indicated by an address. These addresses range from 0 of the r registers is indicated by an address. These addresses range from 0 to r-1. Each register (word) can hold n bits of data. Now assume the RAM to r-1. Each register (word) can hold n bits of data. Now assume the RAM contains r = 2k words. It needs the following

contains r = 2k words. It needs the following

o

o n data input linesn data input lines o

o data output linesdata output lines o

o k address linesk address lines o

o A Read control lineA Read control line o

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1 1 0 0



 The memory can be viewed at the register level as a device, M. And since itThe memory can be viewed at the register level as a device, M. And since it contains multiple locations, then we must specify which address in contains multiple locations, then we must specify which address in memory we will be using.

memory we will be using.



 This is done by indexing memory references. Memory is usually accessedThis is done by indexing memory references. Memory is usually accessed in computer systems by putting the desired address in a special register, in computer systems by putting the desired address in a special register, the Memory Address Register (MAR, or AR). And when memory is the Memory Address Register (MAR, or AR). And when memory is accessed, the contents of the MAR get sent to the memory unit’s address accessed, the contents of the MAR get sent to the memory unit’s address lines.

lines.



 For Read Operation: when address of required location is transferred intoFor Read Operation: when address of required location is transferred into address register AR then the content is loaded into data register DR.

address register AR then the content is loaded into data register DR. DR

DR  M [AR]M [AR]



 For Write operation:For Write operation: the content of data register DR is transferred into the content of data register DR is transferred into memory location addressed by address register AR.

memory location addressed by address register AR. M [AR]

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 micro operationmicro operation



 The operations executed on data stored in registers are calledThe operations executed on data stored in registers are called micro- micro-operations.

operations.



 A micro operation is an elementary operation performed with data storedA micro operation is an elementary operation performed with data stored in register. They are classified into:

in register. They are classified into:

o

o Register transfer micro operationsRegister transfer micro operations: Transfer binary information: Transfer binary information

from one register to another. from one register to another.

o

o Arithmetic micro operatio Arithmetic micro operation:n: Perform arithmetic operations onPerform arithmetic operations on

numeric data stored in registers. numeric data stored in registers.

o

o Logic micro operation:Logic micro operation: Perform bit manipulation operations onPerform bit manipulation operations on

non-numeric data stored in

non-numeric data stored in registers.registers.

o

o Shift micro operation Shift micro operation: Perform shift operation on data stored in: Perform shift operation on data stored in

registers. registers.



 Arithmetic Micro operationArithmetic Micro operation



 Basic arithmetic micro operations are:Basic arithmetic micro operations are:

o o AdditionAddition o o SubtractionSubtraction o o IncrementIncrement o o DecrementDecrement o

o Arithmetic ShiftArithmetic Shift



 Short look on different arithmetic micro operations:Short look on different arithmetic micro operations:

o

o The Add micro operation is The Add micro operation is specified as:specified as:

R3

R3  R1 + R2.R1 + R2.

And it means add content of R1 to R2 and store result of addition in R3. And it means add content of R1 to R2 and store result of addition in R3. Usually it is implemented using hardware full

Usually it is implemented using hardware full adders.adders.

o

o The Subtraction is usually implemented using complementation andThe Subtraction is usually implemented using complementation and

addition addition

R3

R3  R1 + R2 +1R1 + R2 +1

And it means subtract R2 from R1 by adding the complement of And it means subtract R2 from R1 by adding the complement of R2 plus 1 to R1. Usually it is implemented using a full adder a R2 plus 1 to R1. Usually it is implemented using a full adder a complement circuit.

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1 1 2 2

R2

R2 is the symbol for the 1’s complement of R2. Adding 1 to the 1’sis the symbol for the 1’s complement of R2. Adding 1 to the 1’s complement produces the 2’s complement. Adding the contents of

complement produces the 2’s complement. Adding the contents of R1 toR1 to the 2’s complement of R2 is equivalent to R1 –

the 2’s complement of R2 is equivalent to R1 – R2. R2.



 The increment and decrement micro-operations are symbolized by plusThe increment and decrement micro-operations are symbolized by plus one and minus-one operation, respectively. These Increment and one and minus-one operation, respectively. These Increment and decrement micro-operations are implemented with

decrement micro-operations are implemented with a combinational circuita combinational circuit or with a binary Up and Down Counter.

or with a binary Up and Down Counter.



 In most computers, multiplication operation is implemented with aIn most computers, multiplication operation is implemented with a sequence of add &

sequence of add & shift micro operations and division is implemented withshift micro operations and division is implemented with sequence of subtract &

sequence of subtract & shift micro-operation.shift micro-operation.



 Binary Adder:Binary Adder: 

 _{To implement binary adder we need registers that holds data and a full}_{To implement binary adder we need registers that holds data and a full} adder that performs arithmetic operation between 2 bits and previous adder that performs arithmetic operation between 2 bits and previous carry.

carry. 

 _{The digital circuit that forms the arithmetic sum of two bits and a}_{The digital circuit that forms the arithmetic sum of two bits and a} previous carry is called a

previous carry is called a full-adder full-adder .. 

 _{The digital circuit that generates the arithmetic sum of two binary}_{The digital circuit that generates the arithmetic sum of two binary} numbers of any lengths is called a

numbers of any lengths is called a binary adder binary adder .. 

 _{Binary adders are constructed from full}_{Binary adders are constructed from full adders connected in cascade.}_{adders connected in cascade.} 

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 _{The interconnections of four full-adders (FA) to provide a 4-bit binary}_{The interconnections of four full-adders (FA) to provide a 4-bit binary} adder.

adder. 

 _{The augend bits of A and the}_{The augend bits of A and the addend bits of B are designated by}_{addend bits of B are designated by}

subscript numbers from right to left, with subscript 0 to n-1. The carries subscript numbers from right to left, with subscript 0 to n-1. The carries are connected in a chain through the full adders.

are connected in a chain through the full adders. 

 _{The input carry to the binary adders C}_{The input carry to the binary adders C}₀₀_{and the output carry is C}_{and the output carry is C}₄₄_.. 

 _{The S outputs of the full-adders generate the required sum bits.}_{The S outputs of the full-adders generate the required sum bits.} 

 _{The output carry from each full-adder is connected to the input carry of}_{The output carry from each full-adder is connected to the input carry of} the next-high-order full-adder.

the next-high-order full-adder. 

 _{The n data bits for the A}_{The n data bits for the A inputs come from one register (such as R1),}_{inputs come from one register (such as R1),} and the n data bits for the

and the n data bits for the B inputs come from another register (such asB inputs come from another register (such as R2). The sum can be transferred to a third register or to one of th

R2). The sum can be transferred to a third register or to one of thee source registers (R1 or R2), replacing its previous content.

source registers (R1 or R2), replacing its previous content.



 Binary Binary Adder-Subtractor:Adder-Subtractor: 

 _{Subtraction of A –}_{Subtraction of A} _{– B can be done by taking 2’s complement of B and}_{B can be done by taking 2’s complement of B and} added to A. The 2’s complement can be done by taking 1’s complement added to A. The 2’s complement can be done by taking 1’s complement then adding “1” to the result. And finally the 1’s complement is the then adding “1” to the result. And finally the 1’s complement is the binary inversion.

binary inversion. 

 _{The addition and subtraction operations can be combined into one}_{The addition and subtraction operations can be combined into one} common circuit by including Ex-OR with

common circuit by including Ex-OR with each full adder.each full adder. 

 _{By looking at next drawing you will notice that input mode M control}_{By looking at next drawing you will notice that input mode M control} addition or subtraction operations.

addition or subtraction operations.

o

o If M=0 then circuit is an Adder andIf M=0 then circuit is an Adder and o

o If M=1 then circuit is a Subtractor (can you observe why??).If M=1 then circuit is a Subtractor (can you observe why??).



 _{Each exclusive-OR gate receives input M and one of the inputs of B.}_{Each exclusive-OR gate receives input M and one of the inputs of B.} 

 _{When M=0, we have B Ex-OR 0}_{When M=0, we have B Ex-OR 0 = B}_{= B}

o

o The full-adders receive the value of B, the input carry is 0, andThe full-adders receive the value of B, the input carry is 0, and o

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1 1 4 4

When M=1, we have B

Ex-When M=1, we have B Ex-OR 1 =B’ and COR 1 =B’ and C00=1=1

o

o The B inputs are all complemented and 1 is added through theThe B inputs are all complemented and 1 is added through the

input carry, and input carry, and

o

o The circuit performs the operation A plus the 2’s The circuit performs the operation A plus the 2’s complement ofcomplement of

B. B.



 Binary Incrementor:Binary Incrementor: 

 _{The binary incrementor is defined as it always adds one to the number}_{The binary incrementor is defined as it always adds one to the number} in a register. For example, if a 4-bit register has a binary value 0110, it in a register. For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is incremented.

will go to 0111 after it is incremented. 

 _{The incrementor can be implemented in one way by a counter. When}_{The incrementor can be implemented in one way by a counter. When} clock transition arrives the count is incremented. But in another way clock transition arrives the count is incremented. But in another way the incrementor can be done using half adders.

the incrementor can be done using half adders. Hardware Implementation:

Hardware Implementation: 

 _{The next drawing shows in hardware an incrementor of 4 bits. It can be}_{The next drawing shows in hardware an incrementor of 4 bits. It can be} extended to n bits easily including n half adders.

extended to n bits easily including n half adders. 

 _{One of the inputs to the least significant half adder (HA) is connected to}_{One of the inputs to the least significant half adder (HA) is connected to} logic-1 and the input is connected to the least significant bit of the logic-1 and the input is connected to the least significant bit of the number to be incremented. The output carry from one half-adder is number to be incremented. The output carry from one half-adder is connected to one of the inputs of the inputs of the next-higher-order connected to one of the inputs of the inputs of the next-higher-order half adder.

half adder. 

 _{The circuit receives four bits from A}_{The circuit receives four bits from A}₀₀_{to A}_{to A}₃₃_{, adds one to it, and generates}_{, adds one to it, and generates} the incremented output in S

the incremented output in S00 through S through S33. The output carry C. The output carry C44 will be 1 will be 1

only after incrementing binary 1111.

only after incrementing binary 1111. This also causes output SThis also causes output S00 through through

S

S33 to go to 0. to go to 0.



 Arithmetic Circuit Arithmetic Circuit 

 _{The arithmetic micro operations listed in table 4-4 can be implemented}_{The arithmetic micro operations listed in table 4-4 can be implemented} in one composite arithmetic circuit. This circuit comprised of full in one composite arithmetic circuit. This circuit comprised of full adders and multiplexers.

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 _{The multiplexer controls which data is fed into Y input of the adder.}_{The multiplexer controls which data is fed into Y input of the adder.} 

 _{The diagram of a 4-bit arithmetic circuit is shown in following diagram.}_{The diagram of a 4}_{-bit arithmetic circuit is shown in following diagram.} 

 _{It has four full adder circuits that constitute the 4-bit adder and four}_{It has four full adder circuits that constitute the 4-bit adder and four} multiplexers for choosing different operations.

multiplexers for choosing different operations. 

 _{There are two 4-bit inputs A and B}_{There are two 4-bit inputs A and B and a 4-bits output D.}_{and a 4-bits output D.}

The output of the

The output of the binary adder is computed frombinary adder is computed from D = A + Y +Cin

D = A + Y +Cin



 The Y input can have one of 4 different values: B, B’, always “1”, or alwaysThe Y input can have one of 4 different values: B, B’, always “1”, or always “0”. The next table shows how this can

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1 1 6 6



 Logic Logic Micro-operaMicro-operationstions



 Logic micro operation specifies binary operations on the strings of bits inLogic micro operation specifies binary operations on the strings of bits in registers. Logic micro operations are bit-wise operations, i.e.,

registers. Logic micro operations are bit-wise operations, i.e., they work onthey work on the individual bits of data.

the individual bits of data.



 Those could be useful for bit manipulations on binary data and also usefulThose could be useful for bit manipulations on binary data and also useful for making logical decisions based on the bit value. There are, in principle, for making logical decisions based on the bit value. There are, in principle, 16 different logic functions that can be defined over two binary input 16 different logic functions that can be defined over two binary input variables. However, most systems only implement four of these:

variables. However, most systems only implement four of these:



 AND ( ), AND ( ), OR OR ( ( ), ), XOR XOR ( ( ), ), Complement/NOTComplement/NOT



 The others can be created from combination of these. List of LogicThe others can be created from combination of these. List of Logic Microoperations-16 different logic operations with 2 binary variables are Microoperations-16 different logic operations with 2 binary variables are shown next.

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 The hardware implementation of logic micro operation requires theThe hardware implementation of logic micro operation requires the insertion of the most important gates like AND, OR, EXOR, and NOT for insertion of the most important gates like AND, OR, EXOR, and NOT for each bit or pair of bits in the registers.

each bit or pair of bits in the registers.

Hardware Implementation: Hardware Implementation:



 The next figure shows one stage of a circuit that generates the four basic logicThe next figure shows one stage of a circuit that generates the four basic logic micro operations. It consists of four gates and a multiplexer. The two selection micro operations. It consists of four gates and a multiplexer. The two selection lines of the multiplexer selects one of the four logic operations available at one lines of the multiplexer selects one of the four logic operations available at one time. The circuit shows one stage for bit “i” but for logic circuit of n bits the time. The circuit shows one stage for bit “i” but for logic circuit of n bits the circuit should be repeated n times but with one remark; the selection pins will circuit should be repeated n times but with one remark; the selection pins will be shared with all stages.

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Applications Of Logic Micro oper

Applications Of Logic Micro operationsations



 Logic micro operations can be used to Logic micro operations can be used to manipulate individual bits or amanipulate individual bits or a portions of a word in a register

portions of a word in a register



 Consider the data in a register A. In another register, B, is bit data thatConsider the data in a register A. In another register, B, is bit data that will be used to modify the contents of A

will be used to modify the contents of A

Selective-set A

Selective-set A _{A + B}_{A + B} Selective-complement A

Selective-complement A _A_A _B_B Selective-clear A

Selective-clear A  _{A • B’}_{A • B’} Mask

Mask (Delete) (Delete) AA  _{A • B}_{A • B}

Clear A

Clear A _A_A _B_B

Insert A

Insert A  _{(A • B) + C}_{(A • B) + C}

Compare A

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g g e e 1 1 9 9 o o Selective-setSelective-set

 In a selective set operation, the bit pattern in B is used toIn a selective set operation, the bit pattern in B is used to set set certain bits in A certain bits in A 1 1 1 1 0 0 0 0 AAt t 1 1 0 0 1 1 0 0 BB 1 1 1 1 1 1 0 0 AAt+1t+1 (A(A  A + B) A + B)

 If a bit in B If a bit in B is set to 1, that same position in A gets set to 1,is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps its previous value

otherwise that bit in A keeps its previous value

o

o Selective-complementSelective-complement

 In a selective complement operation, the bit pattern in B isIn a selective complement operation, the bit pattern in B is used to

used to complement complement certain bits in A certain bits in A 1 1 1 1 0 0 0 0 AAt t 1 1 0 0 1 1 0 0 BB 0 0 1 1 1 1 0 0 AAt+1t+1 (A(A  A A  B) B)

 If a bit in B If a bit in B is set to 1, that same position in A getsis set to 1, that same position in A gets complemented from its original value, otherwise it is complemented from its original value, otherwise it is unchanged

unchanged

o

o Selective-clearSelective-clear

 In a selective clear operation, the bit pattern in B is used toIn a selective clear operation, the bit pattern in B is used to clear

clear certain bits in A certain bits in A 1 1 1 1 0 0 0 0 AAt t 1 1 0 0 1 1 0 0 BB 0 0 1 1 0 0 0 0 AAt+1t+1 (A(A  A A B’)B’)

 If a bit in B If a bit in B is set to 1, that same position in A gets set to 0,is set to 1, that same position in A gets set to 0, otherwise it is unchanged

otherwise it is unchanged

o

o Mask (Delete)Mask (Delete)

 In a mask operation, the bit pattern in B is used toIn a mask operation, the bit pattern in B is used to clear clear certain bits in A certain bits in A 1 1 1 1 0 0 0 0 AAt t 1 1 0 0 1 1 0 0 BB 1 1 0 0 0 0 0 0 AAt+1t+1 (A(A  A A  B) B)

 If a bit in B If a bit in B is set to 0, that same position in A gets set to 0,is set to 0, that same position in A gets set to 0, otherwise it is unchanged

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2 2 0 0 Clear Clear A A A A BB

 In a clear operation, if the bits in the same position in A andIn a clear operation, if the bits in the same position in A and B are the same, they are cleared in A,

B are the same, they are cleared in A, otherwise they are setotherwise they are set in A in A 1 1 1 1 0 0 0 0 AAt t 1 1 0 0 1 1 0 0 BB 0 0 1 1 1 1 0 0 AAt+1t+1 (A(A  A A  B) B) o o Insert Insert AA (A • B) + C(A • B) + C

 An insert operation is used to introduce a specific bitAn insert operation is used to introduce a specific bit pattern into A

pattern into A register, leaving the other bit positionsregister, leaving the other bit positions unchanged

unchanged

 This is done asThis is done as 

 _{A mask operation to clear}_{A mask operation to clear the desired bit positions,}_{the desired bit positions,} followed by

followed by 

 _{An OR operation to introduce the new bits into the}_{An OR operation to introduce the new bits into the} desired positions

desired positions 

 _Example_Example

o

o Suppose you wanted to introduce 1010 into Suppose you wanted to introduce 1010 into thethe

low order four bits of A: low order four bits of A: 1101 1101 1000 1000 1011 1011 0001 0001 A A (Original)(Original) 1101 1101 1000 1000 1011 1011 1010 1010 A A (Desired)(Desired) 1101 1101 1000 1000 1011 1011 0001 0001 A (Original)A (Original) 1111 1111 1111 1111 1111 1111 0000 0000 MaskMask 1101 1101 1000 1000 1011 1011 0000 0000 A (Intermediate)A (Intermediate) 0000

0000 0000 0000 0000 0000 1010 1010 Added bitsAdded bits 1101

1101 1000 1000 1011 1011 1010 1010 A (Desired)A (Desired)



 Shift Shift Micro-operMicro-operationsations



 Shift micro-operations are used for serial transfer of data beside they areShift micro-operations are used for serial transfer of data beside they are used in conjunction with arithmetic, logic, and other data processing used in conjunction with arithmetic, logic, and other data processing operations.

operations.



 There are 3 types of shift micro operations. What differentiates them is theThere are 3 types of shift micro operations. What differentiates them is the information that goes into the serial input:

information that goes into the serial input:

o

o Logical shiftLogical shift o

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g g e e 2 2 1 1 

 Logical Shift:Logical Shift: 

 _{Logical shift is one that transfers 0}_{Logical shift is one that transfers 0 through the serial input. In a}_{through the serial input. In a} Register Transfer Language, the following notation is used

Register Transfer Language, the following notation is used

o

o shl for a logical shift leftshl for a logical shift left o

o shr for a logical shift rightshr for a logical shift right



_{A right logical shift operation}_{A right logical shift operation}



_{A left logical shift operation:}_{A left logical shift operation:}

  _Examples:_Examples: R2 R2  shr R2shr R2 R3 R3  shl R3shl R3

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2 2 2 2



 Circular Shift:Circular Shift: 

 _{The circular shift rotates of the}_{The circular shift rotates of the register around the two ends w}_{register around the two ends without}_ithout loss of information. This is accomplished by connecting the two ends loss of information. This is accomplished by connecting the two ends ofof the shift register to each other. t

the shift register to each other. the following notation is usedhe following notation is used

o

o cil for a circular shift leftcil for a circular shift left o

o cir for a circular shift rightcir for a circular shift right



 _{A right circular shift operation:}_{A right circular shift operation:}



 _{A left circular shift operation:}_{A left circular shift operation:}

  _Examples:_Examples: R2 R2 cir R2cir R2 R3 R3 cil R3cil R3 

 Arithmetic Shift: Arithmetic Shift: 

 _{Arithmetic shift is a micro-operation that shifts a signed binary number}_{Arithmetic shift is a micro-operation that shifts a signed binary number} to the left

to the left or right. Arithmetic shift must leave sign bit unchanged.or right. Arithmetic shift must leave sign bit unchanged. 

 _{An arithmetic shift is meant for}_{An arithmetic shift is meant for signed binary numbers (integer)}_{signed binary numbers (integer)} 

 _{An arithmetic left shift multiplies a signed number by two}_{An arithmetic left shift multiplies a signed number by two} 

 _{An arithmetic right shift divides a signed number}_{An arithmetic right shift divides a signed number by two}_{by two} 

 _{The main distinction of an arithmetic shift is that it must keep the sign}_{The main distinction of an arithmetic shift is that it must keep the sign} of the number the

of the number the same as it performs the multiplication or divisionsame as it performs the multiplication or division 

 _{Note that the arithmetic shift right is considered divide by 2 and left}_{Note that the arithmetic shift right is considered divide by 2 and left} shift is considered multiply by 2.

shift is considered multiply by 2. 

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g g e e 2 2 3 3 

 _{A left arithmetic shift operation:}_{A left arithmetic shift operation:}



 _{Arithmetic shifts must leave the sign bit unchanged just to preserve the}_{Arithmetic shifts must leave the sign bit unchanged just to preserve the} sign of the resulted number. If that case happened then it will be an sign of the resulted number. If that case happened then it will be an overflow.

overflow.



_{An left arithmetic shift operation mus}_{An left arithmetic shift operation must be checked for the overflow}_{t be checked for the overflow}



 _{An overflow flip flop will be used to detect arithmetic shift left overflow}_{An overflow flip flop will be used to detect arithmetic shift left overflow} as shown in next figure.

as shown in next figure.



 _{In a RTL,}_{In a RTL, the following notation is used for arithmetic shifts:}_{the following notation is used for arithmetic shifts:}

o

o ashl for an ashl for an arithmetic shift leftarithmetic shift left o

o ashr for an ashr for an arithmetic shift rightarithmetic shift right

  _Examples:_Examples: o o R2R2  ashr R2ashr R2 o o R3R3  ashl R3ashl R3

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2 2 4 4



 Hardware Implementation:Hardware Implementation: 

 _{One possible for a shift unit}_{One possible for a shift unit would be bidirectional shift register with parallel}_{would be bidirectional shift register with parallel} load as shown in chapter 2. But another solution can be constructed from load as shown in chapter 2. But another solution can be constructed from multiplexers as shown in next figure.

multiplexers as shown in next figure.

The figure shows 4 2 by 1 multiplexers with 4 input lines A0 to A3 and 4 The figure shows 4 2 by 1 multiplexers with 4 input lines A0 to A3 and 4 output lines H0 to H3. The upper (left) multiplexer can take its inputs from output lines H0 to H3. The upper (left) multiplexer can take its inputs from serial in (IR) or A0. The last multiplexer (bottom or right) can take its inputs serial in (IR) or A0. The last multiplexer (bottom or right) can take its inputs from A3 or serial input (IL). the single line select will select for shift right or from A3 or serial input (IL). the single line select will select for shift right or left operations.

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g g e e 2 2 5 5 

 Arithmetic Logic Shift UnitArithmetic Logic Shift Unit



 Instead of having individual registers performing micro-operationsInstead of having individual registers performing micro-operations directly, computer systems employ a number of storage registers directly, computer systems employ a number of storage registers connected to a unit called Arithmetic Logic Unit (ALU). This unit has 2 connected to a unit called Arithmetic Logic Unit (ALU). This unit has 2 operands input ports and one output port and a number of select lines to operands input ports and one output port and a number of select lines to help in selecting different operations.

help in selecting different operations.



 The ALU is made of combinational circuit so that the entire registerThe ALU is made of combinational circuit so that the entire register transfer operation from the sources to the destination is performed in one transfer operation from the sources to the destination is performed in one clock cycle.

clock cycle.



 The arithmetic, logic, and shift circuits known previously will be combinedThe arithmetic, logic, and shift circuits known previously will be combined in one ALU with common selection inputs. One stage (bit) of ALSU with its in one ALU with common selection inputs. One stage (bit) of ALSU with its table is shown in next two figures.

table is shown in next two figures.



 As shown the arithmetic and logic units will select their operationsAs shown the arithmetic and logic units will select their operations simultaneously when S0 and S1 are applied; while S2 and S3 will select simultaneously when S0 and S1 are applied; while S2 and S3 will select one of those unit outputs or a shift left bit stage or shift right bit stage.

one of those unit outputs or a shift left bit stage or shift right bit stage.



 Note that one stage arithmetic circuit used here is implemented fromNote that one stage arithmetic circuit used here is implemented from figure 4.9 and the one

figure 4.9 and the one stage logic circuit is implemented from figure 4.10.stage logic circuit is implemented from figure 4.10.



 The circuit shown provides 8 arithmetic operations, 4 logic operations, andThe circuit shown provides 8 arithmetic operations, 4 logic operations, and 2 shift operations.

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2 2 6 6

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g g e e 2 2 7 7 1)

1) Show the block diagram of the hardware that implements the following registerShow the block diagram of the hardware that implements the following register transfer statement:

transfer statement: yT2: R2

yT2: R2 ←← R1, R1 R1, R1 ←← R2 R2

Explain why this can be done in the same clock cycle without using a temp register? Explain why this can be done in the same clock cycle without using a temp register?

Note: This can be done in the same clock cycle without using a temp register because the Note: This can be done in the same clock cycle without using a temp register because the registers are edge-triggered flip flop; at the same time the outputs are already on different registers are edge-triggered flip flop; at the same time the outputs are already on different buses to be the new input for the other register.

buses to be the new input for the other register. 2)

2) The outputs of four registers R0, R1, R2 and R3, are connected through 4-to-1-lineThe outputs of four registers R0, R1, R2 and R3, are connected through 4-to-1-line multiplexers to the inputs of a fifth register R5, each register is 8 bits long. The multiplexers to the inputs of a fifth register R5, each register is 8 bits long. The required transfers are dictated by

required transfers are dictated by four timing variables T0 through T3 as four timing variables T0 through T3 as follows:follows: T0: R5 T0: R5←←R0R0 T1: R5 T1: R5←←R1R1 T2: R5 T2: R5←←R2R2 T3: R5 T3: R5←←R3R3

The timing variables are mutually exclusive, which means that only one variable is The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5.

the multiplexers and to the load input of register R5.

The truth table for the outputs: The truth table for the outputs:

PROBLEMS PROBLEMS

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2 2 8 8 T0 T1 T2 T3 S1 S0 Load T0 T1 T2 T3 S1 S0 Load 0 0 0 0 0 0 0 0 X X X X 00 1 1 0 0 0 0 0 0 0 0 0 0 11 0 0 1 1 0 0 0 0 0 0 1 1 11 0 0 0 0 1 1 0 0 1 1 0 0 11 0 0 0 0 0 0 1 1 1 1 1 1 11

Use the “sum of product” technique to get the logic expressions for the selection lines and Use the “sum of product” technique to get the logic expressions for the selection lines and the load signal:

the load signal:

S1 = T2 + T3 S1 = T2 + T3 S0 = T1 + T3 S0 = T1 + T3 Load = T0 + T1 + T2 + Load = T0 + T1 + T2 + T3T3 3)

3) Represent the following conditional control statement by two register transferRepresent the following conditional control statement by two register transfer statements with control functions.

statements with control functions. IF (P= =1) then (R1

IF (P= =1) then (R1 ←← R2) else if (Q= =1) then (R1 R2) else if (Q= =1) then (R1 ←← R3) R3) Solution: Solution: P P : : R1R1 R2 R2 P’Q P’Q : : R1R1  R3 R3 4)

4) A digital computer has a common bus system A digital computer has a common bus system for 16 registers of 32 bits for 16 registers of 32 bits each. Theeach. The bus is constructed with multiplexers.

bus is constructed with multiplexers. a)

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g g e e 2 2 9 9 b)

b) What size of multiplexers is needed?What size of multiplexers is needed? c)

c) How many multiplexers are the in the bus?How many multiplexers are the in the bus? Solution:

Solution: a)

a) 4 selection lines to select one of 16 registers.4 selection lines to select one of 16 registers. b)

b) 16 × 1 multiplexers.16 × 1 multiplexers. c)

c) 32 multiplexers, one for each bit of the registers.32 multiplexers, one for each bit of the registers. 5)

5) The following transfer statements specify a memory. Explain the memory operationThe following transfer statements specify a memory. Explain the memory operation in each case: in each case: a. a. R2R2 ←← M[AR] M[AR] b. b. M[AR] ←M[AR] ← R3 R3 c. c. R5R5 ←← M[R5] M[R5] Solution: Solution: a)

a) Read memory word specified by the address in AR into register R2.Read memory word specified by the address in AR into register R2. b)

b) Write content of Write content of register R3 into the memory word speregister R3 into the memory word specified by the address in AR.cified by the address in AR. c)

c) Read memory word specified by the address in R5 and transfer content to Read memory word specified by the address in R5 and transfer content to R5(destroyR5(destroy previous value).

previous value). 6)

6) Draw the block diagram for the hardware that implements the followingDraw the block diagram for the hardware that implements the following statements:

statements:

x + yz: AR

x + yz: AR ←← AR + BR AR + BR

Where AR and BR are two n-bit registers and x, y, and z are control variables. Where AR and BR are two n-bit registers and x, y, and z are control variables. Include logic gates for control the function.

Include logic gates for control the function. Solution:

Solution:

7)

7) Consider the following register transfer statements for two 4-bit registers R1 andConsider the following register transfer statements for two 4-bit registers R1 and R2. R2. xT: R1 xT: R1←←R1+R2R1+R2 x x′′T: R1T: R1←←R2R2

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3 3 0 0

x=1, or the content of R2 is transferred to R1 if x=0. Draw a diagram showing the x=1, or the content of R2 is transferred to R1 if x=0. Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two hardware implementation of the two statements. Use block diagrams for the two 4-bit registers, a 4-4-bit adder, and a quadruple 2-to-1-line multiplexer that selects the bit registers, a 4-bit adder, and a quadruple 2-to-1-line multiplexer that selects the inputs to R1. In the diagram, show how the control variables x and T select the inputs to R1. In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1.

inputs of the multiplexer and the load input of register R1. Solution:

Solution:

8)

8) Show the hardware that implements the following statement. Include the Show the hardware that implements the following statement. Include the logic gates forlogic gates for the control function and a block diagram for the

the control function and a block diagram for the binary counter with a binary counter with a count enable input.count enable input. xyT0

xyT0 + T1 + y’T2 : AR+ T1 + y’T2 : AR  AR + 1 AR + 1

9)

9) Design a 4-bit combinational circuit decrementer using 4 full-adder circuits.Design a 4-bit combinational circuit decrementer using 4 full-adder circuits. Solution:

Solution:

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g g e e 3 3 1 1 10)

10) Design an arithmetic circuit with one selection variable S and two n-bit data inputsDesign an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The A and B. The circuit circuit generates the generates the following four following four arithmetic arithmetic operations in operations in conjunction conjunction with the input with the input

carry Cin. carry Cin. Draw the Draw the logic diagram logic diagram for the first for the first two stages. two stages.

Solution: Solution:

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3 3 2 2

11)

11) Register A holds the 8-bit Register A holds the 8-bit binary value 11011001. Determine the B operand and the binary value 11011001. Determine the B operand and the logiclogic micro- operation to be performed in order to change t

micro- operation to be performed in order to change the value in A to:he value in A to: a. 01101101 a. 01101101 b. 11111101 b. 11111101 Solution: Solution: 12)

12) The 8-bit registers AR, BR, CR , & DR initially have The 8-bit registers AR, BR, CR , & DR initially have the following values:the following values: AR = 1111 0010 AR = 1111 0010 BR = 1111 1111 BR = 1111 1111 CR = 1011 1001 CR = 1011 1001 DR = 1110 1010 DR = 1110 1010

Determine the 8-bit values in each register after the execution of the following Determine the 8-bit values in each register after the execution of the following sequence of micro-operations. sequence of micro-operations. AR AR ←← AR + BR AR + BR CR CR ←← CR CR DR, DR, BRBR ←← BR + 1 BR + 1 AR AR ←← AR AR – – CR CR 1. 1. AR AR : : 1111 1111 00100010 BR BR : : 1111 1111 11111111 AR + BR : 1111 0001 AR + BR : 1111 0001 AR : 1111 00 AR : 1111 0001 01 BR : 1111 11BR : 1111 1111 11 CR : 1011 1CR : 1011 1001 001 DR : 1110 1DR : 1110 1010010 2. 2. CR CR : : 1011 1011 1001 1001 BR BR : : 1111 1111 11111111 DR DR : : 1110 1110 1010 1010 : : 11 CR CR DR DR : : 1010 1010 10001000 BR BR + + 1 1 : : 0000 0000 00000000

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g g e e 3 3 3 3 AR : 1111 00 AR : 1111 0001 01 BR : 0000 00BR : 0000 0000 00 CR : 1010 1CR : 1010 1000 000 DR : 1110 1DR : 1110 1010010 3. 3. AR AR : 1111 : 1111 00010001 CR CR : : 1010 1010 10001000 AR - BR : 0100 1001 AR - BR : 0100 1001 AR : 0100 10 AR : 0100 1001 01 BR : 0000 00BR : 0000 0000 00 CR : 1010 1CR : 1010 1000 000 DR : 1110 1DR : 1110 1010010 13)

13) An 8-bit register contains the binary value 10011100. What is the register valueAn 8-bit register contains the binary value 10011100. What is the register value after arithmetic shift right? Starting from the initial number 10011100, determine after arithmetic shift right? Starting from the initial number 10011100, determine the register value after an arithmetic shift left, and state whether there is an the register value after an arithmetic shift left, and state whether there is an overflow. overflow. Solution: Solution: R = 10011100 R = 10011100 Arithmetic shift ri

Arithmetic shift right: 11001110ght: 11001110

Arithmetic shift left: 00111000 overflow because a negative number changed to positive. Arithmetic shift left: 00111000 overflow because a negative number changed to positive.

14)

14) Starting from an initial Starting from an initial value of R = 11010111, determine the sequence value of R = 11010111, determine the sequence of binary valuesof binary values of R after a

of R after a logical shift left, followed by a circular shift-right, logical shift left, followed by a circular shift-right, followed by a logical shiftfollowed by a logical shift right and a circular shift right.

right and a circular shift right. Solution:

Solution:

R = 11010111 R = 11010111 Logical shift left:

Logical shift left: 1010111010101110 Circular shift-right: 01010111 Circular shift-right: 01010111 Logical shift right: 00101011 Logical shift right: 00101011 Circular shift right: 10010101 Circular shift right: 10010101 15)

15) What is wrong with the following register tWhat is wrong with the following register transfer statements?ransfer statements? a. XT : AR a. XT : AR ←← (AR) (AR)′′ , AR , AR ←← 0 0 b. YT: R1 b. YT: R1 ←← R2, R1 R2, R1 ←← R3 R3 c. ZT: PC c. ZT: PC ←← AR, PC AR, PC ←← PC+1 PC+1 Solution: Solution:

a. Cannot complement and clear the same register at the same time. a. Cannot complement and clear the same register at the same time.

b. Cannot transfer two different values (R2 and R3) to the same register (R1) at the same b. Cannot transfer two different values (R2 and R3) to the same register (R1) at the same time.

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3 3 4 4

at the same time. at the same time. 16)

16) Design a digital circuit Design a digital circuit that performs the four logic operations of exclusive-OR, exclusive-that performs the four logic operations of OR, exclusive-NOR, NOR and NAND. Use

NOR, NOR and NAND. Use two selection variables. Show the logic diagram two selection variables. Show the logic diagram of one typicalof one typical stage.

stage.

QUESTION BANK QUESTION BANK



 What is register transfer language? Clear it with example.What is register transfer language? Clear it with example.



 Explain the operation of three state bus buffers and show its use in design ofExplain the operation of three state bus buffers and show its use in design of common bus.

common bus.



 Define: RTL, Computer Organization, Micro-operationDefine: RTL, Computer Organization, Micro-operation



 Explain selective set, selective complement aExplain selective set, selective complement and selective clearnd selective clear



 Explain 4-bit incrementer with necessary diagram.Explain 4-bit incrementer with necessary diagram.

