Differential Amplifiers: Implementation on ICs

Differential Amplifiers:

Implementation on ICs

Replacing

R

_SS

and

R

_D

with

current-sources and active loads

I_D

I_D

Resistor R

_ss

provides

source degeneration for a stable bias

F. Najmabadi, ECE102, Fall 2012 (2/29)

I_D I_D

I_D I_D

2I_D

Bias (Common Mode circuit )

 _{In discrete circuits, bias is similar to that of a CS amplifier (source degeneration}

with a source resistor).

 _However R_{SS does not affect the differential gain and , in fact, should be large}

Differential amplifier with current source active load

Q1 and Q2 are identical &V_G2 = V_G1

Q3 and Q4 are identical

o Q3/Q4 act active load/ current source (similar to a CS amplifier).

Q5 is necessary

o For signals, Q5 provides R_SS = r_o5 necessary for reducing common-mode gain (a large R_SS = r_o5 can be obtained without significant voltage drop across Q5).

o Parameters of Q5 (i.e., W/L, V_G) should be chosen such that I_D3= I_D4 = 0.5 I_D5 . o Q5 eases the necessary precision in biasing Q1 and Q2 gates.

Differential amplifier with

current source active load – Bias

F. Najmabadi, ECE102, Fall 2012 (4/29)

 Q1 and Q2 are identical & V_G2= V_G1

 Q3 and Q4 are identical

 _{Parameters of Q5 (i.e.,} W/L, V_{G) are chosen such}

that I_D3= I_D4 = 0.5 I_D5 5 4 3 2 1 2 1 2 1 5 . 0 D D D D D OV OV GS GS I I I I I V V V V = = = = = ⇒ =

Ignoring channel-length modulation:*

1. I_D1 = I_D3 = 0.5 I_D5 sets V_OV1 and V_GS1 2. V_S1 = V_GS1 −V_G1

3. V_D5 = V_S1

4. V_DS5 = V_S1 +_VSS

5. We need to include channel-length modulation to find V_DS1 and V_DS3

6. Precise biasing of Q1 and Q2 are not necessary to get correct I_D1 (it only affects V_DS1 and V_DS3 )*

* Similar results are obtained if we do not ignore channel-length modulation:

Differential amplifier with

current source active load – Signal analysis

r_o3 = r_o4

Differential amplifier with

current source active load – Signal analysis

F. Najmabadi, ECE102, Fall 2012 (6/29)

Common Mode d m o d o d m d m d o v r r g v v v r r g v r r g v ) || ( 5 . 0 ) || ( 5 . 0 ) 5 . 0 ( ) || ( o3 o1 1 1 , 2 o3 o1 1 o3 o1 1 , 1 − = − = = − − = c o c o o o o m o m c c o v v r r r g r g v v , 2 , 1 1 3 5 1 3 1 , 1 / 2 1 = + + − = Differential Mode

Cascode differential amplifier

Cascode amplifier Cascode active load

Bias analysis is similar to the case of differential amplifier with current-source active load.

No reason to put a cascode current source here.

Cascode differential amplifier – Signal analysis

F. Najmabadi, ECE102, Fall 2012 (8/29)

Small signal

Cascode differential amplifier – Signal analysis

Differential Mode

(

)

d o d o d m m m d o o m o o m o o o o m m m d o v v v r r g r r g g v r r g r r g r r r r g g g v , 1 , 2 o7 o5 5 o1 o3 3 1 7 5 5 3 1 3 7 5 3 1 5 3 1 , 1 ) 5 . 0 ( || ) 5 . 0 ( − = − − = − × + − ≈

Cascode differential amplifier – Signal analysis

F. Najmabadi, ECE102, Fall 2012 (10/29)

Common Mode 2 9 7 5 5 , 1 , 2 c o o o m c o c o v r r r g v v = ≈ − × For g_m r_o >> 1*

Differential Amplifiers –

Output Configurations

Typical implementation of differential amplifier circuits

Output Configurations of Differential Amplifiers

F. Najmabadi, ECE102, Fall 2012 (12/29)

Differential Output

Differential Amplifiers with Differential Output

Differential Output

Differential Mode

Common Mode

Not used often because the load floats (i.e., not attached to the ground

Differential Amplifiers with Differential Output

F. Najmabadi, ECE102, Fall 2012 (14/29)

Differential Output Differential Mode Common Mode /2) || || ( /2) || || ( 2 ) 5 . 0 /2)( || || ( , 1 , 1 , 2 , 1 , 2 , 1 L D o m d od d d L D o m d o d o d o od d o d o d L D o m d o R R r g v v A v R R r g v v v v v v v R R r g v − = = − = − = − = − = − − = 0 0 / 2 1 , 1 , 2 , 1 , 2 , 1 = = = − = = + + − = c oc c c o c o oc c o c o o D SS m D m c c o v v A v v v v v r R R g R g v v ∞ = = | | | | CMRR c d A A d d c c o A v A v v = ⋅ + ⋅

Differential Amplifiers with Two Outputs

Differential Mode

Common Mode

Two Separate Outputs (R_L1 ≈ _{RL2 = RL}) (i.e., input to another difference amplifier)

Note: To use half circuit, (R_L1 ≈ R_L2) or

R_L should be large enough so that

Differential Amplifiers with Two Outputs

F. Najmabadi, ECE102, Fall 2012 (16/29)

o L D SS m L D m c c o o L D SS m L D m c c o r R R R g R R g v v r R R R g R R g v v / ) || ( 2 1 ) || ( / ) || ( 2 1 ) || ( 2 2 , 2 1 1 , 1 + + − = + + − = Differential Mode Common Mode ) || || ( 5 . 0 ) || || ( 5 . 0 2 , 2 1 , 1 L D o m d d o L D o m d d o R R r g v v R R r g v v − = + − = −

Note: Each output has its own differential- and common-mode gains: d d c c o c c o c d d o d v A v A v v v A v v A ⋅ + ⋅ = = = 1 1 1 , 1 1 , 1 1 ,

Typical implementation of differential

amplifiers with two outputs

B i A

o v

v _1, = _1,

Amplifier Stage A Amplifier Stage B

B i A o v v _2, = _2, CS Amp: R_L = ∞ for Stage A

Differential Amplifiers with

Single-ended Output

F. Najmabadi, ECE102, Fall 2012 (18/29)

Single-ended Output

Differential Mode

Common Mode

To use half circuit, R_L should be large enough such that symmetry is preserved (i.e. R_L >> R_o = R_D||r_o)

Differential Amplifiers with

Single-ended Output

Single-ended Output Differential Mode Common Mode ) || || ( 5 . 0 ) || || ( 5 . 0 ) || || ( 5 . 0 2 2 L D o m d od d d L D o m o od L D o m d o R R r g v v A v R R r g v v R R r g v v − = = − = = − = o L D SS m L D m c oc c r R R R g R R g v v A / ) || ( 2 1 ) || ( + + − = = d d c c o A v A v v = ⋅ + ⋅

To use half circuit, R_L Should be large so that symmetry is preserved

(i.e. R_L >> R_o = R_D||r_o) Note: Ac ≠ 0 which means

An implementation of differential amplifiers

with an output (coupled to a CS amplifier)

F. Najmabadi, ECE102, Fall 2012 (20/29)

CS stage Differential Amplifier

Active load for a single-ended output

Works fine but require biasing of

Q3 and Q4 (i.e., V_G3) “Popular” active load for single-ended output  _{Q3/Q4 are NOT current sources and do}

not require biasing (i.e., V_G3)

 Gets a similar gain and CMRR

 But, circuit is NOT symmetric (half-circuit does not work!)

Active load for a single-ended output:

Small signal equivalent

F. Najmabadi, ECE102, Fall 2012 (22/29)

Small Signal

Diode-connected transistor

Small-signal analysis of single-ended output

Note r_o4 = r_o3 and g_m4 = g_m3

r_o2 = r_o1 and g_m2 = g_m1

Small Signal

Circuit is NOT symmetric CANNOT use “half-circuit”

Small-signal analysis of single-ended output –

Differential Gain (1)

F. Najmabadi, ECE102, Fall 2012 (24/29)

r_o4 = r_o3 and g_m4 = g_m3 r_o2 = r_o1 and g_m2 = g_m1 v_gs1 = − _0.5vd − _v5 v_gs2 = + _0.5vd − v₅ 0 ) 5 . 0 ( ) 5 . 0 ( 0 ) 5 . 0 ( 0 ) 5 . 0 ( 5 1 5 1 1 5 1 3 5 5 5 1 5 5 1 3 3 3 1 5 3 5 1 3 3 = − + − − − − − + − + = − + − + + + = − + − − + v v g v v g r v v r v v r v r v v v v g r v v g r v v v v g v g d m d m o o o g o o o d m o o g m o g d m g m Node v_g3 Node v_o Node v₅

Small-signal analysis of single-ended output –

Differential Gain (2)

( )

0 1 1 2 2 1 5 . 0 1 1 1 5 . 0 1 1 1 5 1 1 5 1 3 1 1 3 1 1 5 3 3 1 1 1 5 1 3 3 =       − +       + + + +       − − =       + +       − − + + =       − − +       + o o o o m o g d m o o o o m m g d m o m o m g r v r r g v r v v g r r v r g v g v v g r g v r g v

Dropping 1/r_o terms compared with g_m

Rearranging terms:

( )

(

)

( )

(

)

(

2

)

1 0 1 5 . 0 1 1 5 . 0 1 1 5 1 3 1 1 3 1 5 3 3 1 1 5 3 3 =       − + + +       − − =       + + − + + = − + o o m o g d m o o o m m g d m m m g r v g v r v v g r r v g v g v v g g v g v

Dropping v₅ /r_o5 term implies that very little current flows into

r_o5 (can remove r_o5 from the circuit as done in the textbook)

Small-signal analysis of single-ended output –

Differential Gain (3)

F. Najmabadi, ECE102, Fall 2012 (26/29)

( )

(

)

( )

(

)

(

2

)

1 0 1 5 . 0 1 1 5 . 0 1 1 5 1 3 1 1 3 1 5 3 3 1 1 5 3 3 =       − + + +       − − =       + + − + + = − + o o m o g d m o o o m m g d m m m g r v g v r v v g r r v g v g v v g g v g v

Subtracting second equation from the first*:

) || ( ) || ( || ₃ 1 1 1 3 1 1 3 1 o o m d d o o m o d m o o o r r g A v r r g v v g r r v _{= − ⇒ = − ⇒ = −}

* This is sloppy math as if subtract 2nd _{equation from first before dropping} r

o terms, a vg3 term appears in the above equation. Fortunately, as v_g3 << v_o, ignoring v_g3 term is justified

Adding all three equations give:

d o m m d o m o o m g o m o g o o g m v r g g v r g r r g v r g v v r v v g 3 1 3 3 3 1 1 3 3 3 3 3 3 3 4 2 ) || ( 2 0 2 ≈ + = − = ⇒ = + Note: v_g3 << v_o Textbook Eq. 7.1.40 is incorrect

Small-signal analysis of single-ended output –

Common-mode Gain (1)

r_o4 = r_o3 and g_m4 = g_m3 r_o2 = r_o1 and g_m2 = g_m1 v_gs1 = − _0.5vd − _v5 v_gs2 = + _0.5vd − v₅ 0 ) ( ) ( 0 ) ( 0 ) ( 5 1 5 1 1 5 1 3 5 5 5 1 5 5 1 3 3 3 1 5 3 5 1 3 3 = − − − − − + − + = − + − + + = − + − + v v g v v g r v v r v v r v r v v v v g r v v g r v v v v g v g c m c m o o o g o o o c m o o g m o g c m g m Node v_g3 Node v_o Node v₅

Small-signal analysis of single-ended output –

Common-mode Gain (2)

F. Najmabadi, ECE102, Fall 2012 (28/29)

0 ) ( ) ( 0 ) ( 0 ) ( 5 1 5 1 1 5 1 3 5 5 5 1 5 5 1 3 3 3 1 5 3 5 1 3 3 = − − − − − + − + = − + − + + = − + − + v v g v v g r v v r v v r v r v v v v g r v v g r v v v v g v g c m c m o o o g o o o c m o o g m o g c m g m

Subtracting second equation from the first and dropping 1/r_oterms compared with g_m

∞ = ⇒ = ⇒ = 0 0 CMRR || ₃ 1 c o o o A r r v ) || ( 2 CMRR 2 1 2 1 3 1 1 5 3 5 3 5 3 o o m o m o m c c o m o g r g r r r g A v r g v = ⇒ = ⇒ =

Small-signal analysis of single-ended output –

Output Resistance

0 ) ( ) ( ) ( 0 ) ( 5 1 5 1 1 5 1 3 5 5 5 1 5 5 1 3 3 3 1 5 3 5 1 3 3 = − − − − − + − + = − + − + + = − + − + v g v g r v v r v v r v i r v v v g r v v g r v v v g v g m m o x o g o x o x m o x g m o g m g m Node v_g3 Node v_x Node v₅

Subtracting second equation from the first and dropping 1/r_o terms compared with g_m

3 1 3 1 || || o o x x o x o o x r r i v R i r r v = = =

Attach a source v_x to the output and calculate i_x)