Analog Circuits GATE

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GATE-1999 One Mark Questions GATE-1999 One Mark Questions 1. The first

1. The first dominant pole encounteredominant pole encountered in the d in the frequency response of afrequency response of a compensated op-amp is approximately at

compensated op-amp is approximately at a.

a. 5 5 Hz Hz b. b. 10 10 kHzkHz c.

c. 1 1 MHz MHz d. d. 100 100 MHzMHz

2. Negative feedback in an amplifier 2. Negative feedback in an amplifier a. reduce gain

a. reduce gain

b. increase frequency and phase distortions b. increase frequency and phase distortions c. reduces bandwidth

c. reduces bandwidth d. increases noise d. increases noise

3. In the cascade amplifier shown in

3. In the cascade amplifier shown in the figthe figure, if the common-emitter stage (Qure, if the common-emitter stage (Q11)) has a transconductange g

has a transconductange g_m1_m1, and the common base stage (Q, and the common base stage (Q₂₂) has a) has a transcodnuctanc

transcodnuctance e gg_m2_m2 then the overall transconductance g(=ithen the overall transconductance g(=i₀₀ /v /v_ii) of the cascade) of the cascade amplifier is amplifier is Q Q ii ii V V R R 2 2 Q Q 1 1 ← ← V V o o o o L L a. g a. gm1m1 b. g b. g_m2_m2 c. g c. g_m1_m1 /2 /2

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d. gm d. gm22 /2 /2

4. Crossover distortion behaviour is characteristic of 4. Crossover distortion behaviour is characteristic of a.

a. Class Class A A output output stage stage b. b. Class Class B B output output stagestage c.

c. Class Class AB AB output output stage stage d. d. Common-base Common-base output output stagestage

GATE-1999 Two Marks Questions GATE-1999 Two Marks Questions 5. An npn transistor (with C = 0.3

5. An npn transistor (with C = 0.3 pF) has a unit-gain cutoff frequencypF) has a unit-gain cutoff frequency f f TTof 400of 400 MHz at a dc bias current I

MHz at a dc bias current Icc = 1mA. The value of its C= 1mA. The value of its Cµ µ (in pF) (in pF) is approximatelyis approximately (V (V_T_T= 26 mV)= 26 mV) a. a. 15 15 b. b. 3030 c. c. 50 50 d. d. 9696

6. An amplifier has an

open-6. An amplifier has an open-

loop gain of 100, an input impedance of 1kΩ and an

output impedance of 100Ω. A

output impedance of 100Ω. A feedback network with a feedback factor of 0.99 is

feedback network with a feedback factor of 0.99 is

connected to the amplifier in a voltage series feedback mode. The new

connected to the amplifier in a voltage series feedback mode. The new input andinput and output impedances, respectively are.

output impedances, respectively are.

a. 10 Ω and 1 Ω

b. 10 Ω and 10 Ω

c. 100 k Ω and 1 Ω

d. 100 kΩ and 1 k Ω

7. A dc power supply has a

7. A dc power supply has a no-load voltage of 30 V, and a full-load voltage of 25no-load voltage of 30 V, and a full-load voltage of 25 V at a

V at a full-load current of 1A. Its output resistance and full-load current of 1A. Its output resistance and load regulation,load regulation, respectively are

respectively are

a. 5 Ω and 20%

b. 25 Ω and 20%

c. 5 Ω and 16.7%

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8. An amplifier is assumed to

8. An amplifier is assumed to have a single-pole high-frequency transfer function.have a single-pole high-frequency transfer function. The rise time of its output response to a step function input is 35 nsec. The upper The rise time of its output response to a step function input is 35 nsec. The upper

–

3 dB frequency (in

3 dB frequency (in MHz) for the amplifier to a sinusoidal input MHz) for the amplifier to a sinusoidal input is approximately atis approximately at a.

a. 4.55 4.55 b. b. 1010 c.

c. 20 20 d. d. 28.628.6

GATE-2000 One Mark Questions GATE-2000 One Mark Questions

9. In the differential amplifier of the figure, if the

9. In the differential amplifier of the figure, if the source resistancesource resistance of the currentof the current source I

source IEEEE is infinite, then the is infinite, then the common-modcommon-mode gain ise gain is a. zero

a. zero b. infinite b. infinite c.

c. indetermindeterminateinate

d. d. EE EE EE EE EE -V -V ↓ ↓ V V R R R R in1 in1 V Vin2in2 II

10. In the circuit of the figure V 10. In the circuit of the figure V₀₀ isis

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R R R R 0 0 +15V +15V + + 1V1V V V -15V -15V a. a. -1V -1V b. b. 2V2V c. c. + + 1V 1V d. d. + + 15V15V

11. Introducing a resistor in the

11. Introducing a resistor in the emitter of a common aemitter of a common a mplifier stabilizes the dcmplifier stabilizes the dc operating point against variations in

operating point against variations in a. only

a. only the temperaturethe temperature

b. only the β of the transistor

c. both temperature and β

d. none of d. none of the abovethe above 12. The current gain of

12. The current gain of a bipolar transistor drops at high frequencies because of a bipolar transistor drops at high frequencies because of a. transistor

a. transistor capacitancecapacitancess

b. high current effects in the base b. high current effects in the base c. parasitic

c. parasitic inductive elementsinductive elements d. the Early effect

d. the Early effect

13. If the op-amp in the figure is ideal, the v 13. If the op-amp in the figure is ideal, the v00 isis

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C C Sin Sin C C C C tt Sin Sin tt a.

a. zero zero b. b. (V(V11-V-V22) sin) sin

ωt

c.

–

(V(V11 + V+ V22

) sinωt

d. (Vd. (V11 + V+ V22

) sinωt

14. The configuration of the figure is

R R C C C C R R a.

a. precision precision integratointegrator r b. b. Hartely Hartely oscillatoroscillator c.

c. Butterworth Butterworth high high pass pass filter filter d. d. Wien-bridge Wien-bridge oscillatoroscillator

15. Assume that the op-amp of the figure is ideal. If V

15. Assume that the op-amp of the figure is ideal. If Vii is a triangular wave then vis a triangular wave then v00 will be

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R R

C C

a.

a. square square wave wave b. triangular b. triangular wavewave c.

c. parabolic parabolic wave wave d. d. sine sine wavewave

16. The most commonly used amplifier in sample and

16. The most commonly used amplifier in sample and hold circuits ishold circuits is a. a unity gain inverting amplifier

a. a unity gain inverting amplifier b. a

b. a unity gain non-inverting amplifierunity gain non-inverting amplifier c. an inverting amplifier with a gain of c. an inverting amplifier with a gain of 1010 d. an inverting amplifier with a gain of d. an inverting amplifier with a gain of 100100

GATE-2000

GATE-2000 Two Two Marks Marks QuestionsQuestions 17. In the circuit of

17. In the circuit of the figure, assume that the transistor is in the figure, assume that the transistor is in the active region. Itthe active region. It has a large

has a large

β and its base emitter voltage is 0.7V. the value of I

_cc isis

II R R ↓ ↓ 10K 10K 5K 5K 15V 15V c c c c 430 430 a. Indeterminate since R

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b. 1mA b. 1mA c. 5 mA c. 5 mA d. 10 mA d. 10 mA

18. If the op-amp in the figure has an input offset voltage of 5mV and an 18. If the op-amp in the figure has an input offset voltage of 5mV and an open-loop voltage gain of 10,000 then v

loop voltage gain of 10,000 then v₀₀ will bewill be

+15V +15V -15V -15V a. a. 0V 0V b. b. 5mV5mV c. +15V or c. +15V or

–

15V 15V d. d. +50V +50V oror

–

50V50V

GATE-2001 One Mark Questions GATE-2001 One Mark Questions 19. The current gain of a BJT is 19. The current gain of a BJT is a. g

a. g_m_mrr_o_o b. gb. g_m_m /r /r₀₀ c. g

c. gmmrrππ d. gd. gmm /r /rππ

20. The ideal OP-AMP

20. The ideal OP-AMP has the following characteristics.has the following characteristics. a. R

a. Rii

= ∞, A= ∞, R

00 = = 0 0 b. b. RRii

= 0, A= ∞, R

00 = 0= 0 c. R

c. R11

= ∞, A= ∞, R

00

= ∞

d. Rd. Rii

= 0, A= ∞, R

00

= ∞

21. Consider the following two statements:

21. Consider the following two statements: Statement 1:

Statement 1:

A stable multivibrator can be used for

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Statement 2: Statement 2:

Bistable multivibrator can be used for storing binary information. Bistable multivibrator can be used for storing binary information. a. Only statement 1 is

a. Only statement 1 is correctcorrect b. Only statement 2 is

b. Only statement 2 is correctcorrect

c. Both the statements 1 and 2 are correct c. Both the statements 1 and 2 are correct d. Both the statements 1 and 2 are incorrect d. Both the statements 1 and 2 are incorrect

GATE-2001 Two Marks Questions GATE-2001 Two Marks Questions 22. An npn BJT has g

22. An npn BJT has gmm = 38 mA/V, C= 38 mA/V, Cµ µ = 10= 10-14-14 F, CF, Cππ = 10= 10-13-13 F, and DC current gainF, and DC current gain

ββ

00 = 0-. For this transistor f = 0-. For this transistor f TT and f and f ββ areare a. f a. f _T_T= 1.64 x 10= 1.64 x 1088 Hz and f Hz and f ββ= 1.47 x 10= 1.47 x 101010HzHz b. f b. f TT= 1.47 x 10= 1.47 x 101010Hz and f Hz and f ββ = 1.64 x 10= 1.64 x 1088HzHz c. f c. f TT= 1.33 x 10= 1.33 x 101212 Hz and f Hz and f ββ = 1.47 x 10= 1.47 x 101010 HzHz d. f d. f _T_T= 1.47 x 10= 1.47 x 101010Hz and f Hz and f ββ = 1.33 x 10= 1.33 x 101212HzHz

23. The transistor shunt

23. The transistor shunt regulator shown in the figure has a regulator shown in the figure has a regulated outputregulated output voltage of 10V, when the

voltage of 10V, when the input varies from 20V to 30V. input varies from 20V to 30V. the relevant paramethe relevant parametersters for the zener diode and

for the zener diode and the transistor are: Vthe transistor are: Vzz= 9.5, V= 9.5, VBEBE

= 0.3V β = 99.

= 0.3V β = 99. neglect the

neglect the

current through R

current through R_B_B. then the maximum power dissipated in the zener diode (P. then the maximum power dissipated in the zener diode (P_zz)) and the transistor (P

and the transistor (P_T_T) are) are

↓ ↓ → → V V ↓ ↓ V V 20 20 II 20-30 V 20-30 V II R R =10V =10V B B --z z c c BE BE z z + + a. P a. Pzz = 75 mW, P= 75 mW, PTT= 7.9 W= 7.9 W

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b. P b. Pzz = 85 mW, P= 85 mW, PTT= 8.9 W= 8.9 W c. P c. P_zz = 95 mW, P= 95 mW, P_T_T= 9.9 W= 9.9 W d. P d. Pzz = 115 mW, P= 115 mW, PTT= 11.9 W= 11.9 W

24. The oscillator circuit shown in

24. The oscillator circuit shown in the figure isthe figure is

C C_c_c L L --C C c c 1 1_=2pF_=2pF e e 2 2 L L C C _C_C H H =10 =10 =2pF =2pF

a. Hartley oscillator with f

a. Hartley oscillator with f oscillationoscillation= 79.6 MHz= 79.6 MHz b. Colpitts oscillator with f

b. Colpitts oscillator with f oscillationoscillation = 50.3 MHz= 50.3 MHz c. Hartley oscillator with f

c. Hartley oscillator with f _oscillation_oscillation= 159.2 MHz= 159.2 MHz d. Colpitts oscillator with f

d. Colpitts oscillator with f _oscillation_oscillation = 159.2 MHz= 159.2 MHz

25. The inverting OP-AMP shwn in the figure has an open-loop gain of 100. the 25. The inverting OP-AMP shwn in the figure has an open-loop gain of 100. the closed-loop gain V

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+ + =1K =1K =10K =10K --a. a.

–

8 8 b. b. -9-9 c. c. -10 -10 d. d. -11-11

26. In the figure assume the OP-AMPs to be ideal. The

26. In the figure assume the OP-AMPs to be ideal. The output voutput v₀₀ of the circuit is:of the circuit is:

+ + --10mH 10mH 100 100 10 10 =10co =10cos (s (100t)100t) 10 10 FF 3 3 1 1 2 2 + + --=10co =10cos (s (100t)100t) 10 10 10mH 10mH 100 100 10 10 1 1 2 2 33 F F a. a. 10 10 cos cos (100t) (100t) b.b. c. c. d.d.

GATE-2002 One Mark questions GATE-2002 One Mark questions

27. In a negative feedback amplifier using voltage series (i.e.

27. In a negative feedback amplifier using voltage series (i.e. voltage smapling,voltage smapling, series mixing) feedback,

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a. R

a. Rii decreases and Rdecreases and R00 decreasesdecreases b. R

b. R_ii decreases and Rdecreases and R₀₀ increasesincreases c. R

c. Rii increases and Rincreases and R00 decreasesdecreases d. R

d. Rii increases and Rincreases and R00 increasesincreases (R

(R_ii and Rand R₀₀ denote the input denote the input and output resistance respectively)and output resistance respectively)

28. A 741-type opamp has a gain-bandwidth product of 1 MHz. A non

28. A 741-type opamp has a gain-bandwidth product of 1 MHz. A non invertinginverting amplifier using this opamp and having a voltage g

amplifier using this opamp and having a voltage gain of 20dB will exhibit a ain of 20dB will exhibit a 3-dB3-dB bandwidth of bandwidth of a. a. 50 50 KHz KHz b. b. 100 100 KHzKHz c. c. 1000/17 1000/17 KHz KHz d/ d/ 1000/7.07 1000/7.07 KHzKHz

29. Three identical RC-coupled transistor amplifiers are cascaded. If each of 29. Three identical RC-coupled transistor amplifiers are cascaded. If each of thethe amplifiers has a frequency responses as

amplifiers has a frequency responses as shown in the figure, the shown in the figure, the overall frequencyoverall frequency response is as given in

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GATE-2002 Two

GATE-2002 Two Marks QuestionsMarks Questions

30. An amplifier using an opam with a slew-rate SR=1 V/µ

30. An amplifier using an opam with a slew-rate SR=1 V/µsec has a gain of 40dB.sec has a gain of 40dB. if this amplifier has to faithfully amplifiy sinusoidal signals from dc to

if this amplifier has to faithfully amplifiy sinusoidal signals from dc to 20 KHz20 KHz without introducing any slew-rate induced distortion, then the input

without introducing any slew-rate induced distortion, then the input signal levelsignal level must not exceed.

must not exceed. a.

a. 795 795 mV mV b. b. 395 395 mVmV c.

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31. The circuit in

31. The circuit in the figure employs positive feedback and is intended to generatethe figure employs positive feedback and is intended to generate

sinusoidal osicallation. If at a frequency f

sinusoidal osicallation. If at a frequency f 00 B(f)= B(f)= then then to to sustainsustain oscillation at this frequency.

oscillation at this frequency.

B(f) B(f) Network Network (f) (f) ↑ ↑ ↓ ↓ (f) (f) -- --+ + + + a. R a. R22= 5R= 5R11 b. Rb. R22 = 6R= 6R11 c. R c. R22= R= R11 /6 /6 22 = R= R11 /5 /5d. d. RR

32. A Zener diode regulator in the figure is to be designed to meet the 32. A Zener diode regulator in the figure is to be designed to meet the specifications: I

specifications: I_L_L= 10mA, V= 10mA, V₀₀ = 10V and V= 10V and V_in_in varires from 30 V to 50V. The zenervarires from 30 V to 50V. The zener diode has V

diode has Vzz = 10V and I= 10V and Izk zk (knee current)= 1mA For satisfactory operation(knee current)= 1mA For satisfactory operation

↓ ↓ ↓ ↓ II ↑ ↑ ↓ ↓ ↑ ↑ ↓ ↓ D Dzz z z IILL==10mA10mA + +

--a. R ≤ 1800 Ω

a. R ≤ 1800 Ω

b. 2000 Ω R ≤ 22000 Ω

c. 3700 Ω ≤ R ≤ 4000 Ω

d. R > 4000 Ω

33. The voltage gain A

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+ + (1M (1M R Rss G G = +10V = +10V V V ↓ ↓ + + --II DD DD R R D D=1mA=1mA 1 1 2 2 R R C C C C s s )) C C D D )) (3K (3K )) V V_DD_DD= +10V= +10V ↓ ↓IIDD=1mA=1mA R RDD (3K (3K )) C C C C C C 1 1 2 2 s s + + + + --R R G G RRss ((11M M )) _(2.5K_(2.5K )) → → (2.5K (2.5K → → IIDssDss = 10 mA= 10 mA (Assume C

(Assume C₁₁, C, C₂₂and Cand C_ss to be very large)to be very large) a.

a. +18 +18 b. b. -18-18 c.

c. + + 6 6 d. d. -6-6

34. Consider the following statements in

34. Consider the following statements in connection with the CMOS inverter inconnection with the CMOS inverter in the figure, where both the MOSFETs are

the figure, where both the MOSFETs are of enhancement type and both have aof enhancement type and both have a thresh old voltage of 2V.

thresh old voltage of 2V. Statement 1: T

Statement 1: T11 conducts when Vconducts when V11

≥ 2V.

Statement 2: T

Statement 2: T11 is always in saturation when Vis always in saturation when V00 = 0V.= 0V.

→ → ← ← + + T T 1 1 T T 2 2 5V 5V

Which of the following is correct? Which of the following is correct?

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a. Only statement 1 is TRUE a. Only statement 1 is TRUE b. Only Statement 2 is TRUE b. Only Statement 2 is TRUE c. Both the s

c. Both the statemetatements are TRUEnts are TRUE d. Both the

d. Both the StatemStatements are FALSE.ents are FALSE.

GATE-2003 One Mark Questions GATE-2003 One Mark Questions 35. Choose the correct match for

35. Choose the correct match for input resistance of various amplifierinput resistance of various amplifier configuration shown below.

configuration shown below. Configuration

Configuration Input resistanceInput resistance CB:

CB: Common Common Base Base LO: LowLO: Low CC:

CC: Common Common Collector Collector MO: MO: ModerateModerate CE:

CE: Common Common Emitter Emitter HI: HI: HighHigh a.

a. CB-LO, CB-LO, CC-MO, CC-MO, CE-HI CE-HI b. b. CB-LO, CB-LO, CC-HI, CC-HI, CE-MOCE-MO c.

c. CB-MO, CB-MO, CC-HI, CC-HI, CE-LO CE-LO d. d. CB-HI, CB-HI, CC-LO, CC-LO, CE-MOCE-MO

36. The circuit shown in the figure is best described as a 36. The circuit shown in the figure is best described as a

~

~ OutputOutput

a.

a. bridge bridge rectifier rectifier b. b. ring ring modulatormodulator c.

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37. If the input

37. If the input to the ideal comparator shown in the to the ideal comparator shown in the figure is a sinusoidal signal of figure is a sinusoidal signal of 8V (peak to peak) without any

8V (peak to peak) without any DC component, then the output of DC component, then the output of the comparathe comparatortor has a duty cycle of

has a duty cycle of

=2V =2V V V_ref_ref Input Input Output Output a. a. 1/2 1/2 b. b. 1/31/3 c. c. 1/6 1/6 d. d. 1/121/12

38. If the differential voltage gain and the common mode v

38. If the differential voltage gain and the common mode v oltage gain of aoltage gain of a differential ampl

differential amplifier are 48 ifier are 48 dB and 2 dB and 2 dB respectively, then its common modedB respectively, then its common mode rejection ratio is rejection ratio is a. a. 23 23 dB dB b. b. 25 25 dBdB c. c. 46 46 dB dB d. d. 50 50 dBdB

39. Generally, the gain of

39. Generally, the gain of a transistor amplifier falls at high frequencies due to thea transistor amplifier falls at high frequencies due to the a. internal capacitances of the device

a. internal capacitances of the device b. coupling capacitor at the input b. coupling capacitor at the input c. skin effect

c. skin effect

d. coupling capacitor at the output d. coupling capacitor at the output GATE-2003 Two Marks Questions GATE-2003 Two Marks Questions

40. An amplifier without feedback has a voltage

40. An amplifier without feedback has a voltage gain of 50, input resistance of gain of 50, input resistance of 1K

1K

Ω and output resistance of 2.5 KΩ. The input resistance of the current

-shunt-shunt negative feedback ampli

negative feedback amplifier using the above amplifier with a fier using the above amplifier with a feedback factor of feedback factor of 0.2 is 0.2 is

a. 1/11KΩ

b. 1/5 KΩ

c. 5 KΩ

d. 11K Ω

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41. In the amplifier circuit shown in the figure, the values of R

41. In the amplifier circuit shown in the figure, the values of R11 and Rand R22 are suchare such that the transistor is operating at V

that the transistor is operating at V_CE_CE = 3V and I= 3V and I_C_C

= 1.5mA when its β is 150. for a

= 1.5mA when its β is 150.

for a

transistor with β of 200,

transistor with β of 200, the operating point (V

the operating point (V

CECE, I, ICC) is) is

a.

a. (2V, (2V, 2mA) 2mA) b. b. (3V, (3V, 2mA)2mA) c.

c. (4V, (4V, 2mA) 2mA) d. d. (4V, (4V, 1mA)1mA)

42. The oscillator circuit shown

42. The oscillator circuit shown in the figure hasin the figure has an ideal inverting amplifier. Itsan ideal inverting amplifier. Its frequency of oscillation (in Hz) is

frequency of oscillation (in Hz) is

C C C C CC R R R R RR a. b. a. b. c. d. c. d.

43. The output voltage of the regulated power

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40K 40K Power source Power source 15V DC 15V DC 1K 1K + + Regulated Regulated --V V 20K 20K z z Unregulated Unregulated DC DC OutputOutput =3V =3V a. a. 3V 3V b. b. 6V6V c. c. 9V 9V d. d. 12 12 VV

44. The action of a JFET in its equivalent circuit can best be represented as a 44. The action of a JFET in its equivalent circuit can best be represented as a a. Current Controlled Current Source

a. Current Controlled Current Source b. Current Controlled Voltage Source b. Current Controlled Voltage Source c. Voltage Controlled Voltage Source c. Voltage Controlled Voltage Source d. Voltage Controlled Current Source d. Voltage Controlled Current Source

45. If the op-amp in

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1K 1K 3V 3V 5K 5K 1K 1K 8K 8K 2V 2V a. a. 1V 1V b. b. 6V6V c. c. 14 14 V V d. d. 17V17V

46. Three identical amplifiers with each one having a volta

46. Three identical amplifiers with each one having a volta ge gain of 50, inputge gain of 50, input

resistance of 1KΩ and output

resistance of 1KΩ and output resistance of 250 Ω, are

resistance of 250 Ω, are cascaded. The open circuit

cascaded. The open circuit

voltage gain of the combined amplifier is voltage gain of the combined amplifier is a.

a. 49 49 dB dB b. b. 51 51 dBdB c.

c. 98 98 dB dB d. d. 102 102 dBdB

47. An ideal saw

47. An ideal saw tooth voltage waveform of frequency 500 Hz and tooth voltage waveform of frequency 500 Hz and amplifier 3 Vamplifier 3 V is generated by charging a capacitor of 2µ

is generated by charging a capacitor of 2µ F in every cycle. The charging requiresF in every cycle. The charging requires a. constant voltage source of 3 V for 1 ms

a. constant voltage source of 3 V for 1 ms b. constant voltage source of 3 V for 2 ms b. constant voltage source of 3 V for 2 ms c. constant current source of

c. constant current source of mA for 1 msmA for 1 ms d. constant current source of

d. constant current source of 3mA for 2 ms3mA for 2 ms

GATE- 2004 One Mark Questions GATE- 2004 One Mark Questions 48. An ideal op-amp is an ideal

48. An ideal op-amp is an ideal a. voltage controlled current source a. voltage controlled current source b. voltage controlled voltage source b. voltage controlled voltage source c. current controlled current source c. current controlled current source

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d. current controlled voltage source d. current controlled voltage source

49. Voltage series feedback (also called series-shunt feedback) results in 49. Voltage series feedback (also called series-shunt feedback) results in a. increase in both

a. increase in both input and output impedancesinput and output impedances b. decrease in both

b. decrease in both input and output impedancesinput and output impedances c. increase in input i

c. increase in input impedance and decrease in output impedanmpedance and decrease in output impedancece d. decrease in input

d. decrease in input impedancimpedance and increase in output impedancee and increase in output impedance

50. The circuit in the figure is a 50. The circuit in the figure is a

5K 5K R R R R a.

a. low-pass low-pass filter filter b. b. highigh-pass filterh-pass filter c.

c. band-pass band-pass filter filter d. d. band-reject band-reject filterfilter

51. Assuming V

51. Assuming VCEsatCEsat= 0.2V= 0.2V

and β = 50, the minimum base current (I

BB) required to) required to drive the transistor in the figure to saturation is

drive the transistor in the figure to saturation is

3V 3V → → B B II

↓

1K 1K II_c_c a. a. 56 56 µµA A b.140 b.140 mAmA c. c. 60 60 mA mA d. d. 3 3 mAmA

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GATE-2004 Two Marks Questions GATE-2004 Two Marks Questions 52. A bipolar transistor is

52. A bipolar transistor is operating in the active region with a collector current of operating in the active region with a collector current of 1 MA. Assuming that the

1 MA. Assuming that the

β of the transistor is

β of the transistor is 100 and the thermal voltage (V

100 and the thermal voltage (V

_T_T) is) is 25 mV, the transconductance (g

25 mV, the transconductance (g_m_m) and the input resistance (r) and the input resistance (rππ) of the transistor in) of the transistor in the common emitter configuration are

the common emitter configuration are a. g

a. gmm = 25mA/V and r= 25mA/V and rππ

= 15.625kΩ

b. g

b. gmm = 40/V and r= 40/V and rππ

= 4.0kΩ

c. g

c. g_m_m = 25mA/V and r= 25mA/V and rππ

= 2.5kΩ

d. g

d. g_m_m = 40 mA/V and r= 40 mA/V and rππ

= 2.5kΩ

53. The value of C

53. The value of C required for sinusoidal oscillations of frequency 1 kHz in required for sinusoidal oscillations of frequency 1 kHz in thethe circuit of the figure is

circuit of the figure is

C C C C 1K 1K 2.1K2.1K 1K 1K 1K 1K a. a.

b. 2πµ F

c. c.

d. 2 π √6 µ F

54. In the op-amp circuit given in the figure the load current i 54. In the op-amp circuit given in the figure the load current iLLisis

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L L ii

↓

a. a. b.b. c. d. c. d.

55. In the voltage regulator shown in

55. In the voltage regulator shown in the figure the load current can the figure the load current can vary fromvary from 100mA to 500 mA.

100mA to 500 mA. Assuming that the zener diode is ideal (i.e. Assuming that the zener diode is ideal (i.e. the Zener kneethe Zener knee current is negligibly small and zener resistance is

current is negligibly small and zener resistance is zero in the breakdown region),zero in the breakdown region), the value of R is the value of R is --+ + 5V 5V Varia

Variable ble LoadLoad 100 to 500 mA 100 to 500 mA 12V 12V R R a. 7 a. 7

Ω

b. 70 Ω

c. 70/3 Ω

d. 14 Ω

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56. In a

56. In a full-wave rectifiefull-wave rectifier using two r using two ideal diodes Videal diodes Vdcdc and Vand Vmmare the dc and peak are the dc and peak values of the voltage respectively across a resistive load. If P

values of the voltage respectively across a resistive load. If PIV is the peak inverseIV is the peak inverse voltage of the diode, then the appropriate relationships for

voltage of the diode, then the appropriate relationships for the rectifier arethe rectifier are

a.

a. b.b.

c. d.

57. The effect of current shunt

57. The effect of current shunt feedback in an amplifiefeedback in an amplifierr is tois to a. increase the input resistance and decrease the output

a. increase the input resistance and decrease the output resistanceresistance b. increase both input and

b. increase both input and output resistancesoutput resistances c. decrease both input and output resistance c. decrease both input and output resistance

d. decrease the input resistance and increase the output resistance d. decrease the input resistance and increase the output resistance

58. the input resistance of R

58. the input resistance of Rii of the amplifier shown in the figure isof the amplifier shown in the figure is

a.

30/4 kΩ

b. 10 K kΩ

d. 40 kΩ

d. infinited. infinite

59. The cascade amplifier is a multistage configuration of 59. The cascade amplifier is a multistage configuration of a.

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c.

c. CB-CC CB-CC d. d. CE-CCCE-CC GATE- 2005 Two Marks Questions GATE- 2005 Two Marks Questions

60. For an npn transistor connected as shown in the figure V

60. For an npn transistor connected as shown in the figure VBEBE = 0.7 volts. Given= 0.7 volts. Given that reverse saturation current of the junction at room temperature 300

that reverse saturation current of the junction at room temperature 30000K is 10K is 10-13-13 A, the emitter current is

A, the emitter current is

↑ ↑ II

↓

cc V V_BE_BE a. a. 30 30 mA mA b. b. 39 39 mAmA c. c. 49 49 mA mA d. d. 20 20 mAmA 61. The voltage e

61. The voltage e00 indicated in the figure has been measured by an indicated in the figure has been measured by an ideal voltmeter.ideal voltmeter. Which of the following can be

Which of the following can be calculated?calculated?

1 1 MM e e00 1 1 MM

a. Bias current of the

a. Bias current of the inverting input onlyinverting input only b. Bias current of

b. Bias current of the inverting and non-inverting inputs onlythe inverting and non-inverting inputs only c. Input offset current only

c. Input offset current only d. Both the

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62. The OP-amp circuit shown in the figure is a filter. The type of filter and its 62. The OP-amp circuit shown in the figure is a filter. The type of filter and its cut-off frequency are

cut-off frequency are respectiverespectivelyly

1K 1K 10 K 10 K F F 10 K 10 K 1 1 a.

a. high high pass, pass, 1000 1000 rad/sec. rad/sec. b. low b. low pass,pass, 1000 rad/sec.1000 rad/sec. c.

c. high high pass, pass, 10000 10000 rad/sec. rad/sec. d. low d. low pass, pass, 10000 10000 rad/sec.rad/sec.

63. In an ideal differential amplifier shown in the

63. In an ideal differential amplifier shown in the figure, a large value of figure, a large value of (R(R_E_E))

EE EE

-V -V

a. increases both the differential and common mode gains. a. increases both the differential and common mode gains. b. increase the

b. increase the commcommon-mode gain only.on-mode gain only. c. decrease the

c. decrease the differential-mdifferential-mode gain onlyode gain only d. decrease the

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64. For an n-channel MOSFET and its transfer curve shown in the figure, the 64. For an n-channel MOSFET and its transfer curve shown in the figure, the threshold voltage is threshold voltage is D D characteristics characteristics ↑ ↑ 1V 1V || || GS GS D D → → II V V = =

→

V V 3V_G_G3V V V S S D D G G = = 5V5V Transfer Transfer = = 1V1V V Vss

a. 1V and the device is in active region a. 1V and the device is in active region b. -1V

b. -1V and the device is in saturation regionand the device is in saturation region c. 1 V and the device is in saturation region c. 1 V and the device is in saturation region d. -1 V and the device is in active region d. -1 V and the device is in active region

65. The circuit using a BJT with

β = 50 and V

BEBE = 0.7V is shown in the = 0.7V is shown in the figure.figure. The base current I

The base current I_B_B and collector voltage Vand collector voltage V_cc are respectivelyare respectively

10 10 40 40 2k 2k 20 V 20 V 1K 1K 430K 430K F F F F a.

a. 43 43 µµA A and and 11.4 11.4 Volts Volts b. b. 40µ40µA A and and 16 16 VoltsVolts c.

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66. The zener diode in

66. The zener diode in the regulator circuit shown in the the regulator circuit shown in the figure has a Zener voltagefigure has a Zener voltage of 5.8 volts and

of 5.8 volts and a Zener knee current of 0.5mA. a Zener knee current of 0.5mA. the maximum load current drawnthe maximum load current drawn from this circuit ensuring proper functioning over the input voltage range between from this circuit ensuring proper functioning over the input voltage range between 20 and 30 volts, is 20 and 30 volts, is

↑

20-30 20-30 =5.8V=5.8V 1k 1k Load Load a. a. 23.7 23.7 mA mA b. b. 14.2 14.2 mAmA c. c. 13.7 13.7 mA mA d. d. 24.2 24.2 mAmA 67. Given the

67. Given the ideal operational amplifier circuiideal operational amplifier circuit shown in t shown in the figure indicate thethe figure indicate the correct transfer characteristics assuming ideal diodes with zero cut-in voltage. correct transfer characteristics assuming ideal diodes with zero cut-in voltage.

0.5K 0.5K -10V -10V 2K 2K +10V +10V 2K 2K

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→ → → → ↑ ↑ → → ← ← -5V -5V -8V -8V +10V +10V (a) (a) ← ← -10V -10V → → → → ↑ ↑ → → ← ← -5V -5V +8V+8V +10V +10V (b) (b) ← ← -10V -10V → → → → ↑ ↑ → → ← ← -5V -5V +5V+5V +5V +5V (c) (c) ← ← -10V -10V → → → → ↑ ↑ → → ← ← -5V -5V +5V+5V +10V +10V (d) (d) ← ← -5V -5V Common Data Questions 68, 69, 70 Common Data Questions 68, 69, 70 Given r

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68. Z

68. Zii and Zand Z00 of the circuit are respectivelyof the circuit are respectively a. 2M

a. 2M

Ω and 2k

Ω and 2k Ω

Ω

b. 2Mb. 2M

Ω and 20/11 k Ω

Ω and 20/11 k

Ω

c. infinity and 2 M

Ω

d. infinity and 20/11

d. infinity and 20/11 k Ω

k Ω

69. I

69. IDD and Vand VDSDSunder DC conditions respectivelyunder DC conditions respectively a.

a. 5.625mA 5.625mA and and 8.75 8.75 V V b. b. 7500 7500 mA mA and and 5.00V5.00V c.

c. 4.500 4.500 mA mA and and 11.00 11.00 V V d. d. 6.250 6.250 mA mA and and 7.50V7.50V

70. Transconductance in milli-Siemens (ms) and voltage gain of the

70. Transconductance in milli-Siemens (ms) and voltage gain of the amplifieamplifier arer are respectively

respectively a.

a. 1.875 1.875 ms ms and and 3.41 3.41 b. b. 1.875 1.875 ms ms and and -3.41-3.41 c.

c. 3.3 3.3 mS mS and and -6 -6 d. d. 3.3 3.3 mS mS and and 66

GATE- 2006 One Mark Questions GATE- 2006 One Mark Questions 71. The input impedance (Z

71. The input impedance (Zii) and the output ) and the output impedance (Zimpedance (Z00) of an ideal) of an ideal transconductanc

transconductance (voltage controlled current se (voltage controlled current source) amplifier areource) amplifier are a. Z

a. Z_ii = 0, Z= 0, Z₀₀= = 0 0 b. b. ZZ_ii = 0, Z= 0, Z₀₀

= ∞

c. Z

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72. An n-channel depletion MOSFET has following two points on its I

72. An n-channel depletion MOSFET has following two points on its IDD

–

VVGSGS curve.

curve. (i) V

(i) VGSGS= 0 at I= 0 at IDD = 12 mA and= 12 mA and (ii) V

(ii) VGSGS= - 6 Volts at Z= - 6 Volts at Z00

= ∞

Which of the following Q-points will give

Which of the following Q-points will give the highest trans-conductancethe highest trans-conductance gain forgain for small signals?

small signals? a. V

a. VGSGS = = -6 -6 Volts Volts b. b. VVGSGS = - 3 Volts= - 3 Volts c. V

c. VGSGS = = 0 0 Volts Volts d. d. VVGSGS = 3 Volts= 3 Volts

GATE-2006 Two Marks Questions GATE-2006 Two Marks Questions 73. For the

73. For the circuit shown in the following figure, the capacitor C is circuit shown in the following figure, the capacitor C is initiallyinitially uncharged. At t = 0, the switch S is closed. The voltage V

uncharged. At t = 0, the switch S is closed. The voltage VCC across the capacitor at tacross the capacitor at t = 1 millisecond is = 1 millisecond is 1K 1K 10V 10V F F C=1 C=1 + + S S

--In the figure shown above, the OP-AMP is supplied with ± 15 In the figure shown above, the OP-AMP is supplied with ± 15 V.V. a.

a. 0 0 Volt Volt b. b. 6.3 6.3 VoltsVolts c.

c. 9.45 9.45 Volts Volts d. d. 10 10 VoltsVolts

74. For the circuit shown below, assume that the zener diode is ideal with a break 74. For the circuit shown below, assume that the zener diode is ideal with a break down voltage of volts. The waveform observed across R is

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~ ~ RR 12sin 12sin tt + + 6V 6V R R V V --(b) (b) 6V6V (a) (a) (c) (c) -12V -12V (d) (d) 12V 12V -6V -6V -6V -6V

Common Data for Questions 75, 76

Common Data for Questions 75, 76 & 77& 77 In the transistor amplifier circuit shown in the

In the transistor amplifier circuit shown in the figure below, the transistor has thefigure below, the transistor has the following parameters.

following parameters.

ββ

DCDC= 60, V= 60, VBEBE = 0.7, h= 0.7, hieie

→∞, h

fefe

→∞

The capacitance C

The capacitance Ccc can be assumed to be can be assumed to be infinite.infinite.

5.3K 5.3K 53K 53K 1K 1K C C cc c c VV --12v 12v + + ~ ~

In the figure above, the ground has been shown by the symbol ▼

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75. Under the DC

75. Under the DC conditions, the collect to-emitter voltconditions, the collect to-emitter voltage drop isage drop is a.

a. 4.8 4.8 Volts Volts b. b. 5.3 5.3 voltsvolts c.

c. 6.0 6.0 volts volts d. d. 6.6 6.6 voltsvolts

76. If β

DCDCis increased by 10% is increased by 10% the collector to emitter voltage dropthe collector to emitter voltage drop a. increases by less than or equal to 10%

a. increases by less than or equal to 10% b. decreases by less than or equal to 10% b. decreases by less than or equal to 10% c. increases by more than 10%

c. increases by more than 10% d. decreases by more than 10% d. decreases by more than 10%

77. the small-signal gain of the amplifier v

77. the small-signal gain of the amplifier v_cc /v /v_ss isis a.

a. -10 -10 b.b.

–

5.35.3 c.

c. 5.3 5.3 d. d. 1010

Common Data for Questions 78 & 79. Common Data for Questions 78 & 79. \a regulated power supply shown

\a regulated power supply shown in figure below, has in figure below, has an unregulated input (UR)an unregulated input (UR) of 15 volts and

of 15 volts and generategenerates a res a regulated output Vgulated output V_out_out. Use the component values shown. Use the component values shown in the figure in the figure 6V 6V 1K 1K 12 12 Q1 Q1 24 24 15V (UR) 15V (UR) + + --12 12

In the figure abov

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78. The power dissipation across the transistor Q1 shown in the figure is 78. The power dissipation across the transistor Q1 shown in the figure is a.

a. 4.8 4.8 Watts Watts b. b. 5.0 5.0 WattsWatts c.

c. 5.4 5.4 Watts Watts d. d. 6.0 6.0 WattsWatts

79. If the unregulated voltage increases by 20%

79. If the unregulated voltage increases by 20% the power dissipation acrossthe power dissipation across thethe transistor Q1

transistor Q1 a.

a. increases increases by by 20% 20% b. b. increases increases by by 50%50% c.

c. remains remains unchanged unchanged d. d. decreases decreases by by 20%20%

80. The correct full wave rectifier circuit is 80. The correct full wave rectifier circuit is

81. In a transconductance amplifier it is desirable to 81. In a transconductance amplifier it is desirable to havehave a. a large input resistance and

a. a large input resistance and a large output resistancea large output resistance b. a large input resistance and

b. a large input resistance and a small output resistancea small output resistance c. a small input resistance and

c. a small input resistance and a large output resistancea large output resistance d. a small input resistance and

d. a small input resistance and a small output resistancea small output resistance

GATE- 2007 Two Marks Questions GATE- 2007 Two Marks Questions 82.

82.

The DC current gain (β) of

The DC current gain (β) of a BJT is 50.

a BJT is 50. Assuming that the emitter injection

Assuming that the emitter injection

efficiency is 0.995, the base transport factor

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a.

a. 0.980 0.980 b. b. 0.9850.985 c.

c. 0.990 0.990 d. d. 0.9950.995

83. For the Op-Amp circuit shown in the figure, V 83. For the Op-Amp circuit shown in the figure, V00 isis

1 1 VV 1K 1K 1K 1K 2K 2K 1K 1K a. a. -2V -2V b. b. -1V-1V c. c. -0.5 -0.5 V V d. d. 0.5V0.5V

84. For the BJT circuit shown, assume that

84. For the BJT circuit shown, assume that the β of the transistor is very large and

the β of the transistor is very large and

V

V_BE_BE = 0.7 V. The mode of operation of the BJT is= 0.7 V. The mode of operation of the BJT is

2V 2V 10V 10V + + --+ + --1K 1K 10K 10K a.

a. cut-off cut-off b. b. saturationsaturation c.

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85. In the OP-Amp circuit shown, assume that the diode current follow the 85. In the OP-Amp circuit shown, assume that the diode current follow the equation I=I

equation I=Iss exp (V/Vexp (V/VTT). for V). for Vii = 2V, V= 2V, V00 = v= v0101, and for V, and for Vii = 4 V, V= 4 V, V00 = V= V0202. the. the relationship between V

relationship between V0101 and Vand V0202 isis

2K 2K a. V a. V0202

= √2 V

0101 b. Vb. V0202 = e= e22 VV0101 c. V c. V0202 = V= V0101 In In 2 2 d. d. VV0101

–

VV0202 = V= VTT In 2In 2 86. In the CMOS inverter circuit shown, if

86. In the CMOS inverter circuit shown, if the transconductance parametethe transconductance parameters of rs of thethe NMOS and PMOS transistors are k

NMOS and PMOS transistors are k nn = k = k pp = µ = µ nn CCoxoxWWnn /L /Lnn ==µ µ nn CCoxoxWWpp /L /Lpp = 40 µ = 40 µ A/V

A/V22 and their threshold voltages are Vand their threshold voltages are VTHnTHn= |V= |VTHpTHp| = 1V, the current is| = 1V, the current is

5 V 5 V PMOS PMOS 2.5 V 2.5 V II NMOS NMOS ↓ ↓ a. a. 0A 0A b. b. 25µA25µA c. c. 45 45 µµA A d. d. 90 90 µµAA

87. For the Zener diode shown in the figure, the zener voltage at knee is 7V, the 87. For the Zener diode shown in the figure, the zener voltage at knee is 7V, the

knee current is negligible and the Zener dynamic resistance is

knee current is negligible and the Zener dynamic resistance is 10 Ω. If the

10 Ω. If the input

input

voltage (V

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200 200 a. a. 7.00 7.00 to to 7.29 7.29 V V b. b. 7.14 7.14 to to 7. 7. 29V29V c. c. 7.14 7.14 to to 7. 7. 43 43 V V d. d. 7. 7. 29 29 to to 7. 7. 43 43 VV

Common Data Questions 88, 89, 90 Common Data Questions 88, 89, 90 The figure shows

The figure shows the high-frequency capacitance voltathe high-frequency capacitance voltage (C-V) characteristics of ge (C-V) characteristics of a Metal/SiO

a Metal/SiO22 /silicon (MOS) capacitor having an area of 1 x 10 /silicon (MOS) capacitor having an area of 1 x 10-4-4 cmcm22. assume that. assume that the permitivities

the permitivities

(ε

00

εε

rr) of silicon and SiO) of silicon and SiO22 are 1 x 10are 1 x 10-12-12 F/cm and 3.5 x 10F/cm and 3.5 x 10-13-13F/cmF/cm respectively.

respectively.

88. The gate oxide thickness in the MOS

88. The gate oxide thickness in the MOS capacitor iscapacitor is a.

a. 50 50 mm mm b. 143 b. 143 mmmm c.

c. 350 350 mm mm d. 1µd. 1µmm

89. The maximum depletion layer width in silicon is 89. The maximum depletion layer width in silicon is a.

a. 0.143 0.143 µµm m b. b. 0.857 0.857 µµmm c.

c. 1 1 µµm m d. d. 1.143 1.143 µµmm

90. Consider the following statements about the C-V

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S1: The MOS capacitor has as

S1: The MOS capacitor has as n-type substrate.n-type substrate.

S2: If positive charges are introduced in the oxide, the C-V plot will shift to the S2: If positive charges are introduced in the oxide, the C-V plot will shift to the left.

left.

Then which of the following is true? Then which of the following is true? a.

a. Both Both S1 S1 and and S2 S2 are are true true b. b. S1 S1 is is true true and and S2 S2 is is falsefalse c.

c. S1 S1 is is false false and and S2 S2 is is true true d. d. Both Both S1 S1 and and S2 S2 are are falsefalse

Statement for Linked Answer Questions 91 & 92. Statement for Linked Answer Questions 91 & 92. Consider the Op-Amp circuit shown in the

Consider the Op-Amp circuit shown in the figure.figure.

C C R

R

91. The transfer funct

91. The transfer function Vion V00 (s)/V(s)/Vii(s) is(s) is

a.

a. b.b.

c. d.

92. If V

92. If Vii = V= V11

sin (ωt) and V

00 = V= V22

sin (ωt + φ), then the minimum and maximum

values of φ (in radians)

values of φ (in radians) are respectively

are respectively

a.

–

– π/2 and π/2

π/2 and π/2

b. 0 and π/2

c.

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93. In the following limiter circuit, an input voltage V

93. In the following limiter circuit, an input voltage V_ii = 10 sin 100= 10 sin 100

πt is applied.

Assume that the diode drop is 0.7V when it is forward biased. The zener

Assume that the diode drop is 0.7V when it is forward biased. The zener breakdown voltage is 6.8 V. breakdown voltage is 6.8 V. D1 D1 1K 1K Z Z 6.8V6.8V D2 D2

The maximum and minimum values of the output voltage

The maximum and minimum values of the output voltage respectively arerespectively are a.

a. 6.1 6.1 V, V, - - 0.7 0.7 V V b. b. 0.7 0.7 V, V, -7.5 -7.5 VV c.

c. 7.5 7.5 V, V, - - 0.7 0.7 V V d. d. 7.5 7.5 V, V, - - 7.5 7.5 VV

GATE-2008 Two Marks Questions GATE-2008 Two Marks Questions

94. Consider the following circuit using an ideal

94. Consider the following circuit using an ideal OPAMP. The I-V OPAMP. The I-V characteristiccharacteristicss of the diode is

of the diode is described by the relationdescribed by the relation Where V

Where VTT= 25m V, I= 25m V, I00 = 1µ= 1µ A and V is the voltage across the diode (taken asA and V is the voltage across the diode (taken as positive for forward bias).

positive for forward bias).

=-1V =-1V 100 K 100 K D D ₄_{4 K}_K

For an input voltage V

For an input voltage Vii = -1V, the = -1V, the output voltagoutput voltage Ve V00 isis a.

a. 0 0 V V b. b. 0.1 0.1 VV c.

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95. The OPAMP circuit shown above represents a 95. The OPAMP circuit shown above represents a

C C

L L

a.

a. high high pass pass filter filter b. b. low low pass pass filterfilter c.

c. band band pass pass filter filter d. d. band band reject reject filterfilter 96. Two identical NMOS transistors M1

96. Two identical NMOS transistors M1 and M2 are and M2 are connectedconnected as shown below.as shown below. V

V_bias_bias is chosen so that both transistors are in saturation. The equivalent gis chosen so that both transistors are in saturation. The equivalent g_m_mof theof the

pair

pair is is defined defined to to be be at at constant constant VVoutout..

The equivalent g

The equivalent gmm of the pair isof the pair is a. the sum of individual g

a. the sum of individual gmm

’s of the transistors

b. the product of individual g

b. the product of individual gmm

’s of the transistors

c. nearly equal to the g

c. nearly equal to the gmm of M1of M1 d. nearly equal to g

d. nearly equal to gmm /g /g00 of M2of M2

97. Consider the Schmidt trigger circuit shown below 97. Consider the Schmidt trigger circuit shown below

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1 1 2 2 II_out_out M M ← ← M M bias bias V V

A triangular wave which goes from

–

12V to 12V is applied12V to 12V is applied to the inverting inputto the inverting input of the OPAMP. Assume that the output of the OPAMP swings from +15V to of the OPAMP. Assume that the output of the OPAMP swings from +15V to --15V. the voltage at the non-inverting input switches

15V. the voltage at the non-inverting input switches betweenbetween a.

a. -12V -12V and and +12v +12v b. b. -7.5 -7.5 and and +7.5 +7.5 VV c.

c. -5V -5V and and + + 5V 5V d. d. OV OV and and 5 5 VV

Statement for linked Answer Questions 98 and 99. Statement for linked Answer Questions 98 and 99. In the following transistor circuit, V

In the following transistor circuit, VBEBE= 0.7 V, r= 0.7 V, ree= 25 mV/I= 25 mV/IEE

and β and all

=9V =9V C C c2 c2 20K 20K C C C C 10K 10K 3K 3K E E 2.3K 2.3K E E c1 c1 3K 3K II ↓ ↓

98. The value of DC current I 98. The value of DC current I_E_E isis

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c.

c. 5 5 mA mA d. d. 10 10 mAmA

GATE-2009 Two marks Questions GATE-2009 Two marks Questions 100. In the circuit below,

100. In the circuit below, the diode is ideal. The voltage V is the diode is ideal. The voltage V is given bygiven by + + V-↓ ↓ 1 1 --+ + 1 1 1A 1A a. min (V

a. min (Vii 1) 1) b. b. max max (V(Vii 1)1) c. min (-V

c. min (-V_ii 1) 1) d. d. max max (-V(-V_ii 1)1)

101. A small signal source v

101. A small signal source vii (t) = A cos 20t + B (t) = A cos 20t + B sin 10sin 1066t is applied to a t is applied to a transistortransistor amplifier as shown below. The transistor

amplifier as shown below. The transistor hashas

β = 150 and h

_ie_ie

= 3KΩ. Which

expression best approximates v

expression best approximates v00 (t)?(t)?

(t) (t) 100 K 100 K 3 K3 K 12V 12V 100 nF 100 nF 900K 900K 10 10 (t) (t) 2 200 KK FF a. v

a. v₀₀ (t) = -1500 (A cos 20t + B s(t) = -1500 (A cos 20t + B sin 10in 1066t)t) b. v

b. v00 (t) = -150 (A cos 20t +B sin 10(t) = -150 (A cos 20t +B sin 1066t)t) c. v

c. v00 (t) = -1500 B sin 10(t) = -1500 B sin 1066tt d. v

d. v00 (t) = -150 B sin 10(t) = -150 B sin 1066tt

Common Data for Questions 102 and 103. Common Data for Questions 102 and 103.

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Consider a silicon p-n

Consider a silicon p-n junction at room temperature having the followingjunction at room temperature having the following parameters:

parameters:

Doping on the n-side = 1 x 10

Doping on the n-side = 1 x 101717 cmcm-3-3 Depletion width on the n-side = 0.1 µm Depletion width on the n-side = 0.1 µm Depletion width one the p-side = 1.0 µm Depletion width one the p-side = 1.0 µm Intrinsic carrier concentra

Intrinsic carrier concentration = 1.tion = 1.4 x 104 x 101010 cmcm-3-3 Thermal voltage =26 mV

Thermal voltage =26 mV

Permittivity of free space = 8.85 x 10

Permittivity of free space = 8.85 x 10-14-14 F.cmF.cm-1-1 Dielectric constant of silicon = 12

Dielectric constant of silicon = 12

102. The built-in potential of the junction 102. The built-in potential of the junction a. is 0.70 V a. is 0.70 V b. is 0.76 V b. is 0.76 V c. is 0.82 V c. is 0.82 V

d. cannot be estimated from the

d. cannot be estimated from the data givendata given

103. The peak electric filed in

103. The peak electric filed in the device isthe device is a. 0.15 MV.cm

a. 0.15 MV.cm-1-1, directed from p-region to n-r, directed from p-region to n-regionegion b. 0.15MV. cm

b. 0.15MV. cm-1-1, directed from n-region to p, directed from n-region to p-region-region c. 1.80 MV.cm

c. 1.80 MV.cm-1-1 directed from p-region to n-regiondirected from p-region to n-region d. 1.80 MV. cm

d. 1.80 MV. cm-1-1 directed from n-region to p-regiondirected from n-region to p-region

Statement for Linked Answer Question 104 and 105. Statement for Linked Answer Question 104 and 105. Consider the CMOS circuit shown, where

Consider the CMOS circuit shown, where the gate voltage Vthe gate voltage VGG of the n-MOSFETof the n-MOSFET is increased from zero, while the gate voltage of

is increased from zero, while the gate voltage of the p-MOSFET is kept the p-MOSFET is kept constant atconstant at 3V. Assume that for both transistors, the magnitude of the threshold voltage is 1 V 3V. Assume that for both transistors, the magnitude of the threshold voltage is 1 V

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and the product of

and the product of the transconductance parametethe transconductance parameter and the r and the (W/L) ratio, i.e. the(W/L) ratio, i.e. the quantity µC

quantity µC_ox_ox(W/L). is 1mA. V(W/L). is 1mA. V-2-2..

← ← V V ← ← → → G G 3V 3V 5V 5V

104. For small increase in V

104. For small increase in VGG beyond 1V, which of thebeyond 1V, which of the following gives the correctfollowing gives the correct description of the region of operation of

description of the region of operation of each MOSFET?each MOSFET? a. Both the

a. Both the MOSFETs are in saturation regionMOSFETs are in saturation region b. Both the

b. Both the MOSFETs are in triode regionMOSFETs are in triode region c. n-MOSFET is in

c. n-MOSFET is in triode and p-MOSFET is in triode and p-MOSFET is in saturation regionsaturation region n-MOSFET is in saturation and

n-MOSFET is in saturation and p-MOSFET is in triode regionp-MOSFET is in triode region

105. Estimate the output voltage V

105. Estimate the output voltage V00 for Vfor VGG = 1.5 V, [Hints: use the appropriate= 1.5 V, [Hints: use the appropriate current-voltage equation for each MOSFET, based on the

current-voltage equation for each MOSFET, based on the answer to Q.57]answer to Q.57]

a.

a. b.b.

c. d.

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ANSWERS & EXPLANATIONS ANSWERS & EXPLANATIONS 1. (a) 1. (a) 2. (a) 2. (a) 3. (a) 3. (a) II_C1_C1

= βI

_B_B, , II_E2_E2 = I= I_C1_C1 ii_o_o

≈ βI

_B_B, , VV_ii = I= I_B_B, r, rππ 4. (b) 4. (b) 5. (a) 5. (a) 6. (c) 6. (c) A = 100, A = 100, B= 0.99 B= 0.99 1 + AB = 100 1 + AB = 100

For voltage series R

For voltage series Rii

↑ & R

00

↓ by 1 + AB

-- R

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7. (b) 7. (b) Regulation Regulation O/P Resistance = O/P Resistance = 8. (b) 8. (b) ttrr

x B.ω = 0.35

B.ω =

9. (a) 9. (a)

Common mode gain, Common mode gain, V

V_C_C = A= A_C_C VV_ii (V(V_i1_i1 = V= V_i2_i2 = V= V_ii)) If R

If Ree is infinite then because of symmetry of fig., Vis infinite then because of symmetry of fig., Vccbecomes zero.becomes zero. iie1e1 = i= ie2e2 = 0= 0 ii_b2_b2 < < i< < i_c2_c2 So i So ic2c2~ i~ ie2e2 10. (d) 10. (d)

In positive feedback op-amp act in its

In positive feedback op-amp act in its satuation region ± Vsatuation region ± V_sat_sat. Here applied voltage. Here applied voltage is positive. is positive. V V00 = + V= + Vsatsat = + 15 V= + 15 V 11. (c) 11. (c)

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12. (a) 12. (a)

At low frequency, A

At low frequency, Aii = - h= - hfefe and Aand Aii decreases as frequency increases.decreases as frequency increases.

13. (c) 13. (c) Here Here 14. (d) 14. (d) 15. (a) 15. (a)

This circuit acts as a

This circuit acts as a differentiatordifferentiator and differentiation of triangular wave givesand differentiation of triangular wave gives square wave.

square wave.

16. (b) 16. (b)

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Control Control Gate Gate C C 17. (d) 17. (d) V V_th_th R R R R 430 430 10/3 10/3 c c th th 15V 15V 5V 5V Since

Since

β is large II

β is large

BB

≈ 0, R

thth = 5 || 10= 5 || 10

18. (c) 18. (c) V V₀₀₀₀ = V= V_i0_i0.A = 5 mV x 10,000 = 50 .A = 5 mV x 10,000 = 50 VV But V But V₀₀₀₀ = ± 15V,= ± 15V, V

V0000 can never be greater than ± Vcan never be greater than ± Vsatsat

19. (c) 19. (c)

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h hfefe = g= gmm .r.rππ 22. (b) 22. (b)

(β

00 = h= hfefe)) 23. (C) 23. (C) V V II II II II₁₁ II → → → → ↓ ↓ z z ↓ ↓ C C E E --+ + 20-30V 20-30V B B BE BE 20 20 B B ↓ ↓ R R =10V =10V (i.e. when I (i.e. when I_zz = 0)= 0) IIEE= I= ICC +I+Izz

IIBB = I= Izz(as no current flows in R(as no current flows in RBB))

From (i) I

From (i) I_E_E

= βI

_zz + I+ I_zz= (99 +1) I= (99 +1) I_zz II_E_E= 100 I= 100 I_zz

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II11 = I= IEE= 100 I= 100 Izz

II_zz == P

Pzz = V= VzzIIzz = 9.5 x 0.01 = = 9.5 x 0.01 = 95mW95mW II_cc = 99I= 99I_zz= 99 x 0.01 = 0.99A= 99 x 0.01 = 0.99A P

P_cc = V= V_C_CII_C_C = 10 x 0.99 = 9.9 W= 10 x 0.99 = 9.9 W

24. (b) 24. (b)

Fig shown is Colpitts oscillator. Fig shown is Colpitts oscillator.

25. (b) 25. (b) Av Avf f = - 9= - 9 26. (a) 26. (a)

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+ + --10mH 10mH 100 100 10 10 =10co =10cos (s (100t)100t) 10 10 FF 3 3 1 1 2 2 + + --=10co =10cos (s (100t)100t) 10 10 10mH 10mH 100 100 10 10 1 1 2 2 33 F F KCL at node 1, KCL at node 1, V V00 = -10V= -10V22= -10(-cos 100t)= -10(-cos 100t) V V00 = 10cos 100t= 10cos 100t 27. (c) 27. (c) R

Rii

increases by factor of 1 + Aβ and R

00

decreases by 1+ Aβ.

28. (b) 28. (b)

Gain X B. ω = 1x10

66 20 log x = 20 dB 20 log x = 20 dB X = 10 X = 10 29. (a) 29. (a) f

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For cascaded stage For cascaded stage

30. (c) 30. (c)

Slew rate = A. 2π fV

mm V = A.V

V = A.Vmm

sin ωt

20 log X = 40 20 log X = 40 X = 100 = A X = 100 = A V Vmm = 79. 5 mV= 79. 5 mV 31. (a) 31. (a) 1 1 KCL at node 1 KCL at node 1

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32. (a) 32. (a) Z Z 1 1 → → L L ↓ ↓ z z II L L R R ↓ ↓ ↓ ↓ + + L L II ↑↑ II --(I (Izz + I+ ILL= I= I11)) When V When Vinin = 30 V= 30 V When V When V_in_in = 50 V= 50 V

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R ≤ 3636

33. (d) 33. (d) V VGG = 0, V= 0, Vss = I= IDD .R.Rss = 1 mA x 2.5 K = 2.5 V= 1 mA x 2.5 K = 2.5 V V VGSGS = V= VGG

–

VVss = - 2.5 V= - 2.5 V A

AVV = -g= -gmm RRDD ( because rd is not given, it is taken as( because rd is not given, it is taken as

∞).

= - 2ms x 3K = -6

34. (c) 34. (c) T

T11 is N-MOSFET which conduct when Vis N-MOSFET which conduct when Vii > V> Vthth When VWhen V00= 0, CMOS inverter has= 0, CMOS inverter has I/P = 1 i.e. 5 V So T

I/P = 1 i.e. 5 V So T11 is in saturation and conducts.is in saturation and conducts.

35. (b) 35. (b) 36. (d) 36. (d) 37. (b) 37. (b) 8V 8Vp-pp-p

= 4 sin ω t

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At V At Vii = 2= 2

Another crossover at Another crossover at

Therefore Duty cycle = Therefore Duty cycle =

38. (c) 38. (c) 39. (a) 39. (a)

A= 50, β = 0.2

D =1 + A D =1 + A

β = 1 + 50 x 0.2

β = 1 + 50 x 0.2 = 11

= 11

Current shunt: R

Current shunt: R00 increases & Rincreases & R11 decreases by D.decreases by D.

41. (a) 41. (a) V V_CE_CE = V= V_CC_CC

–

II_C_C RR₂₂ 3 = 6 3 = 6

–

1.5 mA x R1.5 mA x R22 1.5 mA x R 1.5 mA x R22 = 3= 3 R R22

= 2 KΩ

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When β = 200,

II_C_C ==

ββ

_IB_IB(as R(as R₁₁ is same Iis same I_B_B remains same)remains same) = 0.01 mA x 200 = 0.01 mA x 200 IICC = 2 mA= 2 mA V V_CE_CE = V= V_CC_CC

–

II_C_C RR₂₂ = 6-= 6-

2 mA x 2 kΩ

V VCECE = 2V= 2V 42. (a) 42. (a)

Frequency of oscillation for RC phase

Frequency of oscillation for RC phase shift oscillatorshift oscillator isis

43. (c) 43. (c)

As volt at non

As volt at non inverting terminainverting terminal is 3V l is 3V due to zener diode, due to zener diode, voltage at invertingvoltage at inverting terminal will be 3V because of virtual ground.

terminal will be 3V because of virtual ground.

So current in 20K is So current in 20K is 44. (d) 44. (d) 45. (b) 45. (b) V V₀₀ = 6V= 6V 46. (c) 46. (c)

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4 4 250 250 250250 1K 1K --1K 1K + + --+ + 50 50 + + --1K 1K _V_V 50 50 5050 250 250

Volt. Across 1 K after 1

Volt. Across 1 K after 1stst stage =stage =

Similarly Similarly Therefore A Therefore A_V_V = 40 x 40 x 50 = 8 x 10= 40 x 40 x 50 = 8 x 1044 A A_V_V in dB = 20 log (8 x 10in dB = 20 log (8 x 1044) = 98 dB) = 98 dB 47. (d) 47. (d) I = 3mA I = 3mA 50. (a) 50. (a)

At ω = ∞,

& at& at

ω = 0

51. (a) 51. (a)

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V VCECE = V= VCCCC-I-ICCRRCC 0.2 = 3-I 0.2 = 3-I_C_C x 1 Kx 1 K IICC = 2.8 mA= 2.8 mA 52. (d) 52. (d) h hfefe = g= gmm. r. rππ, h, hfefe

= β

53. (a) 53. (a) ← ← C C 1K 1K ↓ ↓ ↓ ↓ 2.1K 2.1K 1K 1K 1K 1K C C R= 1K R= 1K

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For oscillation imaginary part is zero. For oscillation imaginary part is zero.

i.e. i.e.

ω

22 C C22RR22

–

1 = 01 = 0 54. (a) 54. (a) 1K 1K

↓↓

ii V V L L

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…..(i)

….. (ii)

Putting V

Putting V00 from (1)from (1)

55. (d) 55. (d)

When I

When I_L_L= 100 mA,= 100 mA,

When I

When I_L_L= 500mA= 500mA,,

Therefore R= 14

Ω (choosing minimum one)

56. (b) 56. (b)

57. (d) 57. (d)

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58. (b) 58. (b) 59 (b) 59 (b) 60. (c) 60. (c)

When two terminals of a transistor are

When two terminals of a transistor are shorted it acts as shorted it acts as diode.diode.

61. (c) 61. (c) B1 B1 1M1M ↓ ↓ II II 1M 1M B2 B2 ↑ ↑ 0 0 + + --e e V

V11 = - I= - IB1B1 x 1M, Vx 1M, V22 = V= V11 = - I= - IB1B1 x 1M (due x 1M (due to virtual ground)to virtual ground) Drop in feedback resistor 1M = I

Drop in feedback resistor 1M = IB2B2 x 1Mx 1M ee₀₀ = V= V₂₂ + I+ I_B2_B2 x 1Mx 1M

ee₀₀ = - I= - I_B1_B1 x 1M + Ix 1M + I_B2_B2 x 1Mx 1M ee00 = (I= (IB2B2

–

IIB1B1) x 1M) x 1M

where (I

where (IB2B2- I- IB1B1) is offset current) is offset current

62. (a) 62. (a)

Since O/P is taken across 10K it is a high pass filter. I/P is at non

Since O/P is taken across 10K it is a high pass filter. I/P is at non -inverting point.-inverting point. So,

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63. (d) 63. (d)

Only common mode gain depends on R

Only common mode gain depends on REEand differential mode gain is and differential mode gain is independentindependent of R

of R_E_E..

64. (c) 64. (c)

From the graph its clear that V

From the graph its clear that Vthth = 1V= 1V V

V_Gs_Gs = 3-1 = 2V= 3-1 = 2V V

V_DS_DS = 5-1= 4V= 5-1= 4V Since V

Since V_Ds_Ds

≥ V

_GS_GS

–

VV_T_T S. MOSFET is in saturation regS. MOSFET is in saturation region.ion. 65. (b)

65. (b)

II_E_E= I= I_C_C + I+ I_B_B

= β

_IB_IB+I+I_B_B

= (β+ 1)I

_B_B KVL in I/P loop gives,

KVL in I/P loop gives, V VCCCC

–

VVBEBE = I= IBBRRBB + I+ IEE RREE = I= IBB RRBB

+ (β+1) I

BB RREE II_B_B = 40 µA= 40 µA II_C_C

= β = 50 x 40

= β = 50 x 40 µA = 2000

µA = 2000

µµ A = 2 mA = 2 mAA V VCC = V= VCCCC- I- ICCRRCC = 20-2 mA X 2K= 20-2 mA X 2K V V_C_C = 16 V= 16 V 66. (a) 66. (a) → → →→ 20-30V 20-30V 5.8V 5.8V II II _L_L ↓ ↓ II 1K 1K Load Load 1 1 z z

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V

V_L_L

= ‘5.8 V

Maximum load current will be when V

Maximum load current will be when V₁₁ = V= V_max_max 24.2mA = I 24.2mA = ILL+ I+ Izz II_L_L= 24.2 mA= 24.2 mA

–

0.5 mA = 23.7 mA0.5 mA = 23.7 mA 67. (b) 67. (b) V Vutut

= β

uu VVsatsat

When lower diode is ON, When lower diode is ON,

V

Vιtιt = -= -

ββ

ιι VVsatsat

(when upper diode

(when upper diode is ON, β

is ON, β

ιι ==

V

Vutut & V& Vιtιt are upper and lower transition voltage.are upper and lower transition voltage.

68. (b) 68. (b) Z Zinin

= 2 MΩ

Z Z00 = r= rdd || R|| RDD = 20 K || 2 K= 20 K || 2 K 69. (a) 69. (a)

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IIDD = 10 mA x= 10 mA x V V_DS_DS = V= V_DD_DD

–

II_D_D RR_D_D = 20- 5.625 mA x 2 K= 20- 5.625 mA x 2 K V VDSDS = 8. 75 V= 8. 75 V 70. (b) 70. (b) G Gmm = 1.875 ms= 1.875 ms A AVV = - g= - gmm (r(rdd || R|| RDD) (g) (gmm ZZ00)) A AVV = - 3.41= - 3.41 72. (d) 72. (d)

From the graph it is clear that

From the graph it is clear that as Vas VGSGS increase conductance i.e. slope increase conductance i.e. slope of graphof graph increase. increase. )) GS GS 0 0 D D = = → → ↑ ↑II V V -6V -6V 12mA 12mA (Z (Z

Transfer character of n-channel D

Transfer character of n-channel D-MOSFET-MOSFET

73. (d) 73. (d)

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--10V 10V + + 10V 10V 1 1 F F 1K 1K 1 1 Applying KCL at node 1 Applying KCL at node 1 74. (b) 74. (b)

Zener diode works as normal diode in FB. So, when V

Zener diode works as normal diode in FB. So, when Vinin < 0, V< 0, VRR = V= Vinin When 0 <When 0 < V

Vinin < 6, Diode is OFF and V< 6, Diode is OFF and VRR = 0.= 0. When V

When V_in_in > 6, Diode conducts and V> 6, Diode conducts and V_R_R = V= V_in_in

75. (c) 75. (c)

Applying KVL in base-emitter loop, Applying KVL in base-emitter loop, 12-I 12-IEERRCC