Engr 303
Digital Logic Design
LAB 6 Sequential Logic: Latches and Flip-Flops
You will implement designs for latches and flip-flops..
Deliverables:
0) nSnR Latch
1) nSnR Latch with Control 2) D-Latch with Control 3) D-Flip-Flop
Demonstration Requirement:
You must demonstrate on the DE2 board the D-Flip-Flop from the last part of this lab.
Part 0 – nSnR Latch
In lectrure we introduced the Set Reset Latch using two NOR gates connected with feedback as shown below. The inputs Set and Reset are active high meaning they Set or Reset the Q output, respectively, when at a high (logic 1) level.
In the lab we will use the DE2 development board to test our latch design using the push buttons on the board. The pushbuttons are normally high and present a low level (logic 0) when pressed. To
accommodate the DE2 board we need to redesign the SRLatch to work with active low inputs. Using DeMorgan’s thereom we translate the circuit as shown using two NAND gates. We will refer to this as a notSet (nS) notReset (nR) Latch.
nSnR Latch Design
S R nS nR Q nQ
0 0 1 1 Qprev nQprev Hold Previous State
0 1 1 0 0 1 Reset Q=0
1 0 0 1 1 0 Set Q=1
nSnR Latch
Verify that Q behaves properly by simulating the design and comparing to the truthtable. If you test this on the DE2 board, use the pushbuttons and NOT the slide switch for Set and Reset. The pushbuttons are debounced to prevent multiple transitions from resulting in indeterminant behavior. The pushbuttons on the DE2 board are spring loaded normally HIGH. They go to low (zero) when you press them.
Testing:
nS & nR are both active low in this design. So your test should push nS momentary low then back to high. Then push nR momentarily low then back to high. Verify that Q and nQ behave properly as shown. Your waveform should look like the one shown below. Note it takes about 5ns for these NAND gates to switch, so at this timescale (grid size = 10nS) you can see the propagation delay between inputs and outputs. It is informative to see this delay, but for future testing you would probably want to use a larger timescale so that it is easier to read. Note that when both inputs are low, the output does not make sense (an invalid state).
nSnR Latch Waveform
ENGR303
Part 1 – nSnR Latch with Control
Build and verify the following nSnR Latch with Control shown below. Suggested project name “nSnRLatchwControl”
The bubbles on the input signals at the NAND gates basically make this circuit into a nSnR latch. Otherwise it would be an SR latch. The bubbles are there to make testing on the DE2 device easier, because our DE2 devices have pushbuttons that are normally high. In Quartus, use a NOT gate inplace of a bubble for the inputs nS and nR to the NAND gates.
S R nS nR C Q nQ
0 0 1 1 1 Qprev nQprev Hold Previous
State
0 1 1 0 1 0 1 Reset Q=0
1 0 0 1 1 1 0 Set Q=1
1 1 0 0 1 0 0 Invalid Q=nQ
X X X X 0 Qprev nQprev Disables Latch
nSnRLatchwControl Truth Table
To SET: Push nS momentary low then back to high. To RESET: Push nR momentarily low and back to high.
CONTROL: nS and nR will be ignored unless C is high. Test in both conditions.
Verify that Q behaves properly. If you test this on the DE2 board, use the pushbuttons for Set and Reset. The pushbuttons on the DE2 board are normally HIGH. Use a toggleswitch for Control.
nR
C
nS
nQ
Q
Si
Ri
nSnR Latch with Control
Testing:
nS & nR are both active LOW in this design. So your test should make nS momentary low then back to high. Then make R momentarily low then back to high. Verify that Q and nQ behave properly. Test all four states of nS and nR with Control set to 1, then test with Control set to 0 as shown.
Part 2 – D-Latch with Control
Build and verify the following D-Latch with Control shown below. Note: Dlatch is a reserved word in Quartus, use another name for your project. Suggested project name “Dlatch303”
A D-Latch basically ensures that S and R always have opposite values. These values “flip together” so they are either (0, 1) or (1, 0), causing the latch to set or reset, respectively, and preventing an invalid state (1, 1). The control signal performs the same function as in the previous circuit, causing the input to be ignored unless C is high.
D C Q nQ
0 1 0 1 Reset Q=0
1 1 1 0 Set Q=1
X 0 Qprev nQprev Disables Latch
D-Latch with Control Truth Table
The net effect of this design is “Q follows D when control is high.” Verify this behavior. If you test this on the DE2 board, use toggle switches for D and C.
C
D
nQ
Q
Si
Ri
D-Latch with Control
Testing:
Here is a decent waveform for testing. “Q follows D when control is high.”
D-Latch with Control Waveform
Part 3 – D-Flip-Flop
Build a D-Flip Flop by combining an SR Latch with Control, and a D-Latch with Control in a master-slave configuration as shown. This configuration will require a heirarchical design using a top level project with references to sub-projects. Suggested project name “DFlipFlop303”.
Remember to set Project Library references and export the Block Symbol files from part 1 and part 2 of this lab.
The net effect of this particular design is “Q samples D on the negative clock edge”.
Negative Edge Triggered D-Flip Flop
Testing a D Flip-Flop:
flops are “edge triggered” which means that Q samples D on the clock edge. This particular D Flip-flop is a “negative edge” design, which means “Q samples D on the negative clock edge”. In reality, because of propagation delay, the D input value needs to be stable for a short time after the clock edge. To test this, the D input needs to straddle the negative clock edge. So for waveform testing you will need to set up a 100ns clock period on your waveform. To do this you set the count on Clock to
increment by 1 every 50ns. Then make some D input values that “straddle” both sides of the clock edge as shown below.
Here is a decent test waveform.
D-Flip Flop Waveform
DE2 Board testing pin assignment:
