Xiaofeng Lin
, Member, IEEE
, Jin Liu
, Member, IEEE
, Hoi Lee
, Member, IEEE
, and Hao Liu
, Student Member, IEEE
Abstract—This paper presents an adaptive finite impulse re-sponse (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25- m process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adap-tation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method as on-chip error detector. Measurement results show that the proposed adaptive equalizer achieves over 75% horizontal eye opening when the channel loss at the half-data-rate frequency varies from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s data rate, the equalizer achieves 68% horizontal eye opening when the channel loss is about 9.3 dB at the half-data-rate frequency. The adaptive equalizer including the FIR filter and the error detector occupies 0.095 mm2 die area and dissipates 95 mW at 2.5-Gb/s data rate from 2.5-V voltage supply.
Index Terms—Adaptive equalizers, CMOS analog integrated circuits, continuous time filters, data communication.
I. INTRODUCTION
I
N HIGH-SPEED data communications with data rates over 1 Gb/s, receiver equalization has become an essential building block to mitigate the inter-symbol interference (ISI) problem, which is due to limited bandwidth of low cost channel materials. Several equalization methods have been developed. The passiveRLC high-pass filter [1] is a very low-power and efficient method, but, has little flexibility for adaptation. On the other hand, weighted parallel or serial combinations of analog active filters [2]–[10] offer low-power and area-efficient solutions. A differential pair with either source degeneration capacitor and/or passive load inductors is usually used to realize an active high-pass filter. Another approach is to use finite im-pulse response (FIR) filters, which offer wide ranges of transfer functions digitally adjustable by tap coefficients. Digital FIR filters have been widely used for equalization when data rates are below 1 Gb/s. Nevertheless, digital FIR filtering requires a high-speed data converter. An alternative technique is to use sample and hold circuits (S&H) as the tap delay line [11]–[16]Manuscript received December 5, 2005; revised March 3, 2006.
X. Lin is with Texas Instruments Incorporated, Dallas, TX 75243 USA (e-mail: [email protected]).
J. Liu, H. Lee, and H. Liu are with the Department of Electrical Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, Richardson, TX 75083-0688 USA (e-mail: [email protected]; [email protected]; [email protected]).
Digital Object Identifier 10.1109/JSSC.2006.875302
to achieve several hundreds of Mb/s rate. Time interleaved structure of parallel S&H cells with different sampling phases can be used to further improve the data throughput to several Gb/s [17]–[24]. Decision feedback equalizers (DFE) [25]–[31] use tap delay line as well, however, since the input signal of the delay line is one bit digital signal, it is much simpler than the delay line used in feedforward FIR equalizer. In the latter case, the input signal to the delay line is the received signal, which is generally treated as an analog signal due to ISI. The major issue with the DFE is the time constraints for the decision feedback loop [32]. In addition, the DFE is part of the CDR loop. If the ISI is severe, the received signal quality is poor, and the clock and data recovery circuits tend to fail together. In recent years, FIR filter with passive inductor delay line [33]–[36] achieves up to 40-Gb/s data rate. However, the use of on-chip inductors in the tap delay line consumes large die area. To improve the area efficiency, analog active tap delay line without inductors looks attractive [37], [38]. However, since the group delay of an active delay stage is related with the bandwidth, symbol-rate delay usually cannot offer enough bandwidth. A fractionally spaced FIR equalizer using an active inductor-less tap delay line has been developed [39] to improve the delay line bandwidth above 1 GHz from several hundreds of megahertz. However, the bandwidth of the delay line is still limited by multiple poles in each current-mirror based delay unit.
In this paper, inverter-based tap delay with active-in-ductor-load (INV-AIL) [40] is proposed for the fractionally spaced equalizer (FSE). With the proposed delay line, an additional zero is introduced by an active inductor load in each delay cell compared with the previous design [39]. Therefore, the speed of the equalizer has been enhanced to 3.5 Gb/s from 1 Gb/s. In addition, close-loop adaptation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method [41] as on-chip error detector. The paper is organized as follows. Section II will discuss the circuit design of the FIR filter, while Section III will describe the adaptation issues of the equalizer. The experi-mental results and conclusion are presented in Sections IV and V, respectively.
II. CIRCUITDESIGN OF THEFIR FILTER A. FIR Filter Architecture
In this design, a fractionally spaced FIR equalizer is used; each tap delay provides a delay of 1/4 symbol period. The frac-tionally spaced delay line provides wider bandwidth compared 0018-9200/$20.00 © 2006 IEEE
LINet al.: ADAPTIVE FIR EQUALIZER WITH CONTINUOUS-TIME WIDE-BANDWIDTH DELAY LINE IN 0.25- m CMOS 1909
Fig. 1. Block diagram of the proposed four-tap FIR filter.
with symbol rate delay line [39]. Fig. 1 shows the block dia-gram of the proposed four-tap fractionally spaced FIR filter. It consists of three delay stages, plus one dummy delay at the end of the delay line to provide similar load for the previous stage. The delay cells in front of the tap delay line are for DC biasing purpose, which will be explained in detail in Section II-B. The multiplying digital-to-analog (D/A) converters (MDAC) serve as multipliers. The current outputs of the MDACs are directly connected together to sum the current. Then, the differential cur-rent signals are converted to voltage signals through the load resistors. A common-mode feedback circuit (CMFB) tunes two pairs of current sources to set the output common-mode voltage. The last stage of the filter is a limiting amplifier.
B. Tap Delay
The previous 1-Gb/s filter design [39] used a current mirror with a current-mode second-order biquad as delay cells, as well as fractionally spaced delay to increase the bandwidth of the delay line. However, the multiple poles reduce the bandwidth of the delay line. In this design, an inverter with an active inductor load is proposed as a delay cell to enhance the bandwidth of the delay line. As a result, for the same CMOS 0.25- m process, the speed of the equalizer has been greatly enhanced to 3.5 Gb/s from 1 Gb/s. In this design, each tap delay consists of four delay cells; the dummy delay stage shown in Fig. 1 is also realized by a delay cell.
Fig. 2 shows the schematic of a delay cell; it is composed of an inverter with active inductor load (INV-AIL). The tran-sistors MN2 and MP2 provide low resistive load. As a result, the delay cell has a small voltage gain (designed to be close to unity), and does not function as a high-gain inverter. This is il-lustrated by the DC voltage transfer function of the delay cell in Fig. 3. The dotted line with unity slope is for comparison of linearity with the voltage transfer curve in the solid line. It also shows that the input and output swing ranges are from 0.8 V to 1.7 V. Within this wide range, the delay cell provides close to unity small-signal gain. The transistors MP3 and MN3 in the gate connection of MN2 and MP2 realize two active inductors to increase the bandwidth of the delay cell. The inverter with com-plementary MP1 and MN1 provides better linearity and wider
Fig. 2. INV-AIL delay cell.
Fig. 3. Large-signal voltage transfer function of the INV-AIL delay cell. input common mode range, compared with a single-transistor inverting amplifier. In this design, the common-mode level is set by shorting the output of a delay cell with its input. In addition, on-chip bias helps to reduce the capacitance and impedance dis-continuity on the signal transmission path.
Fig. 4 shows the small-signal model of the delay cell, where , , , and are the transconductance of the transistors MN1, MP1, MN2, and MP2, respectively.
Fig. 4. Small-signal model of the INV-AIL delay cell.
and are the gate capacitors of transistors MN2 and MP2, respectively. and are the channel resistors of MP3 and MN3, which work in the deep triode region. is the total channel conductance of MN1, MP1, MN2, and MP2, and is the load capacitance, which equals to the input capacitance of next delay stage. From small-signal analysis, the voltage transfer function is as follows:
(1) The low-frequency gain is
, where can be ignored in the denominator. We define as the average
of and , and as the average of and .
Since it is desired to have unit gain for each tap delay, the design requires the following equation to be satisfied:
(2) Further, in order to simplify the analysis, we assume the following condition and define a new term to represent
and :
(3) As a result, the transfer function of the delay cell is approxi-mated as follows:
(4) This equation shows that the non-zero channel resistance of MN3 and MP3 introduces a zero to the transfer function. When , which is equivalent to the case when the gates of MN2 and MP2 are open and both transistors turn off, the transfer
function changes into . This is
the transfer function of a simple inverter. When , which is equivalent to the case when the gates of MN2 and MP2 are shorted and both transistors work as active resistors, the transfer function changes into
. This is the transfer function of unit gain first-order low-pass filter.
Further, as the is mainly the gate capacitor of the next stage and a unit-gain delay cell required (2) to be satisfied, we have
(5)
Replacing (5) into (4), the voltage transfer function becomes
(6)
where can be ignored in the denominator. This transfer func-tion has one zero, , and two poles, and , as follows:
(7) (8) (9) The zero in the numerator helps improve the bandwidth. Since the factor in the denominator is , the rela-tionship between and also affects the transfer function. Fig. 5 shows the transfer function with normalized and values. As increases, the increased factor enhances the bandwidth. Also shown in the figure is the transfer function without the zero for the case of . Without the zero, the bandwidth is significantly smaller.
The circuits were designed in CMOS 0.25- m technologies and simulated using Cadence Spectre. The simulation result of one tap delay stage, shown in Fig. 6(a), illustrates that the zero introduces a peak and the 3 dB bandwidth is around 4 GHz. Fig. 6(b) is the group delay response of one tap delay stage. Fig. 7 presents the tap delayed waveforms from simulation. Tap 1 is the input data to the delay line, Tap 2, Tap 3, and Tap 4 are the delayed waveforms after one-, two-, and three-stage tap delay. Because of the peaking in the transfer function, the amplitude of the tap delay signal increases with the number of tap delay stages. The amount of delay of each stage is approx-imately 100 ps, as shown in the plot. Here, the input signal is a data waveform, instead of a sinusoidal waveform. Delaying a data waveform is more difficult than delaying a sinusoidal waveform, since a data waveform has a richer spectrum up to symbol rate frequency and a sinusoidal waveform has a single frequency.
The group delay of the delay cell can be adjusted by the gate voltages of MN3 and MP3. In this design, the gate of MN3 is connected to and the gate of MP3 is connected to Gnd. As mentioned above, cascading of such four delay cells provides
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Fig. 5. Bandwidth enhancement.
Fig. 6. Simulated (a) bandwidth and (b) group delay of one tap delay stage.
approximately 100 ps time delay from simulation. Since the FIR filter is fractionally spaced, some variation of the tap delay does not change the filter transfer function significantly within the signal bandwidth of interest. This is illustrated in Fig. 8. The dotted curve represents the data spectrum. For symbol period of , the first null of the data spectrum is . Most of
Fig. 7. Tap delayed waveforms: Tap 1 is the input signal of the tap delay line, Tap 2, Tap 3, and Tap 4 are the delayed signals after one-, two-, and three-stage of tap delay.
Fig. 8. Effect of tap delay variation on the transfer functions of fractionally spaced equalizers.
the data signal power is below this frequency. The solid curve represents the transfer function of the FSE. The FSE shown on the top plot is spaced, thus, the tap delay . Correspondingly, the transfer function of the FSE has an
effec-tive sampling frequency of . The FSE
transfer function folds at half of . The bottom plot shows an additional FSE transfer function when the tap delay deviates from the desired , specifically, . As a re-sult, the effective sampling frequency is higher than four times the data bandwidth, and the transfer function is stretched out. However, due to over-sampling, the FSE transfer function within the signal bandwidth does not change significantly. In addition, this change can be compensated by adjustment of tap coefficients.
Fig. 9. The 4-bit MDAC. C. Multiplier
The multiplier is implemented by an MDAC. Fig. 9 shows the schematics of the MDAC and the encoder of a tap coeffi-cient. The MDAC multiplies the tap delayed signal, “In”, with the tap coefficients represented by digital bits. In this design, each coefficient has 4 bits, the MSB is a sign bit which directs the output signal of MDAC to the positive output port “outa” or the negative port “outb”, as shown by the encoder block. Other three bits set the gain of the MDAC. The transistors whose gates are connected to the coefficients are connected as cas-cade switches above the transistors whose gates are controlled by the “In” signal. This topology prevents the signal in “outa” and “outb” from coupling to the input though gate-drain capaci-tance. Since the input signal is also the input of next delay stage, such coupling deteriorates the quality of the equalized signal. The sources of the input devices are connected to the ground di-rectly, thus, the input gate capacitances are independent of the MDAC coefficients. The load capacitance at the MDAC output node increases with the number of MDACs (or the number of taps), which limits the bandwidth of the FIR filter. Fig. 10 shows a simulation result on the linearity of the MDAC. The differen-tial output signal between “outa” and “outb” is the product of the input signal, “In”, and the tap coefficients. Here, three LSBs are used, since the MSB is a sign bit. There is minor saturation when the input level is close to either ends of 0.8 V and 1.7 V. D. Common-Mode Feedback Circuit and Limiting Amplifier
A CMFB circuit, shown in Fig. 11, sets the common-mode voltage level at the output of the MDAC. The differential am-plifier composed of M1 to M4 controls the upper bypass current sources, M9 and M10, and the differential amplifier composed of M5 to M8 controls the lower bypass current sources, M11 and M12. To prevent current flowing directly through upper and lower current sources, the input of M5 is connected to VP, in-stead of the output common voltage, . When the level
Fig. 10. Linearity of the MDAC.
is near power supply, VP is high and turns off the upper bypass current sources, while the lower bypass current sources are on. On the other hand, when the output common-mode voltage level decreases toward the ground, VP drops and causes VN to drop as well. As a result, the lower bypass current sources are shut off, while the upper bypass current sources are turned on. In ad-dition, different reference voltages, Vrefa and Vrefb, are used to further reduce the overlapping area when the two bypass current sources are turned on. In order to turn off M11 and M12 when M9 and M10 are on, the reference voltage of the M5–M6 pair, Vrefb, is set to be higher than , where is the threshold voltage of M9 and M10. As a result, when M9 and M10 are turned on or VP is lower than , VN is low to turn off M11–M12. Fig. 12 shows the schematics of the limiting amplifier, which is the same topology as that used in [39].
III. ADAPTATION
Fig. 13 illustrates the three essential blocks of an adaptive FIR equalizer—the FIR filter, the error detector, and the
adapta-LINet al.: ADAPTIVE FIR EQUALIZER WITH CONTINUOUS-TIME WIDE-BANDWIDTH DELAY LINE IN 0.25- m CMOS 1913
Fig. 11. Common-mode feedback circuit.
Fig. 12. Limiting amplifier.
Fig. 13. Block diagram of an adaptive equalizer.
tion controller. The error detector generates an error signal (cost function) such that when the error is minimized, the equalized signal has wide open eyes with low bit error rate (BER). Based on the error signal, the adaptation controller generates a set of coefficients for the FIR filter.
Fig. 14 shows the block diagram of the error detector using pulse extraction method [41]. The pulse extraction circuit is composed of a symbol period delay unit, an inverter and anAND gate. It extracts a pulse for every rising edge of the input signal A. The DC component of the pulse extractor output, signal B, is the weighted integration of the input signal power spectrum; the weight factor is equivalent to a bandpass filter bank [41]. Com-paring the power spectrum of the equalized signal with a ref-erence signal using the pulse extraction method generates the error signal. It is not necessary for the reference signal to be the same as the original transmitted data, neither is it necessary
Fig. 14. Block diagram of the error detector using pulse extraction.
for the reference signal to be synchronized with the received signal. The reason is that the error is the spectrum difference of the equalized signal and the reference signal. As a result, the reference signal can be locally generated as long as it has the same power spectrum as the originally transmitted data. This is usually readily available in a transceiver.
The adaptation part is not in the critical signal path, thus, the speed requirement is relaxed and the power consumption is lower. Based on the error signal, the adaptation controller gen-erates the tap coefficients using generic search algorithms, such as random weight change algorithm [42] or serial perturbation algorithm [43]. Generally, the influences of the tap coefficients to the FIR filter frequency response are not orthogonal, which could lead to multiple local minimum points in the error space of the frequency spectrum. In this design, the four coefficients are limited to a fixed pattern to ensure conver-gence of the tuning process. The first tap is always the inverse to the fourth tap and the third tap remains zero. Such pattern results in only one global minimum point to guarantee conver-gence of the tuning process [41]. In addition, this also reduces the complexity of the adaptation controller. In this design, each tap provides a delay of 1/4 symbol period. Thus, the first and fourth tap coefficients, and , mainly define the high fre-quency response around the signal bandwidth, while mainly sets the DC and low-frequency responses.
This pattern deviates from the normal linear phase FIR filter, which requires the coefficient pattern of . The frequency magnitude responses of FIR filters with these two pat-terns are compared in Fig. 15, specifically one set of coefficients
Fig. 15. Frequency responses of FIR filters with coefficients[7 3 0 0 7]and [7 3 0 3 0 7], and a typical channel transfer function.
Fig. 16. Comparison of the equalized signals by filters with coefficients [7 3 0 0 7]and[7 3 0 3 0 7].
is and the other set is . Also shown in the figure is the frequency response of a typical PCB trace channel. Although the linear phase pattern has a linear phase or constant group delay, it also results in zero amplitude response at DC frequency since the sum of the coefficient equal to zero. From the attenuation curve of the transmission channel, due to its ex-ponential attenuation relationship with frequency, the low-fre-quency components suffer very little loss. As a result, a DC zero of a linear phase filter overly attenuates low-frequency compo-nents and distorts the equalized waveform. This is illustrated in Fig. 16, which compares the equalized waveforms by the two FIR filters. The dotted line is for the linear phase equalizer and the solid line is for the equalizer with the proposed pattern. The arrows identify locations where the low-frequency components are overly attenuated. In the case of first arrow from the left, the equalizer with the proposed coefficient pattern recovers several consecutive zeros. While the linear phase equalizer overly atten-uates the low-frequency components in these consecutive zeros and distorts the waveform from the desired shape. In addition,
Fig. 17. Adaptation procedure.
this also causes timing jitter as indicated around the threshold level.
Fig. 17 shows the adaptation process used in this equalizer. The process starts with setting initial condition and calculating the spectrum information of a reference signal, Spec , and spectrum information of the equalized signal, Spec . These two values are generated from the error detector using pulse extractor followed by a low-pass filter. In each tuning period, the error detector computes the absolute difference between the spectrum information of the equalized signal and the reference signal. The error signal is first compared with a preset toler-ance value, . If it is smaller than the tolerance value, the adaptation process stops, otherwise it will continue. The next step is to compare the current calculated error, Error_curr, with the error calculated in the previous period, Error_prev. If the current error is smaller than the previous one, it is changed in the same direction (i.e., the status is unchanged). If the current error is larger, the status is updated by status status . With the pre-fixed coefficients pattern, there are only two co-efficients need to be updated. As a result, there are in total four statuses, corresponding to the increasing and decreasing of two taps. When the status equals 5, it is set back to 1. This process repeats until the error is smaller than the tolerance value.
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Fig. 18. Chip micrograph.
Fig. 19. Test setup.
Fig. 20. Measured S21 parameters of PCB traces. IV. MEASUREMENTRESULTS
The adaptive equalizer was fabricated in a standard CMOS 0.25- m process with single-poly, six-metal, and N-well tech-nologies. Fig. 18 shows the chip micrograph with dimensions. The die size of the FIR filter is 0.085 mm . The error detector, including a pulse extraction circuit and a low-pass RC filter, occupies 0.01 mm . Fig. 19 shows the setup used to test the equalizer. An Anritsu pulse pattern generator MP1763B gener-ates a differential 2 1 pseudo random bit sequence (PRBS) as the transmitted data. The channel includes custom fabri-cated PCB trace (FR4 material) composed of two differential microstrip transmission lines with characteristic impedance of 50 , coaxial cables, and SMA connectors. The received signal is AC-coupled to the FIR filter. To test the adaptation perfor-mance of the adaptive equalizer, the length of the PCB trace is
Fig. 21. Tuning process of the 2.5-Gb/s adaptive equalizer for the 80-inch PCB trace.
Fig. 22. Measured eye diagrams of (a) the received signal and (b) the equalized signal for 2.5-Gb/s data transmission over the 80-inch PCB trace.
varied from 20 to 120 inches. The measured S21 parameters of the differential PCB traces with different lengths are plotted in Fig. 20. The adaptation controller is implemented using FPGA to allow flexibility for evaluating different search algorithms. The reference spectrum, Spec , was calculated by passing a random sequence through an on-chip pulse extraction followed by a low-pass filter. The BER is measured with Anritsu error detector MP1764A and the eye diagram is measured with a Tektronix 20GS/s digital phosphor oscilloscope.
Fig. 21 shows the adaptation process of the equalizer for 80-inch PCB trace. The channel attenuation for 80-inch PCB trace is about 12 dB at the half-data-rate frequency of 1.25 GHz. After four iterations, the absolute error drops to a significantly
Fig. 23. Measured (a) horizontal and (b) vertical eye openings of the signals be-fore and after equalization for 2.5-Gb/s data transmission over various channel lengths.
Fig. 24. Transfer function of the adapted equalizers for different PCB channels. small value. Fig. 22 shows the measured eye diagrams of the received signal and the equalized signal; the voltage scale for both plots is 100 mV per unit. While the eye diagram of the received signal is totally closed, the equalized eye has about 80% horizontal opening and 65% vertical opening area to achieve BER of less than 10 . Fig. 23 shows the measured horizontal and vertical eye openings of the received and equal-ized signals as the channel length is varied from 10 inches to 120 inches at 2.5-Gb/s data rate. This shows that the equalizer can achieve over 75% horizontal eye opening at 2.5-Gb/s data
Fig. 25. Measured eye diagrams of (a) the received signal and (b) the equalized signal for 3-Gb/s data transmission over the 80-inch PCB trace.
rate when the channel attenuation varies from 4 dB to 21 dB at the half-data-rate frequency of 1.25 GHz. The compensation range can be increased by increasing the number of taps and the number of bits in each tap.
To compare the equalizer gains after adaptation to different PCB channels, we used the actual tap coefficients achieved after adaptation to draw a group of equalizer transfer func-tions in Matlab as shown in Fig. 24. According to the design specification and circuit simulation results, the equalizer is a spaced equalizer. Therefore, the sampling frequency for 2.5-Gb/s data rate is 10 GHz. Thus, the transfer function folds at 5 GHz. If the actual tap delay deviates from the ex-pected value, the actual transfer function will be stretched or compressed as illustrated in Fig. 8. The gains of these equalizer transfer functions shown in Fig. 24 match well with the channel attenuation characteristics shown in Fig. 20. This verifies that the adaptation process is successful.
We also test the performance of the equalizer at 3-Gb/s and 3.5-Gb/s data rate. Fig. 25 shows the measured results com-paring the eye diagrams of the received and the equalized sig-nals at 3 Gb/s over an 80-inch PCB trace channel. While the eye diagram of the received signal after the 80-inch PCB trace is completely closed, the equalized signal has about 72% hori-zontal eye opening and 63% vertical eye opening. The channel attenuation for the 80-inch PCB trace is about 15 dB at the half-data-rate frequency of 1.5 GHz. Fig. 26 shows the mea-sured results at 3.5-Gb/s data rate over a 40-inch PCB trace channel. The channel attenuation for the 40-inch PCB trace is
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Fig. 26. Measured eye diagrams of (a) the received signal and (b) the equalized signal for 3.5-Gb/s data transmission over the 40-inch PCB trace.
TABLE I PERFORMANCESUMMARY
about 9.3 dB at the half-data-rate frequency of 1.75 GHz. The received signal has completely closed eyes and the equalized signal has about 68% horizontal eye opening and 45% vertical eye opening. Table I summarizes the performance of the adap-tive equalizer.
V. CONCLUSION
This paper has presented an adaptive FIR equalizer with con-tinuous-time wide-bandwidth delay line. Using the proposed INV-AIL delay cells and fractionally spaced delay line struc-ture, the bandwidth of the delay line is enhanced to achieve 3.5-Gb/s data rate in standard 0.25- m CMOS technologies. Also presented is a low-power area-efficient adaptation tech-nique using pulse extraction method to detect the spectrum of the equalized signal. Experimental results show that the
equal-izer can successfully adapt to channel loss of 4 dB to 21 dB at half-data-rate frequency for 2.5-Gb/s data rate and channel loss is about 9.3 dB at the half-data-rate frequency for 3.5-Gb/s data. The FIR filter and the error detector occupy 0.095 mm of die area and consume 95 mW from 2.5-V supply at 2.5-Gb/s data rate.
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Gb/s equalizers.
Jin Liu(S’97–M’99) received the B.S. degree in electronics and information systems from Zhong-shan University, China, in 1992, the M.S. degree in electrical and computer engineering from the Uni-versity of Houston, Houston, TX, in 1995, and the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, in 1999.
She joined the University of Texas at Dallas as an Assistant Professor in 1999 and is currently an Asso-ciate Professor at the same university. Her research interests are high-speed communication circuits, sensor interface circuits, and system integration/miniaturization. Current projects include adaptive equaliza-tion and clock/data recovery circuits for high-speed data communicaequaliza-tions, low-power CMOS motion detection imagers, low-power and data transmission circuits for battery-less and wireless sensors, and high-speed A/D converters.
Dr. Liu is an associate editor of IEEE TRANSACTIONS ONCIRCUITS AND
SYSTEMSPARTII, EXPRESSBRIEFS.
Hoi Lee (S’00–M’05) received the B.Eng. (First Class Honors), M.Phil., and Ph.D. degrees in elec-trical and electronic engineering from the Hong Kong University of Science and Technology, Hong Kong, China, in 1998, 2000, and 2004, respectively. In January 2005, he joined the Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, as an Assistant Professor. His research interests include low-voltage low-power analog and mixed-signal circuit techniques, power management integrated circuits and biomedical integrated systems for neural prostheses.
Dr. Lee was the recipient of the Best Student Paper Award at the 2002 IEEE Custom Integrated Circuits Conference.
Hao Liu(S’04) received the B.S. degree in electrical engineering from Wuhan University of Technology, Wuhan, China, in 1996, and the M.S. degree in electrical engineering from the University of Texas at Dallas in 2002, where he is currently working toward the Ph.D. degree.
