FSK

(1)

Implementation of FSK modulation and demodulation

using CD54/74HC/HCT4046A

Mahendra

Mahendra Patel Patel Standard Standard Linear Linear & & LogicLogic

ABSTRACT

In

In telecommunications telecommunications andand signal signal processing,processing, frequency frequency modulation modulation (FM) (FM) is is encoding encoding ofof information

information on aon a carrier wavecarrier wave by varying theby varying the instantaneous instantaneous frequencyfrequency of the wave.of the wave. Digital Digital data

data can be encoded and transmitted via carrier wave by can be encoded and transmitted via carrier wave by shifting the carrier's frequency amongshifting the carrier's frequency among a predefined set of frequencies

a predefined set of frequencies——a technique known asa technique known as frequency-shift frequency-shift keyingkeying (FSK). FSK is(FSK). FSK is widely used in

widely used in modems modems,, Radio-teletypeRadio-teletype andand fax modems, fax modems, and can also be used to send and can also be used to send Morse Morse code.

code.

Frequency-shift keying

Frequency-shift keying ( (FSKFSK) is a) is a frequency modulation frequency modulation scheme in which digital information isscheme in which digital information is transmitted through discrete frequency changes of a

transmitted through discrete frequency changes of a carrier wave. carrier wave. This aThis application pplication report wreport willill discuss logic level implementation of BFSK modulator and demodulator using a PLL device discuss logic level implementation of BFSK modulator and demodulator using a PLL device HC/HCT4046A. BFSK is the simplest FSK, which uses a pair of discrete frequencies to transmit HC/HCT4046A. BFSK is the simplest FSK, which uses a pair of discrete frequencies to transmit binary information. binary information. Contents Contents 1. 1. IntroductionIntroduction 2.

2. Implementation of ModulatorImplementation of Modulator 3.

3. Implementation of DemodulatorImplementation of Demodulator 4.

4. Test circuit waveformsTest circuit waveforms 5.

5. Schemes to realize modulator-demodulator pairSchemes to realize modulator-demodulator pair 6.

6. ConclusionConclusion

List of Figures List of Figures

1.

1. Block diagram of an HC/HCT4046A in a Block diagram of an HC/HCT4046A in a Typical PLL circuitTypical PLL circuit 2.

2. Basic block diagram of a PLL as Basic block diagram of a PLL as a modulatora modulator 3.

3. Frequency characteristics of VCO operating without offsetFrequency characteristics of VCO operating without offset 4.

4. Typical modulator schematicTypical modulator schematic 5.

5. Basic block diagram of a PLL as Basic block diagram of a PLL as a demodulatora demodulator 6.

6. Typical demodulator schematicTypical demodulator schematic 7.

7. Scheme 1Scheme 1 8.

8. Scheme 2Scheme 2 9.

9. Level shifter circuit using LP211Level shifter circuit using LP211

List of Tables List of Tables

1.

1. Modulator test circuit resultsModulator test circuit results 2.

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1. 1. Introduction

Introduction

Many measurement applications (for example, electric and gas meters) require a way to Many measurement applications (for example, electric and gas meters) require a way to communicate electronically with a central office so that measured data can be reported back to communicate electronically with a central office so that measured data can be reported back to the central office and new tariffs can be set in the remote site

the central office and new tariffs can be set in the remote site(1)(1)_{. Telephony provides a}_{. Telephony provides a}

convenient means of data communication. convenient means of data communication.

This application report will discuss logic level implementation of FSK modulator and This application report will discuss logic level implementation of FSK modulator and demodulator using a PLL device HC/HCT4046A. The HC/HCT4046A, PLL with VCO is a high-speed demodulator using a PLL device HC/HCT4046A. The HC/HCT4046A, PLL with VCO is a high-speed CMOS IC designed for

CMOS IC designed for use in general-purpose PLL applications, including frequency use in general-purpose PLL applications, including frequency modulation,modulation, demodulation, discrimination, synthesis and multiplication.

demodulation, discrimination, synthesis and multiplication. Figure 1 illustrates functional block diagram of a PLL IC, Figure 1 illustrates functional block diagram of a PLL IC,

1.

1. The voltage controlled oscillator (VCO) generates a centre frequency locally.The voltage controlled oscillator (VCO) generates a centre frequency locally. 2.

2. This is compared with the incoming signal frequency using a This is compared with the incoming signal frequency using a phase comparator (PC)phase comparator (PC) 3.

3. PC generates an error voltage Vd, which is fed into VCO after an LPF to shift thePC generates an error voltage Vd, which is fed into VCO after an LPF to shift the frequency of VCO to lock with incoming signal.

frequency of VCO to lock with incoming signal.

Figure 1. Block diagram of an HC/HCT4046A in a Typical PLL

Figure 1. Block diagram of an HC/HCT4046A in a Typical PLL circuitcircuit (1)

(1) Schematics in this report are only for reSchematics in this report are only for reference. Precise implementation can vary fromference. Precise implementation can vary from country to country and based

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2. 2. Implementati

Implementation

on of Modulator:

of Modulator:

Function of modulator uses only VCO as shown in the block diagram below. Values of R1

Function of modulator uses only VCO as shown in the block diagram below. Values of R1 and C1and C1 determine the frequency range of the VCO. And centre frequency of

determine the frequency range of the VCO. And centre frequency of operation depends uponoperation depends upon VCO input, which is digital input signal level

VCO input, which is digital input signal level for a modulator. Hence high (bit1) and low (bit 0)for a modulator. Hence high (bit1) and low (bit 0) voltage level of digital

voltage level of digital input determines actual output frequencies and separation betweeinput determines actual output frequencies and separation betweenn them.

them.

Figure 2. Basic block diagram of a PLL

Figure 2. Basic block diagram of a PLL as a modulatoras a modulator To design a modulator with maximum and minimum frequency of f

To design a modulator with maximum and minimum frequency of f MAXMAX and f and f MINMIN respectively, respectively,

following steps are required: following steps are required:

1.

1. Given f Given f MAXMAX and f and f MINMIN, centre frequency f , centre frequency f oo can be estimated as (f can be estimated as (f MAXMAX - f - f MINMIN))/2./2.

Figure 3. Frequency characteristics of VCO operating without offset: Figure 3. Frequency characteristics of VCO operating without offset:

2f

2f LL=frequency lock range=frequency lock range, f , f oo=Centre frequency=Centre frequency

2.

2. Determine the values of R1 and C1 using Determine the values of R1 and C1 using figure 11-15 given ifigure 11-15 given i n the device datasheet.n the device datasheet. Note that values of

Note that values of these components must satisfy following conditions,these components must satisfy following conditions, (i)

(i) 3kΩ < R1 < 300kΩ,3kΩ < R1 < 300kΩ,

(ii)

(ii) C1 C1 > > 40pF 40pF andand (iii)

(iii) (R1||R2) > 2.7K(R1||R2) > 2.7K Use of R2 to

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3.

3. Figure 16-21 of the Figure 16-21 of the device datasheet gives estimate of separation between frequenciesdevice datasheet gives estimate of separation between frequencies for given VCO

for given VCOININvoltage.voltage.

1.0V < VCO

1.0V < VCOININ < 0.9V < 0.9VCCCC is recommended to generate proper oscillation from VCO. is recommended to generate proper oscillation from VCO.

4.

4. A LPF (R3-C2) is included to minimize A LPF (R3-C2) is included to minimize the noise at VCOthe noise at VCOININ pin, which is optional. 3dB pin, which is optional. 3dB CutCut

off frequency of this filter

off frequency of this filter should be 10 times or should be 10 times or higher than the maximum bit rate ofhigher than the maximum bit rate of modulating signal.

modulating signal.

Figure 4. Typical modulator schematic Figure 4. Typical modulator schematic Example:

Example:

A test circuit (V

A test circuit (VCCCC = 5V) was implemented to modulate a digital = 5V) was implemented to modulate a digital signal with followingsignal with following

component values: component values: R1 = 3kΩ, C1 = R1 = 3kΩ, C1 = 47pF, R2 = open,47pF, R2 = open, R3 = 0 R3 = 0Ω, C2 =Ω, C2 =openopen

Table 1. Modulator test circuit results Table 1. Modulator test circuit results VCO

VCOININ(V) (V) Frequency Frequency of of VCOVCOOUTOUT(Hz) (Hz) VCOVCOOUTOUT peak to peak (V) peak to peak (V)

1. 1. 1.0 1.0 8.22M 8.22M 4.64.6 2. 2. 2.5 2.5 17.24M 17.24M 3.13.1 3. 3. 4.5 4.5 27.93M 27.93M 2.22.2

Hence by choosing logic 0 as 1V and

Hence by choosing logic 0 as 1V and logic 1 as 4.5V, a logic 1 as 4.5V, a frequency separation of 19.7MHzfrequency separation of 19.7MHz can be obtained.

can be obtained.

In practical circuit, frequency separation depends upon the

In practical circuit, frequency separation depends upon the bandwidth availability of thebandwidth availability of the transmission media. Hence by choosing appropriate offset frequency and voltage

transmission media. Hence by choosing appropriate offset frequency and voltage levellevel of VCO

of VCOININ signal, expected modulation can be signal, expected modulation can be achieved.achieved.

With increase in VCO

With increase in VCOININ (CH1) voltage, frequency of oscillation increases and VCO (CH1) voltage, frequency of oscillation increases and VCOOUTOUT peak peak

to peak voltage (CH2) decreases as shown in the figure given

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Waveform 1. VCO

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3. 3. Implementati

Implementation

on of Demodulator:

of Demodulator:

Demodulator operates in closed loop mode with PC and an external LPF as shown

Demodulator operates in closed loop mode with PC and an external LPF as shown below,below,

Figure 5. Basic block diagram of a PLL as

Figure 5. Basic block diagram of a PLL as a demodulatora demodulator To design a demodulator with maximum and minimum frequency of f

To design a demodulator with maximum and minimum frequency of f MAXMAX and f and f MINMIN respectively respectively

(which is same as that of modulator), following

(which is same as that of modulator), following steps are required:steps are required: 1.

1. Use same value of R1 Use same value of R1 and C1 as that of modulator.and C1 as that of modulator. 2.

2. While using PC1, the capture range depends on the LPF (R3While using PC1, the capture range depends on the LPF (R3 -C2) characteristics and can be-C2) characteristics and can be made as large as the lock range. For

made as large as the lock range. For PC2, capture range is equal to lock range and isPC2, capture range is equal to lock range and is independent of the LPF.

independent of the LPF. 3.

3. Since leakage current can affect the VSince leakage current can affect the VDEMOUTDEMOUT, a load resistor (R5) from , a load resistor (R5) from this pin to GND in thethis pin to GND in the

range of 50k to 300k is

range of 50k to 300k is recommended.recommended.

Figure 6. Typical demodulator schematic Figure 6. Typical demodulator schematic Example:

Example:

A test circuit (V

A test circuit (VCCCC = 5V) was implemented to demodulate a signal using PC2 = 5V) was implemented to demodulate a signal using PC2 withwith

following component values: following component values:

R1 = 3kΩ, C1 = 47pF, R2 =

R1 = 3kΩ, C1 = 47pF, R2 = open,open, R3 = 36kΩ, C2 = 120pF

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Table 2. Demodulator test circuit results Table 2. Demodulator test circuit results VCO VCOININ(V)(V) at modulator at modulator Frequency of SIG Frequency of SIGININ (Hz) (Hz) At demodulator At demodulator SIG

SIGININ peak to peak (V) peak to peak (V)

At demodulator At demodulator

DEM

DEMOUTOUT(V)(V)

At modulator At modulator 1. 1. 1.0 1.0 8.22M 8.22M 4.6 4.6 1.281.28 2. 2. 2.5 2.5 17.24M 17.24M 3.1 3.1 2.52.5 3. 3. 4.5 4.5 27.93M 27.93M 2.2 2.2 3.763.76 Hence by choosing 3.5Vp-p VCO

Hence by choosing 3.5Vp-p VCOININ and frequency separation of 19.7MHz at modulator, and frequency separation of 19.7MHz at modulator,

DEM

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4. 4. Test Circuit Waveforms:

Test Circuit Waveforms:

Waveforms below show variation in following with change in VCO

Waveforms below show variation in following with change in VCOININ voltage, voltage,

(i)

(i) VCOVCOOUTOUT frequency, frequency,

(ii)

(ii) VCOVCOOUTOUTof modulator or SIGof modulator or SIGININ of demodulator peak to peak voltage and of demodulator peak to peak voltage and

(iii)

(iii) Corresponding DEMCorresponding DEMOUTOUT voltage. voltage.

Table 3. Variation in VCO

Table 3. Variation in VCOOUTOUT frequency, p-p voltage and DEM frequency, p-p voltage and DEMOUTOUT

Condition

Condition at at Modulator Modulator Demodulator Demodulator Waveforms:Waveforms: CH1: SIG

CH1: SIGININ and CH2: DEM and CH2: DEMOUTOUT

1. VCO

1. VCOININ = 1V = 1V

Waveform 2. For VCO

Waveform 2. For VCOININ = 1V = 1V

2. VCO

2. VCOININ = 2.5V = 2.5V

Waveform 3. For VCO

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3. VCO

3. VCOININ = 4.5V = 4.5V

Waveform 4. For VCO

Waveform 4. For VCOININ = 4.5V = 4.5V

Following waveforms show VCO

Following waveforms show VCOININ (level shifted digital (level shifted digital modulating signal), VCOmodulating signal), VCOOUTOUT (modulated (modulated

signal) and corresponding DEM

signal) and corresponding DEMOUTOUT (demodulated signal) at different frequencies of digital (demodulated signal) at different frequencies of digital

signal. signal.

Table 4. VCO

Table 4. VCOININ (modulating), VCO (modulating), VCOOUTOUT (modulated) and DEM (modulated) and DEMOUTOUT (demodulated) (demodulated)

VCO

VCOININ DEMDEMOUTOUT Waveforms:Waveforms:

CH1: VCO

CH1: VCOININ, CH2: VCO, CH2: VCOOUTOUT, CH3: DEM, CH3: DEMOUTOUT

1. 1. pk-pk (V)=3.44Vpk-pk (V)=3.44V Frequency=1kHz Frequency=1kHz pk-pk (V)=3.12V pk-pk (V)=3.12V Mean (V)=2.74V Mean (V)=2.74V

Waveform 5. For VCO

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Waveform 6. For VCO

Waveform 6. For VCOININ frequency = 5kHz frequency = 5kHz

Waveform 7. For VCO

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Waveform 8. For VCO

Waveform 9. For VCO

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Waveform 10. For VCO

It can be concluded from the above waveforms that, it

It can be concluded from the above waveforms that, it is difficult to use the DEMis difficult to use the DEMOUTOUT signal as it signal as it

is, at higher frequency of modulating signal. Hence, a

is, at higher frequency of modulating signal. Hence, a Schmitt trigger can be used withSchmitt trigger can be used with appropriate threshold and hysteresis to get a

appropriate threshold and hysteresis to get a clean demodulated signal with sharp rising clean demodulated signal with sharp rising andand falling edges.

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5. 5. Schemes to realize

Schemes to realize modulator

modulator

_–

demodulator pair

This section describes various FSK modulation-demodulation schemes briefly. It is important to This section describes various FSK modulation-demodulation schemes briefly. It is important to consider the limitations of each technique before using it

consider the limitations of each technique before using it for a specific application. In for a specific application. In each case,each case, frequency used to represent digital data after FSK modulation should be hundred folds or frequency used to represent digital data after FSK modulation should be hundred folds or higher that of digital data rate to

higher that of digital data rate to ensure correct bit duration for each bit after demodulation.ensure correct bit duration for each bit after demodulation. 5.1

5.1 Scheme 1:Scheme 1: In this scheme,

In this scheme, VCO at the modulator transmits a particular fVCO at the modulator transmits a particular frequency during occurrencesrequency during occurrences of bit 1

of bit 1 in the digital data and remains idle during occurrence of bit in the digital data and remains idle during occurrence of bit 0. At the demodulator0. At the demodulator end, presence or absence of the frequency is

end, presence or absence of the frequency is tracked by the PLL. PC output followed by LPFtracked by the PLL. PC output followed by LPF represents demodulated signal, which is equivalent of original digital information.

represents demodulated signal, which is equivalent of original digital information. For

For this this scheme, scheme, VCOVCOININ < 0.6V for logic 0 and < 0.6V for logic 0 and

VCO

VCOININ close to 0.9*VCC for logic close to 0.9*VCC for logic 1 is recommended.1 is recommended.

Use of PC2 at demodulator gives good results over

Use of PC2 at demodulator gives good results over wide range of frequency.wide range of frequency.

Figure 7. Scheme 1 Figure 7. Scheme 1 Advantages:

Advantages:

-- Power consumption is less at Power consumption is less at modulator.modulator.

-- A burst of frequency is transmitted only during transmission of a A burst of frequency is transmitted only during transmission of a specific data bit (eitherspecific data bit (either 1 or 0), hence there

1 or 0), hence there is less noise created in the transmission media.is less noise created in the transmission media. -- Single frequency is used, hence bandwidth requirement is lesser.Single frequency is used, hence bandwidth requirement is lesser.

-- Gives better performance even at higher frequencies (200kps or higher) of Gives better performance even at higher frequencies (200kps or higher) of modulatingmodulating signal (as compared to scheme 2), because of wide separation possible between logic 0 signal (as compared to scheme 2), because of wide separation possible between logic 0 and logic 1 voltages.

and logic 1 voltages. Limitations:

Limitations:

-- It is difficult to It is difficult to make out if remote modulator is defunct.make out if remote modulator is defunct.

-- When VCOWhen VCOININ < 0.6V (logic 0), < 0.6V (logic 0), modulator output may either be 0V or VCC, howevermodulator output may either be 0V or VCC, however

this does not

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5.2

5.2 Scheme 2:Scheme 2: In this scheme,

In this scheme, VCO at the modulator transmits one particular frequency duringVCO at the modulator transmits one particular frequency during occurrences of bit 1 in the digital

occurrences of bit 1 in the digital data and other frequency during occurrence of bit 0.data and other frequency during occurrence of bit 0. At the demodulator end, change in the frequency is tracked by the PLL. PC

At the demodulator end, change in the frequency is tracked by the PLL. PC outputoutput followed by LPF represents demodulated signal, which is equivalent of original digital followed by LPF represents demodulated signal, which is equivalent of original digital information.

information.

For this scheme, 1.0V < VCO

For this scheme, 1.0V < VCOININ < 0.9V < 0.9VCCCC is required. is required.

Use of PC2 at demodulator gives good results over wide

Use of PC2 at demodulator gives good results over wide range of frequency.range of frequency.

Figure 8. Scheme 2 Figure 8. Scheme 2 Level shifting of input digital signal is

Level shifting of input digital signal is required to meet VCOrequired to meet VCOININ input range, which can be input range, which can be

achieved using level shifter circuit, achieved using level shifter circuit,

Figure 9. Level shifter circuit using LP211 Figure 9. Level shifter circuit using LP211 As can be seen from the test

As can be seen from the test waveform above, a digital signal Vin (0V-3.3V) is waveform above, a digital signal Vin (0V-3.3V) is convertedconverted to VCOin (1.07V-4.5V).

to VCOin (1.07V-4.5V).

Advantages: Advantages:

-- It is easy to It is easy to make out if remote modulator is defunct.make out if remote modulator is defunct. Limitations

Limitations

-- Power consumption is more at modulator due to continuous oscillationsPower consumption is more at modulator due to continuous oscillations -- Requires more bandwidthRequires more bandwidth

-- As VCOAs VCOININ logic 0 and logic 0 and logic1 voltage level separation decreases, noise onlogic1 voltage level separation decreases, noise on

demodulated output increases demodulated output increases

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6. 6. Conclusion

Conclusion

This application report described logic level implementation of

This application report described logic level implementation of BFSK modulator andBFSK modulator and demodulator using HC/HCT4046A devices.

demodulator using HC/HCT4046A devices. However, while implementing this circuit for

However, while implementing this circuit for a real time application, following are some of a real time application, following are some of thethe important factors to consider for rel

important factors to consider for reliable communication link,iable communication link, (i)

(i) output impedance of the modulator,output impedance of the modulator, (ii)

(ii) characteristic impedance of the transmission media,characteristic impedance of the transmission media, (iii)

(iii) frequency response of transmission media,frequency response of transmission media, (iv)

(iv) input impedance of the input impedance of the demodulator.demodulator.

Hence, impedance matching and signal conditioning becomes

Hence, impedance matching and signal conditioning becomes an important part in a an important part in a practicalpractical system.