• No results found

A BATCH OPTIMIZATION SOLVER FOR DIFFUSION AREA SCHEDULING IN SEMICONDUCTOR MANUFACTURING

N/A
N/A
Protected

Academic year: 2021

Share "A BATCH OPTIMIZATION SOLVER FOR DIFFUSION AREA SCHEDULING IN SEMICONDUCTOR MANUFACTURING"

Copied!
6
0
0

Loading.... (view fulltext now)

Full text

(1)

A BATCH OPTIMIZATION SOLVER FOR DIFFUSION AREA SCHEDULING IN SEMICONDUCTOR MANUFACTURING Christian Artigues∗,∗∗ St´ephane Dauz`ere P´er`es∗∗∗

Alexandre Derreumaux∗∗∗ Olivier Sibille∗∗∗∗ Claude Yugma∗∗∗

Laboratoire d’Informatique d’Avignon, Universit´e

d’Avignon, BP 1228 Avignon Cedex 9, France

∗∗Centre de Recherche sur les Transports, Universit´e de

Montral, C.P. 6128, succursale Centre-ville, Montr´eal, QC H3C 3J7 Canada

∗∗∗Ecole des Mines de Saint-Etienne, CMP Georges

Charpak, Avenue des An´emones - Quartier Saint-Pierre, F-13541 Gardanne, France

∗∗∗∗ATMEL, Zone industrielle, 13790 Rousset, France

Abstract: We propose a method for solving a dayly batching and scheduling problem of lots of wafers in the diffusion area of a semiconductor plant. The involved complex constraints include in particular both minimal and maximal time lags and there are multiple objectives. The method is based on a disjunctive graph which allows fast calculation of operation start times from a partial or complete batching proposition. A prototype interactive software issued from this research is currently in test in the ATMEL Rousset fabrication unit.

Keywords: Wafer fabrication, diffusion area, batch scheduling, disjunctive graph, local search

1. INTRODUCTION

Semiconductor wafer fabrication can be described as a multistage process with re-entrant flows. The operations include chemical-mechanical polishing, diffusion, film deposition, photolithography, im-plant (doping) and etching. For each of the prod-uct types, a wafer goes through approximately 500 process steps over a period of a few weeks. Wafer fabrication planning and scheduling is a complex task due to the large number of products and machines involved. It is further complicated by additional constraints such as re-entrant flow of operations, setup issues, preventive maintenances and random machine breakdowns, etc.

The importance of scheduling on the performance of semiconductor wafer fabrication facilities is known for many years (Wein, 1988). Recently (Toba et al., 2005) have also shown the impor-tance of using predictive scheduling in load bal-ancing methods among multiple semiconductor wafer fabrication lines in order to make a better estimation of the lot cycle times.

The complexity of the fabrication process is such that most previous existing work on scheduling in semiconductor manufacturing focus on dipatch-ing rules (Wein, 1988; Dabbas and Fowler, 2003). Other approaches deal with Integer Linear Pro-gramming formultations of the problem and apply lagrangean relaxation of the equipment

(2)

limita-tions constraints (Liao et al., 1996; Hwang and Chang, 2003). For a given set of lagrangean mul-tipliers, the relaxation can be solved with mincost network flow methods. Subgradient optimization is used to solve the dual linear program. A feasible solution is obtained by adjusting heuristically the solution of the relaxation.

In this paper, instead of scheduling the entire fab, we propose to focus on a bottleneck part of the manufacturing process. Among the complex operations involved in the fabrication of a wafer, the diffusion phase is of critical importance since the batching decisions it involves may affect the performance of the entire wafer fab (Ibrahim et al., 2003; Monch and Habenicht, 2003). This also the case in the ATMEL fabrication unit of Rousset (France). The diffusion phase is used primarily to alter the type and level of conductivity of semiconductor materials. It is used to form bases, emitters and resistors in bipolar devices, and also to dope polysilicon layers.

The diffusion area defines a batching and schedul-ing problem of lots of wafers. Each lot is made of one or more consecutive operations on equipments (furnaces) and each operation has a recipe which determines its duration and the equipments able to process it. On a 24-hour basis, each operation has to be assigned to an equipment, and included into a batch, i.e. a set of operations of the same recipe that are processed simultaneously by the equipment. The batch size may vary from one operation to a limit fixed by the equipment capac-ity. On each equipment, the constituted batches must be sequenced and a start time has to be assigned to each batch. Some equipments may be unavalaible during specified time periods. Each lot has an expected arrival time in the diffusion area during the next 24 hours. There are minimal and maximal time lags between the start times of the batches due to process and equipment con-straints. The considered and possibly conflicting scheduling objectives are the maximization of the number of wafers produced in the time period, the maximization of batching and the minimization of the X-factor, which is a multiplier of the minimal expected cycle time.

The BOS (Batch Optimization Software) project aims at improving the scheduling decisions at the diffusion area by developing a Decision Support System that optimizes these various performance measures, while taking into account the numerous complex constraints. In the litterature, batching and scheduling in diffusion areas is mainly per-formed by dispathing rules (Ibrahimet al., 2003). (Monch and Habenicht, 2003) propose to use a dispatching rule to batch the operations and a genetic algorithm to assign the batches to the equipments. In (Masonet al., 2002), a scheduling

problem in semiconductor manufacturing related to the one tackled in this paper is solved by a mod-ified shifting bottleneck heuristic (Adams et al., 1988). The author use the disjuctive graph rep-resentation, a useful model for complex job-shops (Roy and Sussman, 1964). They consider a dif-ferent objective function (namely total weighted tardiness). Sequence-dependent setup times and reentrant flows are also tackled but there are no maximal time lags. Unfortunately, these latter constraints increase considerably the difficulty of the problem, see e.g. (Gentneret al., 2004). In this paper, we propose a model of the solution of the considered batching and scheduling prob-lem through a variant of the disjunctive graph proposed in (Mason et al., 2002). We propose a constructive heuristic to build an initial solution graph and a local search procedure to improve the solution for the considered objectives.

Another objective of the BOS project is to make the proposed schedule easily modifiable by the decision makers at the fabrication level. Equip-ments may be declared as down, operations may be moved, lots may be removed or inserted. We show how these requirements are achieved thanks to the flexibility of the disjunctive graph repre-sentation and we present the software issued from this research, currently in production test in the ATMEL Rousset factory. In Section 2, we give the problem formulation. In Section 3, we present the proposed disjunctive graph. The solution methods are described in Section 4. Experimental results on ATMEL real data are presented in Section 5. The BOS software is presented in Section 6. Concluding remarks are drawn in Section 7.

2. PROBLEM FORMULATION

The scheduling problem can be formulated as fol-lows. In Section 5, we will describe more precisely the additional characteristics of the problem in the ATMEL Rousset factory.

A set of jobs (lots)J ={Ji|i= 1, . . . , n}has to be

processed during a periodT by a set of machines

M={Mk|k= 1, . . . , m}. Each job Ji is made of

ni operations such that each operationOij has a

durationpij >0 and a setMij⊆ Mof machines

(the furnaces of the diffusion area) able to process it. Let Ok = {Oij ∈ O|Mk ∈ Mij} denote the

set of operations that can be assigned to machine Mk. The value ofpij and the elements of the set Mijare determined by the recipe of operationOij

denotedρij. In general we have Mij ⊂ Msince

each machine cannot be configured for all recipes. Each operationOij has to be included in a batch

on a resourcek∈ Mij. Each machine has a finite

(3)

operations that can be processed simultaneaously in the same batch. On each machinek,Sk denote

the setup time needed before starting a new batch, Dk denote the removal time needed after the

completion of a batch andsk denote the constant

setup time needed between two different batches. s0

k denotes the initial setup time on machine k,

depending on the state of the resource at time 0. Two consecutive operationsOij andOi(j+1) of the same job are linked by minimal and maximal time lags. Once the batch ofOij is completed and

removed fromk, the setup for the batch ofOi(j+1) cannot start before a minimal time lagτmin

ij and

has to start before a maximal time lag τmax

ij . Let O ={Oij|i = 1, . . . , n;j = 1, . . . , ni} denote the

set of all operations. Each job Ji has a relative

priority ci (ci < cj =⇒ Ji is more urgent

than Jj). Each job corresponds to a number wi

of wafers produced when the job is completed. Finding a feasible solution for the problem lies in making four types of decisions:

D1 Partition the operations into batches. D2 Select a resource to process each batch. D3 Order the batches on each resource. D4 Assign a start time to each batch.

Decisions D1-D3 can all be represented by a family of batches B ={Bkq}k∈{1,...,m},q∈{1,...,νk}

where Bkq represents the batch sequenced at

po-sitionqon machineMk.νk∈ {0, . . . ,|Ok|}denote

the number of batches assigned to machine Mk.

Decision D4 can be represented by a family of start times T = {tij}Oij∈O assigned to the

op-erations. Once a solution {B,T } is determined, we can derive a machine assignment{mij}Oij∈O

wheremij denote the machineOij is assigned to,

i.e. verifying ∃q ∈ {1, . . . , νk} such that Oij ∈

Bmijq. To be feasible, a solution {B,T } and

its corresponding assignment{mij}Oij∈Ohave to

satisfy the following constraints. The operations of the same batch must have the same recipe.

ρij =ρxy ∀B ∈ B,∀Oij, Oxy∈B (1)

Each operation must be assigned to a machine able to process its recipe.

mij ∈ Mij ∀Oij ∈ O (2)

The batch capacity cannot be exceeded and each batch includes at least one operation.

1≤ |Bkq| ≤Rk ∀Bqk∈ B (3)

An operation appears in only one batch..

B∩B′=∅ B, B′∈ B, B6=B′ (4) All operations are included in a batch

∪B∈BB=O (5)

The start time of the first operation of each job cannot exceed the job release date

ti1≥ri ∀Ji∈ J (6)

Each operation Oij, j > 1, cannot start before

a minimal time lag after the end of preceding operation Oi(j−1), which takes account of the

removal time of the batch ofOi(j−1), the minimal

time lagτmin

i(j−1)and the setup time of batch ofOij.

tij−ti(j−1)≥Dmi(j−1)+pi(j−1)+τ

min

i(j−1)+Smij ∀i∈ {1, . . . , n},∀j ∈ {2, . . . , ni} (7)

Each operation Oij, j > 1, has to start before

a maximal time lag after the end of preceding operation Oi(j−1), which takes account of the

removal time of the batch ofOi(j−1), the maximal

time lagτmax

i(j−1)and the setup time of batch ofOij.

tij−ti(j−1)≤Dmi(j−1)+pi(j−1)+τ

max

i(j−1)+Smij ∀i∈ {1, . . . , n},∀j ∈ {2, . . . , ni} (8)

The start times of two operations of the same batch must be equal.

tij =txy ∀B ∈ B,∀Oij, Oxy∈B (9)

An operation of a batch which is not at the first position on its machine cannot start before the end of the preceding batch on the machine, plus the necessary removal time of the preceding batch, plus the minimal setup time on the machine between two batches, plus the necessary setup time for the next batch.

tij−txy ≥pxy+Dk+sk+Sk

∀Bkq,q>1∈ B,∀Oij∈Bkq,∀Oxy∈Bk(q−1) (10) An operation of a batch in the first position on its machine cannot start before the initial setup time for this batch 1.

tij≥s0mij ∀Oij ∈ O (11)

By definition a feasible solution include each op-eration inside a batch. In the ATMEL Rousset production unit, the scheduling horizon is in fact limited to a scheduling periodT. Hence only those batches started in the interval [0, T[ must be taken into account. Several criteria are used to measure the quality of a feasible solution. The number of moves is number of wafers produced during the time period T.

fmov = X

Ji∈J

wiθi (12)

where θi= 1 when the job is completed beforeT

and θi∈[0,1[ denote the completion ratio of job

ibefore timeT otherwise. θi= P Oij,tij+pij<=T pij+ P Oij,tij<T <tij+pij (T−tij) Pni j=1pij 1 we assumeS0 k≤Sk+Dk+sk,∀Mk∈ M.

(4)

The batching coefficient is the average quotient of the actual size of each batch over to its maximal size. Let BT ={B∈ B|t

ij< T,∀Oij ∈B} denote

the set of batches started before time periodT. fbatch =

P

Bkq∈BT |B|/Rk

|BT| (13)

The average X-factor is the average of the X-factor of each job ponderated by the job priority. Let

JT ={J

i ∈ J |tini+pini ≤T}denote the set of

jobs completed beforeT.

fX-fac =

P

Ji∈JTci(tini−ri)

|JT| (14)

The choice made in relation with the decision makers in the ATMEL Rousset unit is to combine these different objectives into a single one by minimizing the sum

f =αfmov−βfbatch−γfX-fac (15) whereα,β andγare adujstable weigths allocated to each objective function. Hence we search of a feasible selection{B,T }such thatf is maximized. Note that given a (feasible) solution{B,T },fcan be computed inO(N) time whereN=Pni=1niis

the total number of operations.

3. THE DISJUNCTIVE GRAPH REPRESENTATION

The considered problem can be seen as an exten-sion of the job-shop problem and, consequently, the disjunctive graph model can be used for batching and scheduling problems as proposed by (Mason et al., 2002). We define the disjunctive graphG= (V, C, E) as follows.

• V is a set of nodes where there is a node per operations, denoted Vij plus a dummy start

node denoted 0.

• C is the set of conjunctive arcs representing the release dates and minimal and maximal time lags. There is an arc from node 0 to node Vi1 of each job Ji. There is an arc from Vij

to Vi(j+1)and an arc from Vi(j+1) to Vij, for

each consecutive operations Oij andOi(j+1) of each jobJi.

• E is the set of disjunctive arcs which rep-resent the decisions of the problem. There are two opposite disjunctive arcs (Vij, Vxv)k

and (Vxy, Vij)k for any machine k∈ M and

for any pair of operations Oij, Oxy ∈ Ok,

Oij 6= Oxy. Such an arc represent the

se-quencing or the batching decision concerning Oij andOxy on machinek.

Let B denote a partial or complete batching for the problem satisfying at least constraints (1), (2),

(3) and (4).Bis a complete batching if (5) is also verified, otherwise it is a partial batching . Recall

Balso defines the machine assignmentmij, for all

Oij ∈ ∪B∈BB. We assume mij = 0 if Oij is not

batched in B, i.e. if we haveOij6∈ ∪B∈BB. Bunambiguously defines a selectionS as follows: For each distinct operations Oij and Oxy such

that mij = mxy = k 6= 0, select arc (Vxy, Vij)k

if Oxy is in a batch sequenced before the batch

of Oij, select arc (Vij, Vxy)k ifOij is in a batch

sequenced before the batch of Oxy, select both

arcs (Vij, Vxv)k and (Vxy, Vij)k ifOij andOxy are

assigned to the same batch.

Once a selection is computed, we define a graph G(S) = (V, C∪ S) where arcsC∪ S are valuated as follows 2:

• Each arc from 0 to the first operation Oi1 is valuated by max(ri, Sm0ij), the maximal

value between the release date of job i and the initial setup time for machinemi1. • Each arc fromVij andVi(j+1) is valuated by

Dmij+pij+τ

min

ij +Smi(j+1), the value of the

minimal time lag between Oij and Oi(j+1) augmented by the setup and removal times linked to the assignment of the operations.

• Each arc from Oi(j+1) and Oij is valuated

by −(Dmij + pij + τ

max

ij + Smi(j+1)), the

(negative) value of the maximal time lag between Oij and Oi(j+1) augmented by the necessary setup and removal times.

• Each arc (Vij, Vxv)k is valuated either by

pij+Dk+sk+Sk if the opposite arc is not

present or by 0 if the opposite arc is present. Indeed, in the first case this arc represent the decision to sequence Oxy after Oij on

machinek whereas in the second case, both arcs (Vij, Vxv)k and (Vxv, Vij)k represent the

sychronisation of the operations included in the same batch.

We can state that the (partial) solution repre-sented the (partial) batchingBand its selectionS

is feasible if and only if all longest path problems from node 0 to each node Vij in G(S) have a

solution. In the positive case and ifBis complete, a feasible schedule T can be obtained by setting tij to the length of the longest path from 0 toVij.

Furthermore T is the best schedule compatible with B one can obtain when the objective is to mazimizef.

The problem can be formulated as follows. Find the batching Bverifying constraints (1), (2), (3), (4) and (5) such that the corresponding selection

S is feasible and maximizesf.

2 we assumes0

(5)

4. SOLUTION METHODS

We propose a two-phase heuristic method to search for a good solution. The first phase is a constructive heuristic based on progressive job in-sertion. The second phase is a local search method which aims at improving the initial solution w.r.t. the objective function. Both phases are based on the evaluation of a (complete or partial) selection through longest path calculations.

4.1 Evaluation of a partial or complete batching

Any partial or complete batchingBand its selec-tionScan be evaluated through the calculation of start timetij, equal to the longest path from 0 to

Vij in G(S), for each operationOij. To compute

such longest paths, since the graph includes arcs with negative weights we use the Bellman-Ford algorithm which has a O(N|S ∪C|) time com-plexity. If the algorithms finds a path of positive length, then the partial or complete solution is unfeasible. Otherwise the algorithm returns start timestij and objective function valuef.

4.2 Computing an initial solution

The initial solution (selection) is computed by a simple job insertion methods. The jobs are first sorted in a list L according to the order: jobs involving maximal time lags first, then increasing release dates, then job priority.

The method starts with an empty batching. Then the jobs are taken in the order given by the list and inserted one by one in the current batching. The insertion of Ji is made as follows. Let B = {Bkq}k∈M,q∈1,...,νk denote the current batching

including jobs located before Ji in L. For each

operation Oij of Ji and for each resource k ∈ Mij, there are 2νk+ 1 insertion positions of Oij

in the batch sequence of machine Mk: indeed,

for each batch Bkq, we may insert Oij inside

batch Bkq or create a new batch right before

batch Bkq. Each of these insertion positions is

evaluated with the algorithm described in the previous section and the one that maximizesf is kept to updateB. If none of the insertion positions is feasible for an operationOij this means that all

these partial solutions violate a maximal time lag and there exists insertion positions that violate only maximal time lag between Oi(j−1) and Oij

(the last position on each resource of Mij, for

instance). Hence we have to removeOi(j−1)from

B, the previous operation of job Ji, and insert

it at a later insertion position. If this is not feasible, we reiterate the process for operation Oi(j−2), and so on. This process will issue a feasible insertion position for job Ji. Note that

at mostPni j=1

P

k∈Mij2νk+ 1 insertion positions

are tested per inserted job.

4.3 Improving the solution

The initial solution computed by the job insertion algorithm can be improved by local search. In simple local search (descent method), a set of moves is tested from an initial solution, each one issuing a new neighbor solution. The best neighbor solution is kept as the new start solution if it strictly improve the objective function and the algorithm is interated until there is no more improvements of the objective function. We have designed two types of moves for our problem the “merge” and the “job reinsertion” move. In order to improve the batching coefficient, the merge move aims at merging two batches of operations having the same recipe. The job reinsertion move, select a job and reinsert it in the solution by using the same method as for computing the initial solution, like if this job was the last inserted job. The local search methods applies iteratively a descent method based on the two moves.

5. COMPUTATIONAL EXPERIMENTS We have coded the proposed algorithm in java and we have tested it on a set of 40 instances of the problem issued for the production problem of 40 consecutive days in the ATMEL Rousset factory from January 1st to February 9th 2005. There are approximately 600 jobs yielding a total number of 1000 operations with about 50 different recipes to schedule on about 60 equipments. The target time horizon if of 24 hours. The actual data issued from the fab has other characteristics that have been tackled, such as in-process jobs and machine down times. We can model easily these characteristics thanks to the disjunctive graph formulation. They can be both represented by operations with fixed start times on the involved machine. A start time tcan be fixed by linking the node with node 0 by two opposite arcs valued byt and−t.

We compare the results of the proposed method with the previously develop method used for batch planning of the diffusion area, an ad-hoc inser-tion based method which is not based on the disjunctive graph model. For these instances, the limit time-horizon In table 5, we give for each method the cpu time, the number of moves (m), the batching coefficient (b) and the x-factor(xf). For each instance, the best result is displayed in italics. On average, the method are equivalent for the number of moves whereas the new method brings an improvement of 3% for the batching coefficient and of 2% for the x-factor, while the CPU time is increased by 34%.

(6)

Previous method Proposed method pb cpu m b xf cpu m b xf 1 18 10853 0,63 3,59 30 11138 0,68 3,56 2 20 11104 0,69 4,86 28 11317 0,68 4,80 3 30 14330 0,71 3,94 46 14492 0,74 4,01 4 31 14729 0,71 3,25 42 14010 0,75 3,13 5 27 13321 0,69 3,68 33 13787 0,74 3,61 6 29 14178 0,73 3,05 40 14168 0,71 2,95 7 26 13349 0,69 2,70 36 13426 0,70 2,70 8 25 13049 0,69 2,70 33 13229 0,73 2,84 9 29 12963 0,67 2,77 33 13084 0,70 2,74 10 30 13849 0,67 2,42 34 13624 0,70 2,48 11 26 12740 0,66 2,40 34 13019 0,66 2,38 12 24 12359 0,63 2,52 31 12156 0,62 2,40 13 34 13769 0,71 2,86 40 13845 0,72 2,73 14 33 14057 0,67 3,05 46 13756 0,71 2,98 15 36 12532 0,66 2,99 38 12901 0,72 2,93 16 27 12740 0,67 3,15 32 12738 0,69 3,23 17 31 14992 0,71 3,00 42 15096 0,72 3,02 18 32 12648 0,69 3,31 35 12713 0,71 3,21 19 33 12693 0,66 2,79 35 12984 0,65 2,81 20 33 12778 0,69 2,64 36 12726 0,72 2,67 21 31 14079 0,69 2,51 44 13930 0,71 2,47 22 32 13623 0,70 2,68 42 13824 0,71 2,68 23 26 12562 0,66 2,84 34 12177 0,67 2,80 24 24 13273 0,65 2,63 36 12899 0,68 2,70 25 31 13615 0,67 3,03 51 13413 0,72 2,74 26 28 14154 0,72 2,76 43 14279 0,75 2,74 27 26 13092 0,69 2,90 44 13400 0,72 2,65 28 35 14561 0,74 2,75 47 14970 0,76 2,72 29 32 14175 0,70 3,02 40 14112 0,73 3,07 30 35 14779 0,71 3,28 55 14914 0,74 3,27 31 26 13756 0,72 3,10 41 13711 0,73 3,00 32 21 13061 0,69 2,70 38 13135 0,69 2,60 33 15 10633 0,64 2,59 20 10878 0,66 2,61 34 19 11412 0,69 2,58 21 11237 0,71 2,67 35 30 13835 0,70 2,69 39 13535 0,71 2,60 36 27 14136 0,74 2,41 33 14234 0,76 2,43 37 28 12976 0,73 2,83 37 12851 0,74 2,67 38 26 13261 0,72 2,55 33 13358 0,73 2,60 39 29 12601 0,71 2,51 35 13211 0,72 2,38 40 27 13387 0,70 2,40 38 13444 0,73 2,41

Table 1. Experimental comparison 6. THE BOS SOFTWARE

The improvement brought by the use of a disjunc-tive graph is in fact more significant for interacdisjunc-tive scheduling at the fab level. A prototype software, the Batch Optimization Software, has been devel-oped jointly by ATMEL the University of Avignon (LIA) and the Ecole des Mines de Saint-Etienne (CMP Gardanne). It includes the off-line batching and scheduling phase, as described above, and also an interactive module that allow the decision-makers to make modifications and to test options directely on the proposed plan. The longest path calculations in the disjunctive graph allow to al-most immediately give the impact of a modifica-tion such as job removal, operamodifica-tion move, job or operation insertion. The software is currently in test in the ATMEL Rousset factory.

7. CONCLUDING REMARKS

We have proposed a novel method based on a disjunctive graph for batching and scheduling in semiconductor manufacturing with minimal and maximal time lags. This approach is in its earliest phase of development and several extensions are the core of our current research. The maximal time lags are currently hard constraints. However in practice some of them can be relaxed and treated as soft constraints or objectives. Another important issue lies in the underlying multiobjec-tive optimization problem which has to be studied more specifically.

REFERENCES

Adams, J., E. Balas and D. Zawack (1988). The shifting bottleneck procedure for job shop scheduling. Management Science 34, 391– 401.

Dabbas, R. M. and J. W. Fowler (2003). A new scheduling approach using combined dispatching criteria in wafer fabs. IEEE Transactions on Semiconductor Manufactur-ing16(3), 501–510.

Gentner, K., K. Neumann, C. Schwindt and N. Trautmann (2004). Batch production scheduling in the process industries. In:

Handbook of Scheduling: Algorithms, Mod-els and Performance Analysis(J.Y.T. Leung, Ed.). pp. 48.1–48.21. CRC Press. Boca Ra-ton.

Hwang, T.-K. and S.-C.g Chang (2003). De-sign of a lagrangian relaxation-based hier-archical production scheduling environment for semiconductor wafer fabrication. IEEE Transactions on Robotics and Automation

19(4), 566–578.

Ibrahim, K., M. A. Chik, W. S.Nizam, N. L. Fem and N. F. Za’bah (2003). Efficient lot batching system for furnace operation. In:

IEEE/SEMI Advanced Semiconductor Man-ufacturing Conference. pp. 322–324.

Liao, D.-Y., S.-C. Chang, K.-W. Pei and C.-M. Chang (1996). Daily scheduling for r&d semi-conductor fabrication.IEEE Transactions on Semiconductor Manufacturing9(4), 550–560. Mason, S.J., J.W. Fowler and W.M. Carlyle (2002). A modified shifting bottleneck heuris-tic for minimizing total weighted tardiness in complex job shops.Journal of Scheduling

5(3), 247–262.

Monch, L. and I. Habenicht (2003). Simulation-based assessment of batching heuristics in semiconductor manufacturing. In: Win-ter Simulation Conference (S. Chick, P.J. Sanchez, D. Ferrin and D. J. Morrice, Eds.). ACM. pp. 1338–1345.

Roy, B. and B. Sussman (1964). Les probl`emes d’ordonnancement avec contraintes disjonc-tives. Technical report. note DS No 9 bis. SEMA, Paris.

Toba, H., H. Izumi, H. Hatada and T. Chikushima (2005). Dynamic load balancing among mul-tiple fabrication lines through estimation of minimum inter-operation time. IEEE Transactions on Semiconductor Manufactur-ing18(1), 202–213.

Wein, L. M. (1988). Scheduling semiconduc-tor wafer fabrication.IEEE Transactions on Semiconductor Manufacturing1(3), 115–130.

References

Related documents

Multi-level models (SPSS HLM, MLn) Random coefficient models (VARCL) Hierarchical linear models (SPSS HLM). Latent growth models (SEM LISREL, Mx,

at 2465 (internal citations omitted). 16-1466) (“The free rider problem is not merely that nonmembers will benefit from the union’s services without bearing their fair share of

[r]

In line with our hypotheses, smokers showed increased activation associated with attentional bias in the dACC, right DLPFC, and left SPL after placebo, whereas this activation

In a study by Moore et al., 1042 women with benign gynecologic disease were evaluated, and HE4 was less often elevated than CA125 (8% vs. CA125 is often increased in normal

“ Banking Industry Information Model ” – Covers the adoption of the Banking Industry Architecture Network (BIAN) Service Landscape as the enterprise data model for SMU tBank.

Shared components Single sources of reference data Common Service Oriented Architecture (SOA) Common domain and business services model..

First, an increase in the direct investment costs increases the fee charged by the passive fund, which in turn increases the incentives of the passive fund manager to attract