Low Power Vlsi

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LOW POWER VLSI

By,

K.Venkataramana reddy

07c31a0458

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Why worry about power?

--Heat Dissipation

Microprocessor power Consumption

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Why we

go

to Low Power..

PORTABILITY:

Enhanced run-time, Reduced weight, Reduced volume, Low cost operation

High Performance:

Low-cost cooling, Low-cost packaging, Low-cost operation

RELIABILITY:

Avoid thermal problems

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Speed/Power performance for

available Technologies

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Where Does Power Go In CMOS

• Dynamic Power Consumption :

Charging and Discharging Capacitors • Short Circuit Currents :

Short circuit path between supply rails during switching

• Leakage:

Leakage diodes and transistors

P

total

= P

DYN

+ P

SC

+ P

Leakage

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Dynamic

Power Consumption

Energy/transition = C

L

* V

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Dynamic Power Consumption

• Power = Energy / Transition * transition rate

=

• So, power is proportional to V

dd

, f ,C

L

• Power dissipation is data dependent

Function of switching activity

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Reducing V

dd

• Power P is proportional to square of V

• V_DD has decreased in modern processes

– High V_DD would damage modern tiny transistors

– Lower V_DD saves power

• V_DD = 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

• Further decreasing may cause affect to Threshold voltage

• Relatively independent of logic function and style. • Power Delay Product Improves with lowering Vdd. • By reducing Vdd Noise margin will be affected

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Noise Margin

• NML = VIL - VOL

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Power Consumption is Data

Dependent

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

Ex: Static 2 i/p NOR Gate P(A=1) = ½ P(B=1) = ½ Then P(out=1) = ¼ P(out=0) = 1-P(out=1) =1-1/4 = ¾ P(0->1) = P(out=1).P(out=0) = ¾ * ¼ = 3/16

A

B

Y

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Transition Probability of 2-input

NOR Gate

A B

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Two phase operation

Precharge (CLK = 0)

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2 input NOR gate

A

B

Y

0

1

0

1

0

1

0

1

0

P(A=1) = ½ P(B=1) = ½ P(out=0) = ¾ Ceff = ¾ * CL  Switching activity is always Higher in Dynamic Circuits

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Transition Probabilities For

Dynamic GATES

Switching Activity for Precharged Dynamic

Gates

P

0 -> 1

AND

(1-P

a

* P

b

)

OR

(1-P

a

)(1-P

b

)

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Glitching…

• Glitching refers to spurious and unwanted

transitions that occur before a node settle

down to its final steady-state value.

• Glitching often arises when paths with

unbalanced propagation delay converges

at the same point in the circuit.

• The dissipation caused by the spurious

transitions can reach up to 25% of the total

dissipation for some circuits.

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Glitching in Static CMOS

 Each gate has Unit delay  Input A, B, C arrive at same time.  No glitching in dynamic circuits

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Short Circuit Currents

• Short circuit currents are encountered only

in static design.

• In static CMOS circuits the flow current

from VDD to GND during Switching when

both NMOS and PMOS conducting

Simultaneously.

• Such path never exists in a dynamic

circuits.

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Short Circuit Currents

V _out V _in 0.5 1 1.5 2 2.5 0 . 5 1 1 . 5 2 2 . 5 NMOS re s PMOS off NMOS sat PMOS sat NMOS off PMOS res NMOS s at PMOS res NMOS res PMOS sat Vin Vout C_L Vdd I V D D ( m A ) 0.15 0.10 0.05 V_in(V) 5.0 4.0 3.0 2.0 1.0 0.0 Vin Vout C_L Vdd I V D D ( m A ) 0.15 0.10 0.05 V_in(V) 5.0 4.0 3.0 2.0 1.0 0.0 Vin Vout C_L Vdd I V D D ( m A ) 0.15 0.10 0.05 V_in(V) 5.0 4.0 3.0 2.0 1.0 0.0

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Impact of rise/fall time on

Short-Circuit Currents

Large Capacitive Load

 The input through the

transient region before the output start to change

Small capacitive Load

 Output fall time is

Substantially smaller than the input rise time

V _in V _out C _L V _DD V _in V _out C _L V _DD

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Short-Circuit energy as a function

of slope ratio

• Short-Circuit energy dissipation (normalized with respect to zero i/p rise time energy) for a static CMOS.

• The power dissipation due to short circuit

currents is minimized by matching the rise/fall times of the input and output signals.

• Short-Circuit reduced by lower the Supply Voltage.

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Leakage

Sub-Threshold current Dominant factor

Vout Vd d Sub-Threshold Current Drain Junction Leakage

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Static Power Consumption

 Dominates over dynamic consumption

 Not a function of Switching Frequency.

 Reduce switching activity

 Reduce physical capacitance V_in=5V V_{o ut} C_L Vd d I_stat

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System-Level optimization : Power

Management

• In event-driven application, large amounts of power are wasted while the system is in idle-mode.

• The power consumption can be reduced significantly by using power management scheme to shunt down idle component.

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Conclusion

• Thus the low power can be achieved by decreasing Vdd to certain level.

• As leakage current cannot be reduced, the short circuit currents are eliminated by dynamic

circuits.

• The power dissipation due to short circuit

currents is minimized by matching the rise/fall times of the input and output signals

• Glitching makes power to dissipate so it is reduced by cope process

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References

• Digital Integrated Circuits –JAN M.RABAEY • Encyclopedia of computer science and

technology,1995.

• VLSI Design Techniques for Analog and Digital Circuits –Randall L.Geiger, Phillip E.Allen.

• Basic VLSI Design A.PUCKNELL.

• Low-Power CMOS Design “IEEE journal of solid state circuit -pages 472-484,Aprill 1992”.

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