CoE3DJ4
Digital Systems Design
Chapter 4: Timer operation
Timer
• There are two 16-bit timers each with four modes of operation
• Timers are used for (a) interval timing, (b) event counting or (c) baud rate generation for built in serial port
• Each 16-bit timer is in fact an asynchronous counter therefore the 16th or last flip-flop divides the input clock frequency by 216=65536
• The output of last stage clocks an overflow flip-flop
• In interval timing applications, a timer is programmed to overflow at a regular interval and set the timer overflow flag
• Flag is used to synchronize the program to perform an action (e.g., turning on a light)
• Interval timing can be used to measure the elapsed time
TCON and TMOD
• Event counting is used to determine the number of occurrences of an event
• An event is an external stimulus that provides a 1 to 0 transition
• 8051 timers are accessed using six of SFRs (i.e., TCON, TMOD, TL0, TL1, TH0,TH1)
• TMOD register contains two groups of four bits that set the operating mode for Timer 0 and Timer 1
• TMOD is not bit addressable and is loaded once at the beginning of a program to initialize the timer
• TCON contains status bits and control bits for Timer 0 and Timer 1.
TCON and TMOD
• Upper four bits in TCON (TCON.4 to TCON.7) are used to turn timers on and off (TR0,TR1) or signal a timer overflow (TF0,TF1)
• The lower four bits in TCON are used to detect and initiate external interrupts
• THx is used to represent TH0 or TH1
Timer Modes
• Mode 0 is a 13-bit timer mode and is not generally used in new designs
• Timer high-byte (THx) is cascaded with five least-significant bits of the timer low-byte (TLx) to form a 13-bit timer
• Upper three bits of TLx are not sued
• Mode 1 is a 16-bit timer mode
• Clock is applied to combined high and low timer registers (TLx/THx)
• Timer counts up and an overflow occurs on FFFF to 0000 transition and sets the timer overflow flag. The timer
continues to count
• Overflow flag is the TFx bit in TCON
Timer Modes
• Mode 2 is 8-bit auto reload mode
• Timer’s low-byte (TLx) operates as an 8-bit timer while timer high-byte (THx) holds a reload value
• When the count overflows from FF not only the flag is set, but the value in THx is loaded into TLx. Counting continues from this value up to next FF
• Mode 3 is split timer mode and is different for each timer
• Timer 0 in mode 3 is split into two 8-bit timers.
• TL0 and TH0 act as separate timers with overflow setting the TF0 and TF1 bits respectively
• Timer 1 can be switched into one of the other modes. The only limitation is that the usual timer 1 overflow flag TF1, in not affected by Timer 1 since it is connected to TH0.
Clocking sources
• How the timers are clocked?
• There are two sources for clock which can be selected by writing to the counter/timer (C/T) bit in TMOD when the timer is initialized.
• One source is for interval timing and the other one for event counting
• Interval timing: If C/T=0, timer is clocked from on-chip oscillator
– A divide by 12 stage is added to reduce the clocking frequency (for a 12 MHz oscillator the timer clock will be 1 MHz.
Clocking sources
• Event counting: If C/T=1, timer is clocked from an external source
• In most applications, external source supplies timer with a pulse upon the occurrence of an “event”, and the timer is an event counter
• External clock comes through Port 3 pins: P3.4 is the external clocking for Timer 0 and P3.5 is the clocking input for Timer 1.
• In counter applications, timer registers are incremented in response to a 1 to 0 transition
Starting, stopping and controlling timers
• Simplest method for starting and stopping timers is with run- control bit (TRx) in TCON
• TRx is clear after a system reset, therefore, timers are disabled by default
• TRx is set by software to start timers
• Example: to start Timer 0
SETB TR0
• To stop Timer 0:
CLR TR0
• Another method for controlling timers is with GATE bit in TMOD and external input INTx (INT0 and INT1 are on Port 3, pins 2 and 3)
• Setting GATE=1 allows timer to be controlled by INTx
Starting, stopping and controlling timers
• Assume INT1 is low but pulses high for a period of time to be measured.
• Initialize Timer 1 for mode 2, 16 bit timer mode withTL1/TH1=0000H, GATE=1 and TR1=1
• When INT1 goes high, timer is gated on and is clocked at a rate of 1 MHz.
• When INT1 goes low, timer is gated off and duration of pulse in microseconds is the count in TL1/TH1
Initializing and accessing timer registers
• Timers are usually initialized once at the beginning of a program to set the correct operating mode
• Within the body of a program, timers are started, stopped, flag bits tested, cleared, timer registers read or updated and so on.
• Example: MOV TMOD, #00010000 B
– This instruction sets M1=0, M0=1 (for mode 1), leave C/T=0 and GATE=0, for internal clocking and clear Timer 0 mode bit). Timer will not begin working until TR1 is set
• If an initial count is necessary timer registers (e.g., TL1/TH1) must also be initialized. Timer counts up and sets the
overflow flag on an FFFFH to 0000H transition
Initializing and accessing timer registers
• Example: a 100 us interval could be timed by initializing TL1/TH1 to 100 counts less than 0000H which is FF9CH.
MOV TL1,#9CH MOV TH1,#FFH SETB TR1
– Overflow flag is automatically set 100 us later. A loop can check to see when the overflow flag is set
WAIT: JNB TF1, WAIT
– When timer overflows, it is necessary to stop timer and clear the overflow flag:
CLR TR1 CLR TF1
Initializing and accessing timer registers
• In some applications it is necessary to read the value in timer registers on the fly
• Possible problem: if we read the low byte first and the high byte second and between these two reads the low byte
overflows into high byte we have a wrong read value
• Solution: Read high-byte first, then low-byte and read high- byte again. If high-byte has changed repeat read operation AGAIN: MOV A, TH1
MOV R6,TL1
CJNE A, TH1, AGAIN MOV R7,A
Short intervals and long intervals
• Write a program that creates a periodic waveform on P1.0 with as high a frequency as possible. What are frequency and duty cycle of waveform?
LOOP: SETB P1.0 CLR P1.0
SJUMP LOOP
• Creates a pulse waveform on P1.0 with a period of 4 us. Signal is high for 1 us (duty cycle of 25%)
• Period of waveform can be lengthened by inserting NOP instructions into loop
16 bit timer plus software loops No limit
16 bit timer 65536
8-bit timer with auto reload 256
Software tuning 10
Technique Interval in microseconds
Short intervals and long intervals
• Example: Write a program using Timer 0 to create a 10 kHz square wave on P1.0
MOV TMOD,#02H MOV TH0,#,-50 SETB TR0
LOOP: JNB TF0, LOOP CLR TF0
CPL P1.0 SJMP LOOP
• This program creates a square wave on P1.0 with a high-time of 50 us and low time of 50 us.
• CPL is a complement bit instruction
Short intervals and long intervals
• Example: write a program using timer 0 to create a 1 kHz square wave on P1.0
MOV TMOD,#01H
LOOP: MOV TH0,#FEH
MOV TL0,#0CH SETB TR0
WAIT: JNB TF0,WAIT
CLR TR0 CLR TF0 CPL P1.0 SJMP LOOP
– A 1kHz square wave requires a high time of 500 us and a low time of 500 us.
Sine the interval is longer than 256 us, mode 2 cannot be used. Mode 1 (16 bit) is required.
Short intervals and long intervals
• Example: A buzzer is connected to P1.7, and a debounced switch is connected to P1.6. Write a program that reads logic level provided by the switch and sounds the buzzer for 1
second for each 1 to 0 transition detected.
HUNDRED EQU 100 COUNT EQU -10000 ORG 8100H
MOV TMOD, #01H LOOP: JNB P1.6, LOOP WAIT: JB P1.6, WAIT
SETB P1.7 CALL DELAY CLR P1.7
SJMP LOOP
DELAY: MOV R7,#HUNDRED AGAIN: MOV TH0,#HIGH CONT
MOV TL0,#LOW COUNT SETB TR0
WAIT2: JNB TF0,WAIT2 CLR TF0
CLR TR0
DJNZ R7,AGAIN RET
END
