CSE140: Components and Design Techniques for Digital Systems

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Sources: TSR, Katz, Boriello & Vahid

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CSE140: Components and Design Techniques

for Digital Systems

Tajana Simunic Rosing

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Where we are now

• What we’ve covered so far

(Chap 1-5, App. A& B)

– Number representations

– Boolean algebra

– SOP and POS

– Logic minimization using K-maps

– Two and multi-level implementation

– Hazards

– AOI, PAL, PLA, ROM implementation

– Mux and Demux

– Adders, Multipliers and ALUs

• What comes next:

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K-maps, hazards, muxes & NOR-only

3 A D C B F(A,B,C,D)=Π M(2, 3, 6, 8, 9, 12, 13, 14)

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Demultiplexers as general-purpose logic

F1 = A'BC'D + A'B'CD + ABCD

F2 = ABC'D' + ABC

F3 = (A' + B' + C' + D')

A B 0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD' 15 ABCD 4:16 DEC Enable C D

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PLA implementation

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ALU bitslice design

6 S₁ S₀ ALU Operations 0 0 -A (Two’s complement of A) 0 1 -B (Two’s complement of B) 1 0 A-B 1 1 A+B

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CSE140: Components and Design Techniques

for Digital Systems

Latches and flip-flops

Tajana Simunic Rosing

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"remember" "load"

"data" "stored value"

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Flight attendant call button

• Flight attendant call button

– Press call: light turns on

• Stays on after button released – Press cancel: light turns off

– Logic gate circuit to implement this? Q Call Cancel a a 3.2 Bit Storage Blue light Call button Cancel button

1. Call button pressed – light turns on

Bit Storage Blue light Call button Cancel button

2. Call button released – light stays on

Bit Storage Blue light Call button Cancel button

3. Cancel button pressed – light turns off

• SR latch works

– Call=1 : sets Q to 1 and keeps at 1 – Cancel=1 : resets Q to 0 R S Q Call but t on Blue light Cancel but t on

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What if a kid presses both call and cancel?

• If S=1 and R=1 at the same time and then released, Q=?

– Can also occur also due to different delays of different paths

– Q may oscillate and eventually settle to 1 or 0 due to diff. path delay

R=1 S=1 0 0 0 0 t Q R=0 S=0 0 0 1 1 t Q R=0 S=0 1 1 0 0 t Q 0 1 0 1 0 1 0 1 S R Q t R S Q Call but t on Blue light Cancel but t on

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Theoretical R-S latch state behavior

• State diagram

– states: possible values – transitions: changes

based on inputs

• Hard to observe SR in the 1-1 state

– one of R or S usually changes first

• non-deterministic transition to state 0-1 or 1-0; a "race condition“; on SR=00 goes to either 01 or 10 Q Q' 0 1 Q Q'1 0 Q Q' 0 0 Q Q' 1 1 SR=00 SR=11 SR=00 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=11 SR=10 SR=01 SR=01 SR=10 SR=11 possible oscillation

between states 00 and 11 R S Q Q' S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable

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Sources: TSR, Katz, Boriello & Vahid 12 Q(t+∆) R S Q(t) S R Q(t) Q(t+∆) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X hold reset set

not allowed characteristic equation

Q(t+∆) = S + R’ Q(t)

R-S latch analysis

• Break feedback path

R S Q Q' 0 0 1 0 X 1 X 1 Q(t) R S

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Oscillation solution: Level-Sensitive SR Latch

• Add input “C”

– Change C to 1 only after S and R are stable

R1 S1 S C R Level-sensitive SR latch Q

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Clocks

• Clock -- Pulsing signal for enabling latches; ticks like a clock • Synchronous circuit: sequential circuit with a clock

• Clock period: time btwn pulse starts

– Above signal: period = 20 ns

• Clock cycle: one such time interval

– Above signal shows 3.5 clock cycles

• Clock duty cycle: time clock is high

– 50% in this case

• Clock frequency: 1/period

– Above : freq = 1 / 20ns = 50MHz; 100 GHz 10 GHz 1 GHz 100 MHz 10 MHz 0.01 ns 0.1 ns 1 ns 10 ns 100 ns Period Freq

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Level-Sensitive D Latch

• SR latch requires careful design so SR=11 never occurs

• D latch relieves designer of that burden

– Inserted inverter ensures R always opposite of S

R S D C D latch Q 1 0 D C S R Q 1 0 1 0 1 0 1 0 D Q’ Q C

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Problem with Level-Sensitive D Latch

• D latch still has problem (as does SR latch)

– When C=1, through how many latches will a signal travel?

D1 Q1 D2 Q2 D3 Q3 D4 C4 C3 C2 C1 Q4 Y Clk Clk_A Clk_B

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Master-slave structure: Flip-Flop

• Break flow by alternating clocks (like an air-lock)

– use positive clock to latch inputs into one R-S latch

– use negative clock to change outputs with another R-S latch

• View pair as one basic unit

– output changes a few gate delays after the falling edge of clock

but does not affect any cascaded flip-flops

master stage slave stage

P P’ CLK R S Q Q’ R S Q Q’ R S

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D Flip-Flop

• Flip-flop

: Bit storage that stores on clock edge, not level

• Master-slave design:

– So master loaded when C=0, then slave when C=1

Clk D/Dm Qm/Ds Cm Cs Qs D latch master D latch servant D Dm Ds Cs Qm Qs’ Qs Q Q’ Cm Clk D flip-flop

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Sources: TSR, Katz, Boriello & Vahid 19

D Flip-Flop

D Q’ Q Q’ D Q

Symbol for rising-edge triggered D flip-flop

Symbol for falling-edge triggered D flip-flop

Clk

rising edges

Clk

falling edges

Internal design: Just invert servant clock rather than master The triangle

means clock input, edge triggered

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D Flip-Flop

• Solves problem of not knowing through how many latches a signal

travels when C=1

Two latches inside each flip-flop

D1 Q1 D2 Q2 D3 Q3 D4 Q4

Y

Clk

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Sources: TSR, Katz, Boriello & Vahid 21 D Q CLK positive edge-triggered flip-flop D Q G CLK transparent (level-sensitive) latch D CLK Qedge Qlatch

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Flip-Flop Types

• SR flip-flop: like SR latch, but edge triggered

• JK flip-flop: like SR (SJ, RK)

– But when JK=11, toggles

– 10, 01

• T flip-flop: JK with inputs tied together

– Toggles on every rising clock edge

• Previously utilized to minimize logic outside flip-flop

– Today, minimizing logic to such extent is not as important

– D flip-flops are thus by far the most common

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Flip-Flop Set, Reset and Active Hi/Low Inputs

– Synchronous reset: clears Q to 0 on next clock edge

– Synchronous set: sets Q to 1 on next clock edge

– Asynchronous reset: clear Q to 0 immediately - see diagram

– Asynchronous set: set Q to 1 immediately

D Q’ Q R Q’ AR D Q Q’ AS AR D Q

cycle 1 cycle 2 cycle 3 cycle 4 clk D AR Q D Q’ Q R

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Flip-flop features

• Reset (set state to 0) – R

– synchronous: – asynchronous:

• Preset or set (set state to 1) – S (or sometimes P)

– synchronous:

– asynchronous:

• Both reset and preset (set and reset dominant)

– Dnew =

• Selective input capability (input enable or load) – LD or EN

– multiplexor at input:

– load may or may not override reset/set (usually R/S have priority)

• Complementary outputs – Q and Q'

• Reset (set state to 0) – R

– synchronous: Dnew = R' • Dold (when next clock edge arrives) – asynchronous: doesn't wait for clock

• Preset or set (set state to 1) – S (or sometimes P)

– synchronous: Dnew = Dold + S (when next clock edge arrives) – asynchronous: doesn't wait for clock

• Both reset and preset

– Dnew = R' • Dold + S (set-dominant)

– Dnew = R' • Dold + R'S (reset-dominant)

• Selective input capability (input enable or load) – LD or EN

– multiplexor at input: Dnew = LD' • Q + LD • Dold

– load may or may not override reset/set (usually R/S have priority)

• Complementary outputs – Q and Q'

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Sources: TSR, Katz, Boriello & Vahid 25 Q D Clk=1 R S 0 D’ 0 D’ _D

Q’ negative edge-triggered D _{flip-flop (D-FF)} 4-5 gate delays

must respect setup and hold time constraints to successfully

capture input characteristic equation

Q(t+1) = D holds D’ when

clock goes low

holds D when clock goes low

Negative edge-triggered flip-flop

• Efficient solution: only 6 gates

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Non-Ideal Flip-Flop Behavior

• Can’t change flip-flop input too close to clock edge

– Setup time: time that D must be stable before edge • Else, stable value not present at internal latch

– Hold time: time that D must be held stable after edge

• Else, new value doesn’t have time to loop around and stabilize in internal latch

clk D clk D setup time hold time R S D C u D latch Q Q’ 1 2 3 4 5 6 7 C D S u R Q’ Q

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Sources: TSR, Katz, Boriello & Vahid 27 clock data D Q D Q

Timing: Definitions

• Setup time

– minimum time before the clocking event by which the input must be stable (Tsu)

• Hold time:

– minimum time after the clocking event until which the input must remain stable (Th)

• Propagation delay

– Amount of time for value to propagate from input to output (Tpd) D Clk Q T _su 1.8 ns T _h 0.5 ns T _w 3.3 ns T _pd 3.6 ns 1.1 ns T _su 1.8 ns T _h 0.5 ns T _pd 3.6 ns 1.1 ns T _w 3.3 ns

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Bit Storage Overview

D flip-flop D latch master D latch servant Dm Qm Cm Ds D Clk Qs’ Cs Qs Q’ Q S R D Q C D latch

Feature: Only loads D value present at rising clock edge, so values can’t propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR – but gate count is less of an issue today.

Feature: SR can’t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store. S1 R1 S Q C R Level-sensitive SR latch

Feature: S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. R (reset) S (set) Q SR latch Feature: S=1 sets Q to 1, R=1 resets Q to 0. Problem: SR=11 yield undefined Q.

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Comparison of latches and flip-flops

Type When inputs are sampled When output is valid

unclocked latch level-sensitive latch master-slave flip-flop negative edge-triggered flip-flop

Type When inputs are sampled When output is valid

unclocked always propagation delay from input change

latch

level-sensitive clock high propagation delay from input change

latch (Tsu/Th around falling or clock edge (whichever is later)

edge of clock)

master-slave clock high propagation delay from falling edge

flip-flop (Tsu/Th around falling of clock

edge of clock)

negative clock hi-to-lo transition propagation delay from falling edge

edge-triggered (Tsu/Th around falling of clock