8.1 Objectives
• To design digital counter circuits using JK-Flip-Flop. • To implement counter using 74LS193 IC.
8.2 Introduction
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. Flip-flops are introduced and connected to make a counter. The number of flip-flops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle.
Counters can be classified into two broad categories: a. Synchronous counters
b. Asynchronous counters
8.3 Synchronous Counters
In synchronous counter all clocks of flip-flops are connected to the same clock signal. Thus, all flip-flop outputs change state at precisely the same moment. Table 8.1 shows the states of a 2-bit counter. Each state is an increment to its previous state by 1, which means that the counter is an up counter. It is clear from the table that the first flip-flop (FF0) toggles at the clock edge (either rising or falling), according to this, this part of the counter is implemented using T flip-flop and its input is always at high logic. The second flip-flop (FF1) toggles if the output of FF0 is 1. Then this part of the counter is also implemented with T flip-flop but with its input connected to the output of the previous flip-flop.
Table 8.1: 2-bit counter. Q1 Q0 0 0 0 1 1 0 1 1
Figure 8.1: 2-bit synchronous counter.
8.4 Asynchronous Counters
In asynchronous counter only the first flip-flop (least significant flip-flop) FF0 is clocked by a clock signal. The clock of the next flip-flops is triggered from the output of the previous flip-flop. The inherent delay in the flip-flop IC (time since the clock trigger until the signal appears on the output) causes Q1 to be triggered after Q0. Thus the transition of the Q output of the flip-flops can never occur at exactly the same time.
Asynchronous counters are also implemented using T flip-flop. The inputs to all flip-flops are connected to logic high and only the clock signal decides if the flip-flop shall toggle, according to the output of the previous flip-flop. The implementation of a 2-bit asynchronous up counter is shown in Figure 8.2.
Figure 8.2: 2-bit asynchronous counter circuit and timing diagram.
Notice that the small delay between the CLK, Q0 and Q1 transitions is not shown in the timing diagram of Figure 8.2.
For an asynchronous counter to become an up/down counter the circuit in Figure 8.3 is connected to the clock of each flip-flop (except FF0 of course because it is connected to CLK).
Figure 8.3: Up/Down logic for asynchronous counters.
8.5 Counter Circuits Design Procedure
The design procedure of counter circuits depends on the counter type. For asynchronous counter it is straight forward and it is explained through the following example.
Example 8.1
Design a logic circuit that counts from 0 to 15 using asynchronous counter. Table 8.2: 4 bit counter.
Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0
Solution:
To count from 0 to 15 there is 16 states which mean 4 flip-flops are needed. By default when designing asynchronous counters, all flip-flop inputs are connected to 1 and only the first flip-flop is trigger with a clock input. By inspecting Table 8.2,
Q1 is toggled when Q0 changes from1 to 0. Q2 is toggled when Q1 changes from 1 to 0. Q3 is toggled when Q2 changes from 1 to 0.
The counter logic circuit is shown in Figure 8.4.
Figure 8.4: Asynchronous 4-bit counter of Example 8.1
For synchronous counter, the design procedure is the same procedure of designing using flip-flops, starting from the state diagram and ending with the logic circuit.
Example 8.2
Design a logic circuit that counts from 0 to 4 then back to 0 only if an input signal is 1. Use synchronous counter.
Solution:
Step one: Figure 8.5 shows the state diagram.
Step two and three: The state and excitation tables are shown in table 8.3.
Table 8.3: State and excitation tables of Example 8.2.
Step four: Construct K-maps for each flip-flop inputs (J and K)
Figure 8.6: K-map for J0 in Example 8.2. J0=U
Current state Input Next state Flip flop 1 Flip flop 0
Q1 Q0 U Q1+ Q0+ J1 K1 J0 K0 0 0 0 0 0 0 X 0 X 0 0 1 0 1 0 X 1 X 0 1 0 0 1 0 X X 0 0 1 1 1 0 1 X X 1 1 0 0 1 0 X 0 0 X 1 0 1 1 1 X 0 1 X 1 1 0 1 1 X 0 X 0 1 1 1 0 0 X 1 X 1
Figure 8.7: K-map for K0 in Example 8.2. K0= U
Notice that even though the implementation is with JK flip-flop the result is that K0=J0 then it is a T flip-flop.
Figure 8.8: K-map for J1=K1 in Example 8.2. J1=K1=Q0.U
Pre-Lab 8
1- Design a synchronous counter that counts from 0 to 7 if an input R is high and from 7 to 0 if the input R is low.
You are required to draw the state diagram, the state table, the excitation table. Then to obtain the inputs to the flip-flops (J1, K1, J2, ……… and so on). But you are NOT required to draw the counter logic circuit.
Lab Work 8
Use the synchronous 4-bit counter IC 74ls193 and 3*8 decoder IC 74ls138 to implement a counter that counts from 2 to 5.
Homework 8
1. Design a 2 bit asynchronous up counter using the JK flip flop shown in Figure 8.10 (take care that the flip flop has a rising edge clock).
Figure 8.10: Positive edge JK-flip flop
2. Using the 74193 4-bit counter you used during your lab work, design an up counter that counts from 2 to 12. To detect the presence of 12, you may use active low 3*8 decoder.
Figure 8.11: 74193 up down counter.
3. Using the 74193 4-bit counter you used during your lab work, design an up/down counter that will count up if an input X is 1 and will count down if X is 0. You can use ON LY one clock for both the COUNT UP and the COUNT DOWN terminals.
