3 The TTL NAND Gate. Fig. 3.1 Multiple Input Emitter Structure of TTL

3

The TTL NAND Gate

3.1

TTL NAND Gate Circuit Structure

The circuit structure is identical to the previous TTL inverter circuit except for the multiple emitter input transistor. This is used to implement a diode switching structure in active transistor form using parallel junction diffusions for several emitters.

Fig. 3.1 Multiple Input Emitter Structure of TTL

If any input is low, the corresponding base-emitter junction becomes forward-biased and the transistor conducts. The other characteristics of the circuit and its transfer characteristic are identical to those of the inverter circuit.

3.2

Logical Operation

A table of conduction states can be drawn up showing the state of each transistor in the circuit for all possible input conditions as before to verify the logic function performed. The direction of conduction of T1 can be in the forward or reverse mode so this should also be noted in the table. It can be seen from the table that the output goes LO only when both inputs are HI which verifies the NAND function.

IN1 IN2 T1 T2 T3 T4 D OUPUT LO LO ONfor OFF OFF ON ON HI LO HI ONfor OFF OFF ON ON HI HI LO ON OFF OFF ON ON HI

⇒

⇒

⇒

⇒

Fig. 3.2 Circuit Diagram of a Standard 2-input TTL NAND Gate N7 N6 N5 N4 N3 N2 N1 Ω k 1 R₂ Ω 130 R₃ Ω k 6 . 1 R₁ Ω k 4 R_B 1

T

3.3. Circuit Analysis

It is of interest to examine the conditions for the different logic states of the NAND Gate circuit, particularly with regard to estimating the power consumption in each state. This can be done by first establishing the voltages at each of the nodes N1 – N7 in the circuit and then finding the total current drawn from the power supply.

(a) At Least One Input LO – Output HI

To aid in the analysis, the NAND Gate circuit can be redrawn with the transistors which are non-conducting or OFF removed from the circuit as shown in Fig. 3.3. Then the potentials, relative to ground, can be determined for each of the nodes in turn. Under this condition, T1 is ON in forward mode, T2 is OFF, T3 is OFF, while T4 is ON at the point of cut-in and therefore T2 and T3 have been removed from the circuit.

I3 I1 IB 0.1 V Output (no load) N7 N6 N5 N4 N3 N2 N1 Ω k 1 R₂ Ω 130 R₃ Ω k 6 . 1 R₁ Ω k 4 R_B 1

T

(i) T1 ON in forward mode and is operating in saturation as there is only a leakage current from T2 available as collector current, i.e. T1 operates with a large base current and negligible collector current where IC MAX = 0. The input logic LO voltage is taken as 0.1V. Then:

V

9

.

0

8

.

0

1

.

0

V

V

V

:

N1

Node

₌

₊

₌

₊

₌

(ii) With T1 operating in saturation, its collector-emitter voltage is VCE SAT = 0.1V so that:

Node

N2

:

V

=

V

+

V

=

0.1

+

0.1

=

0.2V

(iii) With T4 operating at the point of cut-in its base current and hence its collector current can

be taken as zero. This means that there is no voltage drop across either resistor R1 or R3

and so the potential at both sides of these resistors is equal to the supply voltage VCC giving:

5V

V

V

V

:

N5

Node

N3,

Node

₌

₌

₌

(iv) Node N4 is pulled low by the resistor R2 which has no current flowing through it so that:

0V

V

:

N4

Node

₌

(v) Finally, with T4 operating at the point of cut-in:

4.4V

0.6

5

V

V

V

:

N6

Node

₌

₋

₌

₋

₌

and with the diode at cut-in also:

4.0V

0.4

4.4

V

V

V

:

N7

Node

₌

₋

₌

₋

₌

The current drawn from the supply can then be obtained as:

1.025mA

4kΩ

0.9V

5

R

V

V

I

=

−

=

−

=

with I1 and I3 = 0 since negligible current flows into the base or collector of T4 while at the point of cut-in.

The power consumption of the gate with the output in the logic Hi state can then be obtained as:

5.125mW

1.025mA

x

5V

I

x

V

P

₌

₌

₌

(b) Both Inputs HI – Output LO

Under this condition T1 is ON in the reverse mode, T2 is ON, T3 is ON and T4 is OFF. Fig. 3.4 shows the NAND gate circuit redrawn with T4 removed. Potentials must be determined in a different order this time.

5V 5V N7 N6 N5 N4 N3 N2 N1 Ω 130 R₃ Ω k 6 . 1 R₁ Ω k 4 R_B 1

T

I

I

I

(i) With T3 ON and operating in saturation:

V

8

.

0

V

V

:

N4

Node

₌

₌

(ii) With T2 also ON and in saturation:

1.6V

0.8

0.8

V

V

V

:

N2

Node

₌

₊

₌

₊

₌

(iii) Since T1 is ON in the reverse mode, the base-collector voltage in this mode can be taken as the same as the base-emitter voltage of a transistor operating in the forward active mode so that:

2.3V

0.7

1.6

V

V

V

:

N1

Node

₌

₊

₌

₊

₌

(iv) With T2 operating in saturation, its collector emitter voltage will be VCE SAT = 0.1V so that:

0.9V

0.1

0.8

V

V

V

:

N3

Node

₌

₊

₌

₊

₌

(v) With T4 OFF no current will flow through resistor R3 and consequently Node N5 will be pulled up to the supply rail voltage:

5V

V

V

:

N5

Node

₌

₌

(vi) With T3 ON and in saturation, its collector-base voltage will be at a saturation value so that the output voltage at Node N7 is simply:

0.1V

V

V

:

N7

Node

₌

₌

(vii) With T4 and the diode non-conducting, the potential at Node N6 is somewhat ill-defined and depends on the resistances of the non-conducting junctions of these devices but will lie somewhere between that of Nodes N3 and N7, i.e. between 0.1 and 0.9V. However, this voltage is not significant.

The current drawn from the supply this time is given by the sum of IB and I1 with I3 = 0: Then:

0.675mA

4kΩ

2.3V

5

R

V

V

I

=

−

=

−

=

2.56mA

1.6kΩ

0.9V

5

R

V

V

I

=

−

=

−

=

The power consumption when the output is LO is then given as:

16.175mW

2.56)

0.675

(

x

5

)

I

(I

x

V

P

₌

₊

₌

₊

₌

If the NAND gate is assumed to spend half of its time in each logic state then the average power consumption can be expressed as:

10.56mW

2

16.175

5.125

2

P

P

P

=

+

=

+

=