INFORMATICA INDUSTRIALE

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INFORMATICA INDUSTRIALE

Lezione 5

Prof. Christian Forlani

[email protected]

Informatica Industriale

Device Structure:

Peripherals

» I/O

» Parallel Slave Port (PSP)

» Timer

» Capture/Compare/PWM (CCP)

» Serial Slave Port (SSP)

» Master Synchronous Serial Port (MSSP)

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Lezione 5 3

PIC-USART MODULE

(Universal Synchronous Asynchronous Receiver Transmitter)

• Full-duplex Asynchronous Or Half-duplex Synchronous

• 9-bit Addressable mode

• Double-buffered transmit and receive buffers

• Separate transmit and receive interrupts

• Dedicated baud rate generator

RS232

(http://www.tanzilli.com)

Cos'e' e a cosa serve l'RS232

• Lo standard RS232 definisce una serie di specifiche per la trasmissione seriale di dati tra due dispositivi denominati DTE (Data Terminal Equipment) e DCE (Data

Communication Equipment). Come si può vagamente intuire dal nome, il Data Communication Equipment e' un dispositivo che si occupa di gestire una comunicazione dati mentre il Data Terminal Equipment e' un dispositivo che si occupa di generare o ricevere dati.

La comunicazione seriale asincrona

• Per consentire la trasmissione di dati tra il PC ed il modem, lo standard RS232 definisce una serie di specifiche elettriche e meccaniche. Una di queste riguarda il tipo di comunicazione seriale che si vuole implementare che può essere sincrona o asincrona. Nel nostro caso analizzeremo solo la comunicazione seriale asincrona.

RS232 RS232

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Lezione 5 5

Standard RS232

RS232 Voltage levels TTL Voltage levels

5V

0V

Logic ‘0’

Logic ‘1’

Codifica seriale del numero 48 = 0b00110000 a 9600 bps (RS-232 8n2)

stop

USART Block Diagram

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Lezione 5 7

UART Tx Setup

CSRC Clock Source Selection (synch mode only) 1 = Master mode, clock generated by internal BRG 0 = Slave mode, clock derived from external TX9 9-bit / 8-bit Mode Transmission Selection

1 = 9-bit Transmission Format 0 = 8-bit Transmission Format

TXEN Transmit Enable (overridden by SREN/CREN in SYNC mode) 1 = Transmitter Enabled

0 = Transmitter Disabled

SYNC Synchronous / Asynchronous Selection 1 = Synchronous Mode

0 = Asynchronous Mode

BRGH High / Low Baud Rate Selection 1 = High Speed Baud Rate, FOSC / 16 0 = Low Speed Baud Rate, FOSC / 64 TRMT Transmit Shift Register Status

1 = Transmit Shift Register Empty 0 = Transmit Shift Register Full

TX9D 9th Bit of Transmit Data (valid only in 9-bit mode) Written before TXREG, used for parity or address/data

UART Rx Setup

SPEN Serial Port Enable

1 = Serial Port Enabled, Uses RX and TX as serial port pins 0 = Serial Pore Disabled, RX and TX general purpose I/Os RX9 9-bit / 8-bit Mode Reception Selection

1 = 9-bit Reception Format 0 = 8-bit Reception Format

SREN Single Receive Enable (Synchronous Mode Only) 1 = Enable a Single Receive

0 = Disable Single Receive, cleared when reception completed CREN Continuous Receive Enable

1 = Enables Receiver; Continuous Reception in Synch mode, overriding SREN 0 = Disables Receiver in Asynchronous Mode, SREN controls Synch mode ADDEN Address Detect Enable

1 = Enables 9-bit Address Detection, Interrupt and load RCREG when bit 9 is ‘1’

0 = Disables Address Detection, all bytes received FERR Framing Error

1 = Framing Error Occurred in this byte, clear by read RCREG + receive next byte 0 = No Framing Error

OERR Overrun Error

1 = Overrun Error, cleared by clearing CREN 0 = No Overrun Error

RX9D 9th Bit of Received Data (valid only in 9-bit mode) Read before TXREG, used for parity or address/data

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Lezione 5 9

Baud Rate Generator

Esempio Usart TX

void putchar(value) {

while (PIR1bits.TXIF == 0);// Wait for empty FIFO TXREG = value;

}

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Lezione 5 11

MCC18 USART

PIC MSSP MODULE

(MASTER SYNCHRONOUS SERIAL PORT)

SPI

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Lezione 5 13

SPI

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Lezione 5 15

MCC18 SPI

PIC MSSP MODULE

(MASTER SYNCHRONOUS SERIAL PORT)

I ² C BUS

Cos’è:

• sistema di comunicazione che utilizza solo 2 linee bidirezionali (SDA, SCL): BUS

• permette il collegamento di molti dispositivi sulla stessa linea sia master che slave a differenza del protocollo RS232 (point 2 point)

• l’aggiunta/rimozione di dispositivi non pregiudica il funzionamento

del sistema già esistente

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Lezione 5 17

I ² C BUS

5.0 BIT TRANSFER

Due to the variety of different technology devices (CMOS, NMOS,bipolar) which can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’

(HIGH) are not fixed and depend on the

associated level of VDD (see Section 15.0 for Electrical Specifications). One clock pulse is generated for each data bit transferred.

5.1 Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Figure 5).

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Lezione 5 19

I ² C BUS

5.2 START and STOP conditions

Within the procedure of the I²C-bus, unique situations arise which are defined as START and STOP conditions (see Figure 6).

A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.

A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master.

The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is specified in Section 15.0.

Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period in order to sense the transition.

I ² C BUS

6.2 Acknowledge

Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.

The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse .

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Lezione 5 21

PIC I ² C BUS

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Lezione 5 23

MCC18 I ² C BUS

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INFORMATICA INDUSTRIALE