Integrated Circuits & Systems

(1)

Lecture 11

MOSFET – part 2

Prof. José Luís Güntzel

[email protected]

Integrated Circuits & Systems

INE 5442

Federal University of Santa Catarina

Center for Technology

Computer Science & Electronics Engineering

(2)

MOSFET

Lecture 11 – 2012/2 Prof. José Luís Güntzel INE/CTC/UFSC

Integrated Circuits and Systems Slide 11.2

I _D -V _DS Characteristics of NMOS (I-V Curves)

Long-channel NMOS (W/L = 1.5 and L_d=10 µm) Short-channel NMOS (W/L=1.5 and L_d=0.25 µm)

Source: Rabaey; Chandrakasan; Nikolic, 2003

-4

0 0.5 1 1.5 2 2.5

x 10

V_GS= 2.5 V

V_GS= 2.0 V

V_GS= 1.5 V

V_GS= 1.0 V

Velocity Saturation

Linear dependence on VGS

V_DS = V_GS - V_T

€

V_DSAT =κ(V_GT)V_GT

V_DS (V) ID (A

0 0.5 1 1.5 2 2.5

0 1 2 3 4 5 6x 10^-4

V_GS= 2.5 V

V_GS= 2.0 V

V_GS= 1.5 V

V_GS= 1.0 V

Resistive

^Saturation

V_DS = V_GS - V_T

Quadratic dependence on VGS

V_DS (V) ID (A

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MOSFET

I _D -V _GS Characteristics of NMOS (I-V Curves)

0 0.5 1 1.5 2 2.5

0 1 2 3 4 5 6x 10^-4

quadratic

ID (A)

V_GS (V)

0 0.5 1 1.5 2 2.5

0 0.5 1 1.5

2 2.5x 10^-4

quadratic linear

V_GS (V) ID (A

Long-channel NMOS (W/L = 1.5 and L_d=10 µm) Short-channel NMOS (W/L=1.5 and L_d=0.25 µm) V_DS= 2.5 V (NMOS devices are saturated)

Subthreshold conductance

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MOSFET

-2.5! -2! -1.5! -1! -0.5! 0!

-1!

-0.8!

-0.6!

-0.4!

-0.2!

0!^{x 10}!^-4!

V_GS = -1.0V V_GS = -1.5V

V_GS = -2.0V

V_GS = -2.5V

V_DS (V) ID (A

The polarities of all voltages and currents are reversed

Short-channel PMOS (W_d=0.375 and L_d=0.25 µm, W/L=1.5 )

I _D -V _DS Characteristics of PMOS

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MOSFET

NMOS x PMOS (I-V Curves)

Velocity saturation is less pronounced in PMOS (due to higher value of critical electrical field, resulting

from smaller mobility of holes)

-4

0 0.5 1 1.5 2 2.5

x 10

V_GS= 2.5 V

V_GS= 2.0 V

V_GS= 1.5 V

V_GS= 1.0 V

Velocity Saturation

V_DS = V_GS - V_T

€

V_DSAT =κ(V_GT)V_GT

V_DS (V) ID (A

-2.5! -2! -1.5! -1! -0.5! 0!

-1!

-0.8!

-0.6!

-0.4!

-0.2!

0!^{x 10}!^-4!

V_GS = -1.0V V_GS = -1.5V

V_GS = -2.0V

V_GS = -2.5V

V_DS (V) ID (A

Minimum-size (short-channel) NMOS and PMOS (W_d=0.375 and L_d=0.25 µm, W/L=1.5 )

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MOSFET

Simple Model for Manual Analysis

S D

G

B

A Single Current Source Using First-Order Expressions

Employs 5 parameters, which are positive for NMOS and negative for PMOS:

V_T0, V_DSAT , , ,

€

k'

_n

€

λ

€

γ

(7)

MOSFET

Simple Model versus Spice

0 0.5 1 1.5 2 2.5

0 0.5 1 1.5 2

2.5 x 10^-4

V_DS (V)

I D (A)

Velocity Saturated Linear

Saturated

V_DSAT=V_GT V_DS=V_DSAT

V_DS=V_GT

Minimum-size NMOS (W_d=0.375 and L_d=0.25 µm, W/L=1.5 )

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MOSFET

Parameters for Manual Analysis

Minimum-size NMOS (W_d=0.375 and L_d=0.25 µm)

V_T0(V) (V^0.5) V_DSAT(V) k’(A/V²) (V^-1)

NMOS 0.43 0.4 0.63 115 x 10^-6 0.06

PMOS −0.4 −0.4 −1 −30 x 10^-6 −0.1

€

λ

€

γ

Notice: parameters to match well in the (V_DS=2.5V, V_GS=2.5V) region of 0.25µm NMOS

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MOSFET

Experimental setup

I_D

S

G B

+

-

[0,3.3] step 0,5 V

+

-

[0,3.3] step 0,050 V

D

2

3 1

1

+

VDD = 3.3 V

-

+ -

V

_GS

+ -

V

_DS

Determining the I-D Curves of PMOS

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MOSFET

•  Circuit description (SPICE) – PMOS1.cir

–  http://www.inf.ufsc.br/~guntzel/ine5442/parametros

Determining the I-D Curves of PMOS

Also available NMOS1.cir

SpiceOpus (c) 6 -> source PMOS1.cir

SpiceOpus (c) 7 -> dc v3 0 3.3 50m v2 0 3.3 0.5

SpiceOpus (c) 8 -> plot i(v3) xlabel VD[V] ylabel ID[A]

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MOSFET

SpiceOpus (c) 1 -> source PMOS1.cir SpiceOpus (c) 2 -> setplot

new New plot

Current const Constant values (constants)

SpiceOpus (c) 3 -> dc v3 0 3.3 50m v2 0 3 0.5

SpiceOpus (c) 4 -> plot 1000*i(v3) xlabel VD[V] ylabel ID [mA]

V_GS=-3.3 V

V_GS=-2.3 V

V_GS=-2.8 V

V_GS=-1.8 V V_GS=-1.3 V

Determining the I-D Curves of PMOS

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MOSFET

The Transistor as a Switch (“Zero-Order Model”)

Source: Rabaey; Chandrakasan; Nikolic, 2003 & Galup, Schneider 2010

R_on

S D

V_GS ≥ V_T ^|VGS|

Non-ideal switch

Actual NMOS

?

What is the value of R_on? Abrupt transition from on to off?

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MOSFET

The Transistor as a Switch (“Zero-Order Model”)

I_DSAT

V_DD

V_DS(V_DDV_DD/2)

I_D

V_DS> V_DSAT : transistor is in velocity

saturation

or

with Resistance is inversely proportional to W/L

(14)

MOSFET

The Transistor as a Switch

For V_DD >> V_T + V_DSAT/2, R_eq is practically independent of V_DD Once V_DD achieves V_T, R_eq increases significantly!

Simulated R

_eq

x V

_DD

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MOSFET

The Transistor as a Switch

V_DD (V) 1 ^1.5 ² ^2.5

NMOS (kΩ) 35 19 15 13

PMOS (kΩ 115 55 38 31

R

_eq

of NMOS and PMOS Transistors in 0.25 µm (W/L=1, L=L

_min

)

For larger devices, divide R_eqby W/L

(16)

MOSFET

Dynamic Response of MOS Transistor

 

Is a function of time it takes to (dis)charge:

  its intrinsic capacitances

  interconnect lines and load capacitances

 

Origin of intrinsic capacitances:

  The basic MOS structure

  The channel charge

  The depletion regions of reverse-biased pn-junctions of drain and source

 

Capacitance values depends on the applied voltages

(nonlinear capacitors)

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MOSFET

MOS Gate Capacitance

 

If:

  No lateral diffusion

  Transistor in cut-off

C

_gate

= C

_ox

^x WL

where C

_ox

= ε

_ox

t

_ox

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MOSFET

MOS Structure Capacitances

t

_ox Gate oxide

L

Gate-bulk overlap Polysilicon gate

L

_d

W Top view

Cross section

x

_d

x

_d

Lateral diffusions (Area =

x

_d^{x W)}

L_d = designed length; L = effective length

Overlap capacitances (linear):

C_GS0 = C_GD0 =

= C_ox x_d W = C₀ W

where C₀= C_gs0 or C_gd0 = overlap capacitance per

unit transistor

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MOSFET

Gate Capacitance (Piece-Wise Linear Model)

Most important regions in digital design: saturation and cut-off

Cut-off Linear Saturation

Operation region

C_GCB C_GCS C_GCD C_GC

= C_GCB +C_GCS +C_GCD

C_G

Cutoff C_oxWL 0 0 C_oxWL C_oxWL + 2C_oWL

Linear 0 C_oxWL/2 C_oxWL/2 C_oxWL C_oxWL + 2C_oWL

Saturation 0 (2/3) C_oxWL 0 (2/3) C_oxWL (2/3) C_oxWL + 2C_oWL

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MOSFET

Gate Capacitance

C_GCas a function of V_GS (V_DS = 0 thus, linear mode)

C_GCas a function of the degree of saturation

V_T Transistor is off

(cap between gate and body) Degree of saturation

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MOSFET

Junction Capacitances (Diffusion Capacitances)

Bottom

Side wall

Channel Source

N_D

Channel-stop implant N_A+

SubstrateN_A W

x_j

L_S

(22)

MOSFET

MOS Capacitances

p-substrate

S

n

⁺

n

⁺

Field oxide

substrate (bulk) contact

G D

C_GS C_GD

C_SB C_GB C_DB

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MOSFET

MOS Capacitances

Consider as NMOS transistor with the following parameters:

t

_ox

= 6 nm L= 0.24 μm W= 0.36 μm L

_D

=L

_S

= 0.625 μm C

₀

= 3 x 10

^-10

F/m

C

_j0

= 2 x 10

^-3

f/m2

C

_jsw0

= 2.75 x 10

^-10

F/m

Determine the zero-bias value of all relevant capacitances.

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MOSFET

Capacitances in a 0.25 µm CMOS Process

C_ox

(fF/μm²)

CGD0 (fF/μm)

CJ (fF/μm²)

m_j Φ_b (V)

CJSW (fF/μm)

m_jsw Φ_bsw

(V)

NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9

PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9

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MOSFET

1.  RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B.

Digital Integrated Circuits: a design perspective.

2

^nd

Edition. Prentice Hall, 2003. ISBN:

0-13-090996-3.

2.  WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective.

Addison-Wesley, 4

^th

Edition, 2010. ISBN 978-0321547743.

References

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MOSFET

References

3.  MURTHY, R S Ananda. A Simplified Introduction to Circuit Simulation using SPICE OPUS. September 2004. Disponível em http://fides.fe.uni-lj.si/spice/documentation.html

Integrated Circuits & Systems

Lecture 11

MOSFET – part 2

Prof. José Luís Güntzel

[email protected]

Integrated Circuits & Systems

Federal University of Santa Catarina

MOSFET

I D -V DS Characteristics of NMOS (I-V Curves)

MOSFET

I D -V GS Characteristics of NMOS (I-V Curves)

quadratic

quadratic linear

MOSFET

I D -V DS Characteristics of PMOS

MOSFET

NMOS x PMOS (I-V Curves)

MOSFET

Simple Model for Manual Analysis

A Single Current Source Using First-Order Expressions

€

k'

€

λ

€

γ

MOSFET

Simple Model versus Spice

MOSFET

Parameters for Manual Analysis

€

λ

€

γ

MOSFET

Experimental setup

V

V

Determining the I-D Curves of PMOS

MOSFET

• Circuit description (SPICE) – PMOS1.cir

– http://www.inf.ufsc.br/~guntzel/ine5442/parametros

Determining the I-D Curves of PMOS

Also available NMOS1.cir

MOSFET

Determining the I-D Curves of PMOS

MOSFET

The Transistor as a Switch (“Zero-Order Model”)

MOSFET

The Transistor as a Switch (“Zero-Order Model”)

MOSFET

The Transistor as a Switch

Simulated R

x V

MOSFET

The Transistor as a Switch

R

of NMOS and PMOS Transistors in 0.25 µm (W/L=1, L=L

)

MOSFET

Dynamic Response of MOS Transistor

Is a function of time it takes to (dis)charge:

 its intrinsic capacitances

 interconnect lines and load capacitances

Origin of intrinsic capacitances:

 The basic MOS structure

 The channel charge

 The depletion regions of reverse-biased pn-junctions of drain and source

Capacitance values depends on the applied voltages

(nonlinear capacitors)

MOSFET

MOS Gate Capacitance

If:

 No lateral diffusion

 Transistor in cut-off

C

= C

x WL

where C

= ε

I _D -V _DS Characteristics of NMOS (I-V Curves)

I _D -V _GS Characteristics of NMOS (I-V Curves)

I _D -V _DS Characteristics of PMOS

•  Circuit description (SPICE) – PMOS1.cir

–  http://www.inf.ufsc.br/~guntzel/ine5442/parametros

  its intrinsic capacitances

  interconnect lines and load capacitances

  The basic MOS structure

  The channel charge

  The depletion regions of reverse-biased pn-junctions of drain and source

  No lateral diffusion

  Transistor in cut-off

^x WL

1.  RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B.

2.  WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective.