Performance Analysis Of VLSI Implemented Various WSN Security Algorithms

Performance Analysis of VLSI Implemented

Various WSN Security Algorithms

Pooja Srivastava,S. C. Bose

Abstract: The VLSI implemented security algorithms and various security issues with their solutions for WSNs have been discussed. The comparative study has been given which has based on clock frequency, latency, data conversion rate, area occupied and power consumption. The proposed research can be implemented in many areas of anolog/digital circuit design, with ultra low power applications. The impact of research work would be to investigate the applicability of existing security schemes for WSNs and to enhance the development of resource efficient, robust and having low power dissipation security algorithms.

Index Items : VLSI Design, FPGA, ASIC, VHDL, Security Algorithms of WSNs i.e. AES, DES etc

——————————  ——————————

I INTRODUCTION

Wireless Sensor Networks (WSNs) are very useful and in use in various applications like security, structural monitoring, disaster monitoring etc. In these networks, individual sensor node mainly comprises of sensor, its signal conditioning/processing electronic circuits, transreceiver block besides other supportive circuitry. The transmission protocol (software) are partly embedded in the individual node and in the network, comprising of several such nodes connected to host computer without being wired. Besides other issues in WSN such as routing, architecture, fault tolerance, network lifetime, energy efficiency, latency, scalability and accuracy etc., security of data transmission is an important issue. For this purpose, various algorithms are available such as Data Encryption Standard (DES) Algorithm, Advanced Encryption Standard (AES) Algorithm, International Data Encryption Algorithm (IDEA), Scalable Encryption Algorithm (SEA) and Clustering Algorithm etc. and the new ones are being explored. The hardware for such algorithms is typically first implemented/tested on Field Programmable Gate Array (FPGA) before implementing through Application Specific Integrated Circuit (ASIC) as per requirement. All these nodes are required to be deployed in remote and/or unattended location and they are desired to remain continuously operational for a long time as much as possible. Therefore, the nodes while retaining or improving the performance ability must also consume as less energy as possible. These two parameters besides data transmission protocol mainly pertain to the electronic circuitry or integrated circuit (IC) used in such nodes. The architecture of the circuit, the type of transistors used and the technology of the IC are the deciding factors of performance and energy consumption [1; 2]. In this paper, the approach of WSN with its applications and critical issues will be discussed. The important features of various WSN security algorithms will be explored and compared with the help of their FPGA/ASIC implemented results.

II WSN AND THEIR SECURITY ISSUES

WSN faces a lot of problems related to security, routing, quality of service and energy saving. This research work is proposed to be based on security issues in WSN and their possible solutions. The basic security goals and tasks are Confidentiality, Availability, Integrity, Authentication and Non-repudiation. The attacks are divided into well known classifications like Passive attacks (Traffic Analysis, Impersonation) and Active attacks (Sinkhole attacks, Sybil attacks, Denial of Service and Data modification) and Physical attacks (Device cloning, Device theft). The solutions have been provided by various types of algorithms like DES, AES, IDEA, SEA, and Clustering Algorithm etc. Figure 1 shows the applications of WSN in military.

Figure 1: Examples of WSNs [3]

III CLASSIFICATIONS AND PERFORMANCE

METRICES OF WSN ALGORITHMS

To encrypt and decrypt the original information from the hackers and unauthorized access, Cryptography Techniques provides solutions.The cryptography process is obligatory for protection of the user data so that only the permitted user is allowed to access it. The classifications of WSN security algorithms have been proposed and have shown in figure 2.

_________________________________

 Pooja Srivastava, S. C. Bose

 Assistant Professor, Department of Electronics, School of Physical Science, Banasthali Vidyapith, Rajasthan-304022

2940 Figure 2: Classifications of WSN Security Algorithms

Symmetric/Secret Key Algorithms provides same encryption and decryption keys and these algorithms are fast and less complex in nature. On the other hand, Asymmetric Algorithm/Private Key provides different keys for encryption and decryption process. In these algorithms, receiver have special private key. These algorithms are more secure and more complex than symmetric algorithms. Hash algorithms uses long input message but short block as output known as hash or message digest. Now a days, due to increasing demand of compact and energy efficient hardware implementation, the researchers are focusing on Light Weight Algorithms.

PERFORMACE METRICES

The selection of appropriate security algorithms is a critical task for researchers. The performance metrics includes data size, key size, processing time, level of security, execution rounds, key scheduling, area, and power consumption. Now, in this paper, VLSI architectures have been explored for various security algorithms.

IV VLSI ARCHITECTURE OF WSN SECURITY

ALGORITHMS

A. SYMMETRIC ALGORITHMS

1. Data Encryption Standard (DES) Algorithm

DES is a well known standard symmetric algorithm and it has 64 bit block cipher so that DES is able to encrypt 64 bit data at a time and 56 bit key. DES is not stream cipher in which one bit or some group of bits can be encrypted at a time. It is developed by International Business Machines (IBM) based on the key cipher LUCIFIER and useful modifications incorporated by National Security Agency (NSA) and standardized by National Bureau of Standards (NBS) in 1977 [4; 5; 6].

DES is based on S-boxes and Feistel Block Cipher but the non-linearity associated with S-boxes has not been explained by NBS. DES has extremely less key size of 56 bits that has not appropriate for robust system. The developer team of DES did not explained the reason that why they have chosen key size of 56 bits and rest of 8 bits for parity checking. In 1994, National Institute of Standard & Technology (NIST) has reaffirmed DES for Government use for further 5 years more. DES is based on bit-shuffling, non-linear substitutions (S-boxes) and Ex-OR operations using Feistel Network. DES is also property of Avalanche Effect that depicts if any little change will introduce in plain text or in key then it will produce great change in cipher text. The figure 3 has depicted the flow diagram of DES algorithm.

Figure 3: Flow diagram of DES Algorithm [4]

In 1990, Differential Cryptanalysis attack has been investigated by Biham and Shamir [7] against DES (256 chosen ciphertexts), in 1993, Linear Cryptanalysis attack has been applied by Matsui on DES (243 chosen ciphertexts). The new mathematical descriptions to implement and optimize DES in an FPGA have given by Matsui [8]. In 2000, the key search engine and distributed search have been investigated against DES. In 2006, Reconfigurable Search Machine COPACOBANA has been used to break DES with 120 FPGAs in 6.4 days. Knudsen et al. performed three chosen-Plaintext Linear attack [9]. The modified architecture of DES algorithm is depicted by figure 4:

Figure 4: The DES Algorithm [10]

Recently, Rouvroy et al. have dealed with Linear cryptanalysis attack and provided better results against Matsui attack [10]. Robertson et al. have provided ASIC implementation results of DES algorithm having throughput of 6.5 Gb/s using HP 8000 computer aided system with 0.6 μm CMOS technology [11].

2. Advanced Encryption Standard (AES) Algorithm

AES is also well established standard which adopted by NIST and replaced DES algorithm in 2000 after 30 years of DES establishment. AES has key size variants of 128,192 and 256 bit and has defined as symmetric cipher for non-classified materials. In AES, larger key size provides more secure system but according to hardware point of view, larger key size will require larger area and provide lower throughput. In FPGA and ASIC implementation, there will be trade-offs between area, throughput and security level. AES offers optimized area, high throughput, high efficient, high speed and WSN Security Algorithms

Hash Algorithms Symmetric

Algorithms

Asymmetric Algorithms

high level of security than DES. AES is a symmetric algorithm based on Block Cipher and performs Sub Bytes, Shift Row, Mix Column, Key Addition transformations in encryption process. The input for each state is known as State and for each round Round Key will be changed. The non-linearity will be introduced by Sub-Bytes operation. The decryption process used Inverse Block Cipher which is based on Inverse Sub Bytes, Inverse Shift Row, Inverse Mix Column and Inverse Key Addition transformations. The overview of AES algorithm has been shown by figure 5.

Figure 5: The Overview of AES Algorithm

Adib et al. have proposed the hardware implementation of AES algorithm using VHDL language and Xilinx ISE 9.1 simulator. They used the application of T-Box Lookup Table for combination of Sub-Bytes and Mix-Column [12]. Verbauwhede et al. have performed ASIC implantation of AES algorithm and its performance. The encryption chip has delivered 2.29 GB/s of encryption throughput. They have used AES Rijendael algorithm, with different samples of this chip

[13]. Haghighizadeh et al. have proposed compact 8-bit AES crypto-processor for both encryption and decryption process. They have used 0.18 μm standard-cell CMOS technology. The results reported that throughput is 203 Mbps [14].

3. Secure And Fast Encryption Routine (SAFER+) Algorithm

James L. Massey at the ETH Zurich have developed SAFER+ algorithm which is based on SAFER ciphers, which comprises the ciphers SAFER K-64,SAFER K-128, SAFER SK-128 with Pseudo-Hadamard-Transformation (PHT) for the desired diffusion [15]. Equation 1, 2 and 3 have shown the two byte transformations and key schedule of SAFER+.

i 2i 2i+1

i 2i 2i+1

yi = S[x

sk ] + sk

(1)

yi = S^-1 [x + sk ]

sk

(2)

sk[i] = kb[i]+ek[(i/16+(i mod 16)) mod (n+1)] (3)





SAFER+ algorithm uses 8 loops in single round of execution. It is having a input register which combines feedback data from previous data and plaintext with SAFER+ cipher of single round. Sarmila et al. have proposed new approach for SAFER+ and have provided better results than pipelined AES with throughput of 1096.035 Mbps and frequency of 77.065 MHz [16]. Now a days, several Multi-set attack and

Boomerang attack are threatening to SAFER+ due to its weakness of key scheduling process [17; 18].

4. International Data Encryption Algorithm (IDEA) Algorithm

IDEA algorithm has been considered as post DES algorithm due to high immunity to attacks and it has plaintext 64 bit of length and key size 128 bit long and introduced by Lai and Massey in 1991. IDEA is a symmetric, block-oriented cryptographic algorithm and immune to brute-force attacks. Thaduri et al. have implemented IDEA algorithm using VHDL and AMI 0.5 process technology. They have optimized modulus multiplier by using Wallace Tree Multiplier and Booth Multipiler and exploited temporary parallelism [19]. Chaudhari et al. have implemented the IDEA algorithm based on modular arithmetic components using VHDL language and Xilinx ISE 9.1 simulator. The results show that it can be used in very high speed and low power algorithms [20]. Tigli have provided area sufficient ASIC implementation of IDEA algorithm by using pipelined approach and bit parallel approach in the submodules. The resilts are throughput of 193.9 Mbits/sec. and frequency of 10 MHz (in worst case) [21].

Figure 6: The Block Strcture of IDEA ICs [22]

Sklavos et al. have performed asynchronous ASIC implementation of IDEA algorithm and provided better results than synchronous design with respect to frequency and power consumption. The figure 6 has depicted the block description of IDEA ICs0.6 μm CMOS technology [22]. The IDEA has been tested by Differential, Differential-linear, Square, and Impossible Differential attack and in result, some rounds have broken by these attacks. Now a days, Meet-in- middle attack have become more dangerous for IDEA execution [23; 24].

5. Blowfish Algorithm

Blowfish has considered as a optimized symmetric block cipher algorithms based on Feistel cipher. It uses 64 bits block and 448 bits key with 16 rounds. It has a lengthy key schedule, P table and four large S-boxes which requires embedded RAM [25; 26; 27]. Blowfish algorithm uses 16 round Feistel network, in which F function is the part of private key so that safety of this F Function is a critical task. Reflection attack and differential attack provide high threaten to this algorithm [28].

B HASH ALGORITHMS

2942

All message digest algorithms like MD2, MD3 and MD5 have proposed by Ron Rivest. It is a blocked chaining algorithm based on Hash Message Authentication Code (HMAC) and more secure than symmetric algorithms but not secure by Birthday Attack. In MD5, message is processed in 512 bits (padding also) and output is of 128 bit hash [29; 30]. MD5 consists of following Steps 1. Appending Padding Bits 2. Appending Length 3. Buffer Initialization 4. Processing the message 5. Output. Equation 4 has given the flow of MD5 and here A, B, d and D are 32 bits registers.

A = B+((A+Func(B,C,D)+Xj[k]+T[i])≪s) (4)

A←D, B←A, C←B, D←C

The whole function F has been explained by equation 5:

F(X,Y,Z) = (X ∧Y)∨(￢X ∧Z)

G(X,Y,Z) = (X ∧Z)∨(Y ∧￢Z)

H(X,Y,Z) = X ⊕ Y ⊕ Z

I(X,Y,Z) = Y ⊕ (X ∨￢Z) (5)

7. Secure Hash Algorithm 256 (SHA-256)

SHA-256 uses message as less than 264 bits and output as message digest of 256 bits. It is more secure than Birthday Attack. The steps are mostly same as other hash algorithms but it will use compression process. Ting et al. have proposed shift register based architecture of SHA-256 and provided results of 87 MB/s. Due to handshaking tasks, performance will be degraded so they have suggested new solutions for these problems [31].

B .ASYMMETRIC ALGORITHMS

8. RSA Algorithm

RSA has been introduced in the year 1978 by Ron Rivest, Adi Shamir and Leonard Adleman. It is based on modular arithmetic and exponentiation involving large prime numbers. The steps involved in RSA are finding large prime numbers, finding the public key (e), determine the private key (d), encryption and decryption. Haija et al. have proposed solution to speed up the modular multiplication. The experiments have been performed on different FPGA and resulted maximum frequencies of 15.725 MHz, 17.629 MHz respectively [32]. Daly et al. have provided pipelined architecture [33]. Recently, RSA has been used in cloud computing and digital image processing applications.

b. LIGHT WEIGHT ALGORITHMS

Block Cipher is the well known candidate of WSN security networks. Hardware implementation of Block Cipher faces critical issues like limited amount of power availability and area. The concept of Light Weight Algorithms have been

arised to find compact implantation and high throughput. Some algorithms have been discussed in this paper.

9. DES Light Weight Extension (DESL) Algorithm

Biham et al. have proposed the methods to strengthen DES against Linear, Differential, Exhaustive Attacks and improved Davies’ Attacks [34]. They have proposed the new architecture of DES which has based on key dependent invariant S Transformations [35]. DES Light Weight Extension (DESL) is a new block cipher which is strong, efficient and compact. It uses single S box for 8 times and used in Radio Frequency Identification (RFID) applications. Poschmann et al. have proposed Light Weight implementation of DESL better than AES [36]. They have used 0.18 µm technology and found 0.89 µA current at 100 KHz. Leander et al. have provided best results of 5.55 Kbps at 100 KHz [37].

250 known plaintexts and 2 ~~ complexity of

10. PRESENT Algorithm

Present is Ultra Light Weight Block Cipher which is using 64 bit state and 128 bit key places. In the research of low cost cryptography, PRESENT have provided better results than others and used only 2280 Gate Elements.

Figure 7: Architecture of PRESENT Algorithm [38]

Bogdanov et al. have implemented PRESENT algorithm using SP network and 31 rounds. The architecture has been shown in figure 7. They have already tested PRESENT against different attacks and Time Memory Trade-offs (TMTO) [39].

V PERFORMANCE ANALYSIS

In this paper, the various security algorithms have been explored and after exhaustive analysis, the comparative analysis has been given for different algorithms using their basic features, applications, data size, key size and their associated challenges in the table 1. Firstly, partial FPGA/VHDL implementation have been compared in table 2 which is based on critical performance metrics ie. throughput, operating frequency and area details. Next table 3 have discussed some ASIC implemented results available in research. Some famous algorithms have also discussed in table 4, whose ASIC implantation is not available in research.

Table 1: Comparison between Different WSN Security Algorithms

S. No

Algorith ms

History & Developer

I/O (bits)

Key

Agency (bits)

Symmetric Algorithms:

1. DES 1970 (IBM,

NSA, NBS) 64 56

Symmetric Algorithm, S-boxes, Feistel Block

Cipher, Used 16 rounds, Avalanche Effect

General Purpose Block Oriented Transmission, Authentication, Speech, Encrypted Data Storage,

Secure Video Surveillance, Electronic Financial Transactions, Remote Access, Secure

internet,

Non-linearity of S-Boxes, Extremely less Key Size of 56 bits, No Satisfactory Explanation of Design

Criteria of DES and Use of Parity bits of 8 bits.

3. AES NIST in

2000 128

128/ 192/ 256

Symmetric Algorithm, Memory Used, Lookup

Table Sub Bytes, Shift Row,

Mix Column, Key addition Block Cipher & Secure

against Brute-Force Attack & Cryptanalysis

Attack

Bluetooth Devices , Smart Card Application

Side-Channel Attack, Cache-timing Attack, Adi-Shamir Cube Attack

3. SAFER+ James L. Massey K-64, K-128, SK-128 Byte-oriented-block Encryption Algorithms, Pseudo-Hadamard-Transformation

Bluetooth, Smart Card Application

Weakness of Key Schedule, Multi-set Attack and Boomerang Attack

4. IDEA

Lai and Massey in

1991

64 128

Block cipher, Symmetric Key, Mixing

Operations on Different Algebraic groups, Networked Instrumentation & Distributed Measurement Systems,

Audio and Video Data

Meet-in- middle Attack

5. Blowfish - 64 32 to 448

Feistel cipher, 4 Large S-Tables and Large

Recursive Key Schedule

Optimized for the Pentium’s 4Kbyte Cache

Differential Attack & Reflection Attack

Hash Algorithms:

6. MD5 Ron Rivest

Less than 264 bit messa ge and 128 bit- messa ge digest output Blocked Chaining Hash Algorithm HMAC –Hash Massage Authentication Code, Public Key

Chaining with AES used in IoT Applications,

IPSEC- VPN

Birthday attack

7.

SHA-256 NIST

Less than 264 bit messa ge and 256 bit- messa ge digest output

Hash Algorithm. 1. Message Scheduler

2. Compression Fuction 3. Intermediate

Hash

Digital Signatures, Message Authentication

Code, Increase entropy in Pseudo Random Number Generators

Asymmetric Algorithms:

8. RSA

2014 (Ron Rivest, Adi Shamir, Leonard Adleman) 32 bit size

Public Key Algorithm, Asymmetric Algorithm,

1. random two prime numbers, 2.parallel multiplication

of the prime numbers and their 3.decremented values,

Digital Signatures, Internet, PGP & GPG

Algorithms

Not meet to WSNs constraints

Light Weight Algorithms:

9. DESL

DES Light Weight Extension

Light Weight Block Cipher,

Low Power Applications, RFID Tags, Sensors and

Smart Cards Applications

Not suitable for Ultra Light Weight Application

2944

. NT 128 Block Cipher, LUTs

used, Substitution and Permutation Network

RFID, Sensors and Smart Cards

Applications

Hardware Attacks, Time Memory Trade-offs (TMTO)

Table 2: Performance Study based on VHDL/FPGA Implementation Results

S. No .

Algorithms Author & References FPGA Used Speed or Throughput or Data Conversion Rate

Operating Frequency or System Clock Frequency

Slices Area LUTs Register s

Symmetric Algorithms:

1. DES

[10]; IEEE XC2V1000-5/6 14.5 Gbps (21 pipelined _stage) 227 MHz - - 4255 2424

[10]; IEEE XC2V1000-5/6 21.3 Gbps (37 pipelined

stage) 333 MHz - -

4245

4128

2. AES [12] ; IJRES

Virtex XC5VLX50

426,08 Mbps

For Key Size: 128 bits 346,194 MHz 587 - - - Virtex

XC5VLX50

320,35 Mbps

For Key Size: 192 bits 315,348 MHz 746 - - - Virtex

XC5VLX50

263,91 Mbps

For Key Size: 256 bits 321,642 MHz 1140 - - -

3. SAFER+ [16] (ICGST-CNIR) - 1096.035 Mbps 77.065 MHz - - - -

4. IDEA [19] (Elesvier) EPF10K70RC

240 >700 Mbps 10 MHz -

1.95

mm2 - -

5. Blowfish [25] Altera APEX

20K 400 -1 - 40 MHz -

1200

LCs - -

Hash Algorithms:

6. MD5

[30]

[29]

Xilinx Virtex-II XC2V4000-6 FPGA

Virtex V1000FG680– 6

586 Mbps

165 Mbps

354 Mbps

21 MHz

71.4 MHz

647

-

-

-

-

-

-

-

7. SHA-256 [31] XCV300E-8 87 MB/s 88 MHz 1261

Asymmetric Algorithms:

8. RSA [32] (Elsevier)

ALTERA Cyclone IV EP4CE115F2 9C7

VERTIX VII VC707 FPGA

-

15.725 MHz

17.629 MHz

10427

9414

Light Weight Algorithms:

9. DESL [37] (Springer) 5.55 Kbps 100 KHz 1848

(GEs) 10

. PRESENT [38] (Springer) 200 Kbps 100 KHz

1570 (GEs)

Table 3: Performance Study based on ASIC Implementation Results

S.No Algorithms Author &

References Technology Used Throughput Power Fabrication Laboratory

1. DES [11] IEEE 0.6 μm CMOS

technology 6.5 Gb/s.

Sandia's Microelectronics Development Laboratory

2 AES

[13]. IEEE

0.18-/spl mu/m CMOS standard cell technology

2.29 GB/s 56 mW -

[14]. IEEE

0.18 μm standard-cell CMOS technology

203 Mbps 49 μW/MHz at

128 MHz -

3. IDEA [21] Lsi_10k synthesis

libraries (worst

193.9

case)

Lsi_10k synthesis libraries (best resuit)

77.5 Mbits/s 40 MHZ -

[22]

0.6 μm CMOS technology (best case)

- _58mW -

0.6 μm CMOS technology (worst case)

41.25mW

Table 4: List of WSN Security Algorithms whose VLSI Implementation is not available in the literature

S.

No. Algorithms

Authors &

References Tools/Languages Specifications

1. SIT [40] (IJACSA) Matlab

Secure IoT, Light Weight Encryption Algorithm, 64 bit block cipher with 64 bit key size, Substituion and Permutation Network

2. Clustering

[41] (International Journal of Computer Systems )

[42] (IPCSIT)

Matlab

NS2

Energy Efficient Method, Multi-objective Genetic Algorithm,

Secure Clustering Algorithm based on Reputation (SCAR)

3. RC-6 [43] (_IJAERS) Java Platform 128 bit block with 128/192/256 bits Key Size, used in smart _sensors

4. GRNN [44] (IEEE) Matlab

2946

VI CONCLUSION

The inferences produced by this research paper are based on the analysis of attack handling capability of any algorithms. In early 1970, researchers used only symmetric algorithms but day by day more secure algorithms have been investigated in

research. In 1970, DES has been standardized by U.S. government under the research project named Clipper Project but after decade of years (30 years), DES has been replaced by AES. The explanation of design criteria of DES functioning has never been published and it was not fully secure by Cryptanalysis. AES have large key space and high computational capability so that Brute-Force attack are unable to threaten to AES. The Biclique attack and Cryptanalysis attack are also not create problems for AES due to its property of having nonlinear key schedule, by these reasons AES is more secure than DES. But due to physical limitations, AES is not secure against Side-channel attack, Adi-Shamir Cube attack and Cache-timing attack. SAFER+ provides better security approach against pipelined-AES but it suffers from weakness of key schedule problems. IDEA has been developed by Messey et al. and has more resistant to known attacks but Meet-in –middle attack has created more problems for IDEA. In Blowfish algorithm, F function is a weak part and prone to Reflection attack and Differential attack. After symmetric algorithms, hash algorithms like MD4, MD5, and SHA-256 etc. have been evolved in research. They are more secure and complex than symmetric algorithms for IPSEC applications. Results shows that SHA-256 has better immunity against other hash algorithms. Now a days, The researchers are focusing on Light Weight Algorithms like DESL, ,PRESENT etc. All the algorithms are designed for resource constraints systems but DESL is not suitable for Ultra-light systems. Time Memory Data Attacks, and Time Memory Trade-offs (TMTO) problems are the challenges for Light Weight Algorithms.

VII FUTURE SCOPE

The impact of research work would be to investigate the applicability of existing security schemes for WSNs, and to enhance the development of resource efficient, robust and having low power dissipation security algorithms. The researchers can give more focus on ASIC implementation of Clustering, GERN, SIT, RC6 and other algorithms.

VIII ACKNOWLEDGEMENTS

This work is supported by Department of Electronics, Banasthali Vidyapith, Rajasthan, India and IoT Group, CSIR-CEERI, Pilani, India.

REFERENCES

[1] [1]Moore, G. E. (1975). Progress in digital integrated electronics. IEDM Tech. Digest, 21,11-13.

[2] [2] ITRS 2012 Executive Summary. ITRS.[Online]. Available: http://www. itrs. net/Links/2012ITRS/Home2012. htm.

[3] [3] http://www.atacwireless.com/adhoc.html. 2005. [4] [4] www.facweb.iitkgp.ernet.in/~sourav/DES.pdf.

2012.

[5] [5] www.cs.ucsb.edu/~koc/ns/docs/slides/03-des.pdf. 2012.

[6] [6]www.site.uottawa.ca/~chouinar/Handout_CSI41 38_DES_2002.pdf. 2002.

[7] [7] Biham, E., & Shamir, A. (1991). Differential cryptanalysis of DES-like cryptosystems. Journal of CRYPTOLOGY, 4(1), 3-72.

[8] [8] Matsui, M. (1994, August). The first experimental cryptanalysis of the Data Encryption Standard. In Annual International Cryptology Conference (pp. 1-11). Springer, Berlin, Heidelberg.

[9] [9] Knudsen, L. R., & Mathiassen, J. E. (2000, April). A chosen-plaintext linear attack on DES. In International Workshop on Fast Software Encryption (pp. 262-272). Springer, Berlin, Heidelberg.

[10][10] Rouvroy, G., Standaert, F. X., Quisquater, J. J., & Legat, J. D. (2003). Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis. IEEE Transactions on Computers, 52(4), 473-482.

[11][11] Robertson, P. J., Pierson, L. G., & Witzke, E. L. (2003). Data encryption standard ASIC design and development report (No. SAND2003-3867). Sandia National Laboratories.

[12][12] El Adib, S., & Raissouni, N. (2012). AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key. International Journal of Reconfigurable and Embedded Systems (IJRES), 1(2), 67-74.

[13][13] Verbauwhede, I., Schaumont, P., & Kuo, H. (2003). Design and performance testing of a 2.29-GB/s Rijndael processor. IEEE Journal of Solid-State Circuits, 38(3), 569-572.

[14][14] Haghighizadeh, F., H. Attarzadeh, and M. Sharifkhani. "A compact 8-bit AES crypto-processor." In Computer and Network Technology (ICCNT), 2010 Second International Conference on, pp. 71-75. IEEE, 2010.

[15][15] J.L.Massey,(1999) ―On the Optimality of SAFER+Diffusion‖, Second Advanced Encryption Standard Candidate Conference (AES2), Rome, Italy, March 22-23.

[16][16] Sharmila, D., & Neelaveni, R. (2009). Performance Evaluation of VHDL Implementation of SAFER+ and AES algorithm for Bluetooth security system. ICGST-CNIR Journal, 9(1). [17][17] Kelsey, J., Schneier, B., & Wagner, D. (1999,

March). Key schedule weaknesses in SAFER+. In Second AES Candidate Conference.

[18][18] Biryukov, A., De Canniere, C., & Dellkrantz, G. (2003, August). Cryptanalysis of SAFER++. In Annual International Cryptology Conference (pp. 195-211). Springer, Berlin, Heidelberg.

[19][19] Thaduri, M., Yoo, S. M., & Gaede, R. (2005). An efficient VLSI implementation of IDEA encryption algorithm using VHDL. Microprocessors and Microsystems, 29(1), 1-7.

[21][21] Tigli, O. (2003). Area efficient ASIC implementation of IDEA (International Data Encryption Standard). Best design for ASIC implementation of IDEA, GMU.

[22][22] Sklavos, N., Papakonstantinou, A., Theoharis, S., & Koufopavlou, O. (2002). Low-power implementation of an encryption/decryption system with asynchronous techniques. VLSI Design, 15(1), 455-468.N

[23][23] Biham, E., Biryukov, A., & Shamir, A. (1999, March). Miss in the Middle Attacks on IDEA and Khufu. In International Workshop on Fast Software Encryption (pp. 124-138). Springer, Berlin, Heidelberg.

[24][24] Biham, E., Dunkelman, O., Keller, N., & Shamir, A. (2015). New attacks on IDEA with at least 6 rounds. Journal of Cryptology, 28(2), 209-239.

[25][25] Honig, D., Colophon, C., & Core, B. (2000). Blowfish & IDEA in Silicon.

[26][26] Lin, M. C. J., & Lin, Y. L. (2000, January). A VLSI implementation of the blowfish encryption/decryption algorithm. In Proceedings of the 2000 Asia and South Pacific Design Automation Conference (pp. 1-2). ACM.

[27][27] Schneier, B. (1993, December). Description of a new variable-length key, 64-bit block cipher (Blowfish). In International Workshop on Fast Software Encryption (pp. 191-204). Springer, Berlin, Heidelberg.

[28][28] Kara, O., & Manap, C. (2007, March). A new class of weak keys for blowfish. In International Workshop on Fast Software Encryption (pp. 167-180). Springer, Berlin, Heidelberg.

[29][29] Deepakumara, J., Heys, H. M., & Venkatesan, R. (2001). FPGA implementation of MD5 hash algorithm. In Electrical and Computer Engineering, 2001. Canadian Conference on(Vol. 2, pp. 919-924). IEEE.

[30][30] Jarvinen, K., Tommiska, M., & Skytta, J. (2005, January). Hardware implementation analysis of the MD5 hash algorithm. In System Sciences, 2005. HICSS'05. Proceedings of the 38th Annual Hawaii International Conference on (pp. 298a-298a). IEEE.

[31][31] Ting, K. K., Yuen, S. C., Lee, K. H., & Leong, P. H. (2002, September). An FPGA based SHA-256 processor. In International Conference on Field Programmable Logic and Applications (pp. 577-585). Springer, Berlin, Heidelberg.

[32][32] Haija, Q. A., Smadi, M., Ja’fari, M., &

Al-Shua’ibi, A. (2014). Efficient FPGA implementation of RSA coprocessor using scalable modules. Procedia Computer Science, 34, 647-654.

[33][33] Daly, A., & Marnane, W. (2002, February). Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. In Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays (pp. 40-49). ACM.

[34][34] Biham, E., & Biryukov, A. (1997). An improvement of Davies’ attack on DES. Journal of Cryptology, 10(3), 195-205.

[35][35] Biham, Biryukov,: How to Strengthen DES Using Existing Hardware. In: Safavi-Naini, R., Pieprzyk, J.P. (eds.) ASIACRYPT 1994. LNCS, vol. 917, Springer, Heidelberg (1995), available for download at citeseer.ist.psu.edu/biham94how.html [36][36] Poschmann, A., Leander, G., Schramm, K., &

Paar, C. (2007, May). New light-weight crypto algorithms for RFID. In Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (pp. 1843-1846). IEEE.

[37][37] Leander, G., Paar, C., Poschmann, A., & Schramm, K. (2007, March). New lightweight DES variants. In International Workshop on Fast Software Encryption (pp. 196-210). Springer, Berlin, Heidelberg.

[38][38] Bogdanov, A., Knudsen, L. R., Leander, G., Paar, C., Poschmann, A., Robshaw, M. J., ... & Vikkelsoe, C. (2007, September). PRESENT: An ultra-lightweight block cipher. InInternational Workshop on Cryptographic Hardware and Embedded Systems (pp. 450-466). Springer, Berlin, Heidelberg.

[39][39] Biryukov, A., Mukhopadhyay, S., & Sarkar, P. (2005, August). Improved time-memory trade-offs with multiple data. InInternational Workshop on Selected Areas in Cryptography(pp. 110-127). Springer, Berlin, Heidelberg.

[40][40] Usman, M., Ahmed, I., Aslam, M. I., Khan, S., & Shah, U. A. (2017). Sit: A lightweight encryption algorithm for secure internet of things. arXiv preprint arXiv:1704.08688.

[41][41] Peiravi, A., Mashhadi, H. R., & Hamed Javadi, S. (2013). An optimal energy‐efficient clustering method in wireless sensor networks using multi‐objective genetic algorithm. International Journal of Communication Systems, 26(1), 114-126.

[42][42] Yu, Y., & Zhang, L. (2012). A Secure Clustering Algorithm in Mobile Ad Hoc Networks. In 2012 IACSIT Hong Kong Conferences IPCSIT vol. 29 (2012), IACSIT Press, Singapore, 73-77. [43][43] Sisat, S. N., & Honade, S. J. Security and

Privacy in Wireless Sensor Network Using RC6 Algorithm.